JP4939735B2 - Semiconductor integrated circuit device - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit device and a method for manufacturing the same, and more particularly to a technique effective when applied to a semiconductor integrated circuit device in which elongated element formation regions are formed in parallel.

  A semiconductor integrated circuit device includes elements and wirings formed on the main surface of an element formation region (active) partitioned by an insulating film. This element formation region is separated from other element formation regions by an element isolation region, for example, and this element isolation region is formed by, for example, an element isolation insulating film. The element isolation insulating film is formed using, for example, an STI (Shallow Trench Isolation) technique. In this STI, an insulating film such as a silicon oxide film is deposited on the upper part of the groove formed in the semiconductor substrate, and the silicon oxide film outside the groove is removed by a chemical mechanical polishing (CMP) method or the like. A silicon oxide film is embedded in the groove and used for isolation between elements.

  For example, a memory LSI (Large Scale Integrated Circuit) such as an electrically erasable programmable read only memory (EEPROM) is an elongated element arranged in parallel at a constant interval (pitch). It is formed on the formation region.

  Such element formation regions tend to be smaller in width and arranged at a narrower pitch with the miniaturization and higher integration of memory cells.

In order to cope with the miniaturization of memory cells, a NOR type flash memory in which a drain contact is formed using a so-called SAC (Self-Aligned Contact) technique, for example, IEDM (International Electron Devices Meeting), 1998, pp979. -982, “A Novel 4.6F2NOR Cell Technology With Lightly Doped Source (LDS) Junction For High Density Flash Memories” (Non-patent Document 1).
IEDM (International Electron Devices Meeting), 1998, pp 979-982, “A Novel 4.6F2NOR Cell Technology With Lightly Doped Source (LDS) Junction For High Density Flash Memories”

  As a result of studying semiconductor memory devices, particularly nonvolatile memories as described above, the present inventors have found the following unknown problems.

  That is, as the device becomes finer, the number of memory cell defects increases. As a result of examining this cause, it is thought that the crystal defect which arises in the edge part of an element formation area may be the cause.

  That is, there is a peripheral circuit formation region in which a logic circuit or the like (hereinafter referred to as a peripheral circuit) necessary for driving the memory cell is formed at the outer periphery of the memory cell formation region in the semiconductor integrated circuit device. Accordingly, in the periphery of the elongated element formation region in which the memory cells are formed, arranged at a narrow pitch, another element formation region in which a peripheral circuit is formed is disposed, and the width between these element formation regions is Separated by a wide insulating film.

  Therefore, as will be described in detail in the embodiments described later, stress is concentrated at the end of the elongated element formation region where the memory cell is formed, and crystal defects are likely to occur.

  When such a defect occurs, a leakage current increases between the drain region of the memory cell and the semiconductor substrate, or between the source region and the drain region. Furthermore, if this leakage current is greater than or equal to the operating current of the sense amplifier, it becomes defective.

  As described above, since a plurality of memory cells are formed on the elongated element formation region, even if a defect occurs in one memory cell, it is connected to the same data line as that memory cell. All the memory cells that are present become defective.

  An object of the present invention is to reduce defects in a semiconductor substrate in an element formation region.

  Another object of the present invention is to reduce leakage current by reducing defects in the semiconductor substrate in the element formation region.

  Another object of the present invention is to improve product yield and reliability by reducing leakage current.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  (1) A semiconductor integrated circuit device according to the present invention is an element formation region in which a memory cell is formed, and is partitioned by an insulating film, and the element formation region extending in the first direction is perpendicular to the first direction. One or more end portions of the element formation regions arranged in the second direction are extended to below the conductive film formed so as to surround the memory cell.

  (2) In the semiconductor integrated circuit device of the present invention, two or more element forming portions that are partitioned by an insulating film and extend in the first direction are arranged in a second direction perpendicular to the first direction. The end of each part is connected by a connecting part extending in the second direction.

  (3) The semiconductor integrated circuit device of the present invention is an element formation region in which a memory cell is formed, and is partitioned by an insulating film, and the element formation region extending in the first direction is perpendicular to the first direction. Of the element formation regions arranged in the second direction, the width of the outermost element formation region in the second direction is made wider than the width of other element formation regions.

  (4) A semiconductor integrated circuit device according to the present invention is an element formation region in which a memory cell is formed, and is partitioned by an insulating film, and the element formation region extending in the first direction is perpendicular to the first direction. Of the element formation regions arranged in the second direction, a memory cell functioning as a memory cell is not formed on the outermost element formation region.

  The effects obtained by the representative ones of the inventions disclosed by the present application will be briefly described as follows.

  An element forming region in which a memory cell is formed, wherein two or more element forming regions defined by an insulating film and extending in a first direction are arranged in a second direction perpendicular to the first direction. Since the end of the formation region is extended under the conductive film formed so as to surround the memory cell, stress can be concentrated in this extended region, and the defect does not extend to the region where the Mori cell is formed. The leakage current of the memory cell can be reduced.

  Further, two or more element forming portions that are partitioned by an insulating film and extend in the first direction are arranged in a second direction perpendicular to the first direction, and an end portion of the element forming portion extends in the second direction. Since the connection is performed at the existing connection portion, the direction in which the stress is applied can be changed, and the leakage current of the memory cell can be reduced.

  An element formation region in which a memory cell is formed, and a plurality of element formation regions which are partitioned by an insulating film and extend in the first direction are arranged in a second direction perpendicular to the first direction. Of the element formation regions, the width of the outermost element formation region in the second direction is wider than the width of other element formation regions, so that the influence of stress can be reduced and the leakage current of the memory cell is reduced. can do.

  An element formation region in which a memory cell is formed, and a plurality of element formation regions which are partitioned by an insulating film and extend in the first direction are arranged in a second direction perpendicular to the first direction. Since no memory cell that functions as a memory cell is formed on the outermost element formation region in the element formation region, stress can be concentrated on the outermost element formation region, and the leakage current of the memory cell Can be reduced.

  As a result, it is possible to improve product yield and reliability.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted.

(Embodiment 1)
FIG. 1 shows a plan view of the main part of the semiconductor integrated circuit device of the present embodiment. The right part of FIG. 1 shows the memory cell formation region MCFR, and the left part shows the peripheral circuit formation region PCFR. In the memory cell formation region MCFR, NOR-type nonvolatile memory cells are arranged in an array MCAR, and in the peripheral circuit formation region, a selection MISFET S is formed as an example of a peripheral circuit. 2 is a schematic view of the AA cross section of FIG. 1, and FIG. 3 is a schematic view of the BB cross section of FIG.

  As shown in FIG. 1, in the memory cell formation region, element formation regions (active) Ac extending in the X direction are arranged at regular intervals in the Y direction. The element formation region Ac is partitioned (defined) by an insulating film 6 made of, for example, a silicon oxide film 6 or the like. That is, the element formation regions Ac are separated by the insulating film 6 which is an element isolation insulating film. As shown in FIGS. 2 and 3, the insulating film 6 is formed with, for example, an STI structure embedded in a trench in a semiconductor substrate. The element formation region Ac is a region where the p-type well 8 is exposed on the surface of the semiconductor substrate 1.

  The width W of the element formation region Ac in the Y direction is, for example, about 0.3 μm, and the interval SW between the element formation regions Ac is, for example, about 0.4 μm. The length (width in the X direction) of the element formation region Ac corresponds to, for example, a 128-bit memory cell MC formed in the X direction, and is about 80 μm. That is, a plurality of memory cells MC are formed in the X direction in the element formation region Ac.

  Control electrodes (second electrodes) CG extending in the Y direction are arranged at regular intervals above the element formation region Ac. The width L in the X direction of the control electrode CG is, for example, about 0.3 μm, and the distance LS between the control electrodes CG is, for example, about 0.35 μm. The control electrode CG is formed integrally with the control electrode CG of the memory cell MC arranged in the Y direction, and becomes a word line WL extending in the Y direction.

  Between the control electrode CG and the element formation region Ac, as shown in FIGS. 2 and 3, for example, a laminated film (hereinafter referred to as an ONO film) in which a silicon oxide film, a silicon nitride film, and a silicon oxide film are sequentially laminated. An insulating film made of 21 or the like, and a gate insulating film 9 made of a floating electrode (first electrode) FG and a thermal oxide film are formed. The floating electrode FG is formed independently for each memory cell (see FIG. 3).

In the element formation regions Ac at both ends of the control electrode CG, n ⁺ type semiconductor regions 17 (source and drain regions) are formed, and plugs (drain contacts) DC (P1) are formed on the drain regions 17. On the source region 17, a plug (source contact) SC (P1) is formed. The plug DC (P1) is formed independently for each memory cell, but the plug SC (P1) is electrically connected to each of the source regions 17 of the memory cells MC connected to the same word line WL. A source line SL is connected and extended in the Y direction. That is, the plug (source contact) SC (P1) is a wiring extending in the Y direction and constitutes the source line SL. As will be described later, the plug DC (P1) and the plug SC (P1) are formed in the same manufacturing process.

  Further, the drain region 17 has a two-layer structure of plug DC (P1) and plug DC (P2), and a sub bit line SBL is formed on the plug DC (P2). The sub bit line SBL extends in the X direction.

  Further, as shown in FIG. 1, the plug SC (P1) is connected to a common source line CSL via the plug SC (P2). This common source line CSL also extends in the X direction, and is formed of the same wiring layer as the sub-bit line SBL. As will be described later, the plug DC (P2) and the plug SC (P2) are formed in the same manufacturing process.

Thus, the memory cell MC mainly includes a pair of n ⁺ type semiconductor regions 17 which are source and drain regions, a channel formation region (p-type well) 8 (Ac) formed therebetween, a channel A gate insulating film 9 formed on the formation region, a floating electrode (floating gate) FG formed on the gate insulating film 9, an insulating film 21 formed on the floating electrode FG, and formed on the insulating film 21 Control electrode (control gate) CG. The source and drain regions 17 of the memory cells MC adjacent in the Y direction are separated by the insulating film 6, and the control electrode CG of the memory cell MC arranged in the Y direction is formed integrally with the word line WL. The drain regions 17 of the memory cells MC arranged in the Y direction are electrically connected to different subbit lines SBL via plugs DC (P1) and DC (P2), and are arranged in the Y direction. Each of the MC source regions 17 is electrically connected by a source line SL. Further, the drain regions of the memory cells MC adjacent in the X direction are configured in common and are electrically connected to the sub-bit line SBL. The source regions 17 of the memory cells MC adjacent in the X direction are configured in common and are electrically connected to the source line SL.

  Here, writing, reading and erasing operations of the memory cell will be described.

  First, the write operation will be described. In order to write data to the memory cell, for example, a voltage of 9V is applied to the control electrode CG (word line WL) of the memory cell, a voltage of 4V is applied to the drain region (subbit line SBL) of the memory cell, and the element For example, a voltage of 3V is applied to the formation region Ac (p-type well 8), and the source region (source line SL) of the memory cell is maintained at, for example, 0V (ground potential). As a result, hot electrons are generated in the channel region (between the source and drain regions) of the memory cell and injected into the floating electrode FG.

  Next, the reading operation will be described. In order to read data in the memory cell, a voltage of, for example, 2.7 V is applied to the control electrode CG (word line WL) of the memory cell, and a voltage of, for example, 0.8 V is applied to the drain region (subbit line SBL) of the memory cell. The voltage is applied to maintain the element formation region Ac (p-type well 8) and the source region (source line SL) of the memory cell at, for example, 0V. At this time, data (“1” or “0”) of the memory cell is read out depending on whether or not a current flows between the source and drain regions of the memory cell. When the current flows, it can be seen that electrons are not injected into the floating electrode FG of the memory cell (below the threshold voltage), and for example, data of “0” is stored. When no current flows, it can be seen that electrons have been injected into the floating electrode FG of the memory cell (above the threshold voltage), and for example, data of “1” was stored.

  Next, the erase operation will be described. In order to erase the data written in the memory cell, a voltage of, for example, 10.5 V is applied to the control electrode CG (word line WL) of the memory cell, and the element formation region Ac (p-type well 8) and the drain of the memory cell For example, a voltage of 10.5 V is applied to the region (sub-bit line SBL), and the source region (source line SL) of the memory cell is maintained in a floating state (open state, open state). As a result, electrons are emitted from the control electrode CG to the channel region (between the source and drain regions) of the memory cell by the FN (Fowler-Nordheim) tunnel phenomenon.

  A dummy conductive film DSG formed of the same layer as the control electrode CG is formed on the outer periphery of the memory cell array. This dummy conductive film DSG is formed in order to reduce the influence of foreign matter generated during the formation of the memory cell, and to reduce the level difference between the memory cell formation region and the peripheral circuit formation region.

  This dummy conductive film DSG is also formed on the element formation region (p-type well 8), and between this and the element formation region Ac, for example, an insulating film made of ONO film 21 or the like, a floating electrode (first electrode) ) A gate insulating film 9 made of FG and a thermal oxide film is formed (see FIGS. 2 and 3).

On the other hand, a peripheral circuit element forming region LAc is also formed in the peripheral circuit forming region, and a conductive film constituting the gate electrode G of the selection MISFET S is formed on the element forming region LAc. As shown in FIG. 2, the gate electrode G is formed of the same layer as the control electrode CG, and a gate insulating film 9b is formed thereunder. In the element formation regions LAc at both ends of the gate electrode G, n ⁺ type semiconductor regions 27 (source and drain regions) are formed.

  Here, as shown in FIG. 1, the element formation region Ac of the memory cell formation region extends from the end of the drain region of the outermost memory cell by a length D in the X direction. Of the length D, the distance d1 is a distance considering the displacement of a mask used for forming the element formation region Ac, and the distance d2 is a distance considering a region where a crystal defect occurs. In the present embodiment, d1 is about 0.2 μm and d2 is about 0.3 μm. The size of d2 was set because the length of the crystal defect generated in the element formation region Ac when the memory cell was formed according to the above-described rule was about 0.3 μm.

  As described above, in the present embodiment, since the end portion of the element formation region Ac is extended, it is possible to avoid the influence of the crystal defects generated in the element formation region Ac. As a result, the occurrence of leakage current can be reduced, and the rate of occurrence of memory cell defects can be reduced.

  That is, as shown in FIG. 4, the insulating film 6 exists between the element forming regions Ac, and stress due to the insulating film 6 on the outer peripheral portion is applied to the element forming region Ac. In particular, since the insulating film 6 is formed over a wide range in order to separate the peripheral circuit from the peripheral portion of the memory cell formation region, stress is applied to the end portion of the element formation region Ac. concentrate. When such a large stress is applied, defects (De1, De2) such as dislocations are generated in the crystal forming the element formation region Ac. A leak current is generated through this defect, and as described above, if this leak current exceeds the operating current of the sense amplifier, it becomes defective.

  However, in the present embodiment, since the end of the element formation region Ac is extended, the defect De1 extends to a region where the substantial memory cell is formed (memory cell array MCAR) as shown in FIG. Therefore, the leakage current of the memory cell can be reduced.

  A dummy conductive film DSG is formed on the extended portion of the element formation region Ac, and further, an insulating film made of the ONO film 21 and the like, a floating electrode (first electrode) FG, and a thermal oxide film are formed below the dummy conductive film DSG. A gate insulating film 9 made of or the like is formed. Therefore, the structure is a pseudo memory cell structure (however, the source region does not exist), but the dummy conductive film DSG is in a floating state without being applied with a potential. A channel is not formed and no leakage current occurs.

  In the present embodiment, since the element formation region Ac is extended using the area under the dummy conductive film DSG, it is possible to take measures against defects without increasing the memory cell formation region.

  Next, an example of a method for manufacturing the semiconductor integrated circuit device of this embodiment will be described. 6 to 12 are cross-sectional views of the main part of the substrate showing the method of manufacturing the semiconductor integrated circuit device of the present embodiment. FIGS. 6 to 8 correspond to the CC cross-section of FIG. FIG. 12 corresponds to the DD cross section of FIG.

  First, as shown in FIG. 6, for example, a semiconductor substrate 1 made of p-type single crystal silicon having a specific resistance of about 1 to 10 Ωcm is subjected to, for example, thermal oxidation to form a pad oxide film (FIG. (Not shown). Next, an insulating film such as a silicon nitride film (not shown), for example, is deposited on the pad oxide film, and on the element isolation region using a not-shown photoresist film (hereinafter simply referred to as “resist film”) as a mask. The silicon nitride film is removed.

  Next, the resist film is removed, and the semiconductor substrate 1 is etched using the silicon nitride film as a mask to form an element isolation groove 4 having a depth of about 250 nm.

  Thereafter, the semiconductor substrate 1 is dry oxidized at about 1150 ° C., thereby forming a thermal oxide film such as a silicon oxide film 5 having a thickness of about 30 nm on the inner wall of the trench. The silicon oxide film 5 recovers damage caused by dry etching that has occurred on the inner wall of the groove, and relieves stress generated at the interface between the silicon oxide film 6 embedded in the groove and the semiconductor substrate 1 in the next step. To form.

  Next, an insulating film made of, for example, a silicon oxide film 6 having a thickness of about 600 nm is deposited on the semiconductor substrate 1 including the inside of the element isolation trench 4 by CVD, and then heat treatment (annealing) at 1150 ° C. for 60 minutes. ) To make the silicon oxide film 6 dense. Next, the silicon oxide film 6 on the upper part of the groove is polished by CMP to planarize the surface, and then the silicon nitride film is removed. At this time, although the surface of the silicon oxide film 6 protrudes from the surface of the semiconductor substrate 1 by the thickness of the silicon nitride film, it is oxidized by the subsequent cleaning process of the semiconductor substrate 1 and the surface oxidation and oxide film removal processes. The surface of the silicon film 6 gradually recedes.

  Through the above steps, element isolation in which the silicon oxide film 6 is embedded in the element isolation trench 4 is formed.

  Next, as shown in FIG. 7, after the surface of the semiconductor substrate 1 is wet-cleaned, the semiconductor substrate 1 is thermally oxidized to form a through oxide film (not shown) on the surface of the semiconductor substrate 1, for example. An insulating film is formed. Next, after p-type impurities (for example, boron) are ion-implanted into the semiconductor substrate 1, heat treatment is performed to diffuse the impurities, thereby forming the p-type well 8 in the memory cell formation region. A region where the p-type well 8 is exposed on the surface of the semiconductor substrate 1 is an element formation region Ac. Here, the element formation region LAc is similarly formed in the peripheral circuit formation region.

  Next, after a thermal oxide film having a film thickness of, for example, about 8 nm is formed on the surface of the p-type well 8 by thermal oxidation (pre-oxidation), the thermal oxide film is removed and the semiconductor substrate 1 (p-type well 8) is removed. Clean the surface. Next, heat treatment is performed to form, for example, a thermal oxide film having a thickness of about 10.5 nm. This thermal oxide film constitutes the gate insulating film 9 of the nonvolatile memory cell.

  Next, a conductive film such as a polycrystalline silicon film 10 doped with phosphorus having a thickness of about 100 nm is deposited on the gate insulating film 9 by the CVD method. Next, the polycrystalline silicon film 10 is dry-etched using a resist film (not shown) as a mask, whereby a stripe-shaped pattern FG ′ (10) extending in the X direction in the memory cell formation region. Form.

  Next, as illustrated in FIG. 8, an insulating film such as an ONO film 21 is formed on the semiconductor substrate 1 in order to separate the pattern FG ′ (10) from a control electrode CG described later. The ONO film 21 is a laminated film of a silicon oxide film, a silicon nitride film, and a silicon oxide film. For example, a silicon oxide film having a thickness of about 5 nm, a silicon nitride film having a thickness of about 7 nm, and a thickness of about 4 nm are formed by CVD. The silicon oxide films are sequentially deposited. Note that a silicon nitride film of about 10 nm may be further deposited on the uppermost silicon oxide film.

  Here, in the peripheral circuit formation region, the ONO film 21, the polycrystalline silicon film 10, and the gate insulating film 9 on the peripheral circuit formation region are removed. Next, after wet cleaning the surface of the semiconductor substrate 1 in the peripheral circuit formation region, a gate insulating film 9b having a thickness of about 8 nm is formed on the surface of the p-type well 8 in the peripheral circuit formation region by, for example, thermal oxidation. The gate insulating film 9b becomes the gate insulating film 9b of the selection MISFET S formed in the peripheral circuit formation region (see FIG. 2).

Next, as a conductive film, for example, a polycrystalline silicon film 22 doped with about 4.75 × 10 ²⁰ / cm ^{3 of} phosphorus is deposited on the semiconductor substrate 1 by CVD to a thickness of about 200 nm. Subsequently, an insulating film such as a silicon nitride film 24 having a thickness of about 300 nm is deposited thereon by a CVD method. This polycrystalline silicon film 22 becomes the gate electrode G of the selection MISFET S formed in the peripheral circuit formation region, and also becomes the control electrode CG of the nonvolatile memory cell formed in the memory cell formation region.

  Next, as shown in FIG. 9, using the resist film (not shown) in the memory cell formation region as a mask, the silicon nitride film 24, the polycrystalline silicon film 22, the ONO film 21, and the pattern FG ′ (polycrystalline silicon film 10). ) Is dry-etched.

  By this dry etching, a control electrode CG (22) made of polycrystalline silicon 22 and a floating electrode FG (10) made of polycrystalline silicon film 10 are formed. The floating electrode FG (10) is divided for each memory cell arranged in the X direction, and the control electrode CG is formed to extend in the Y direction, and constitutes the word line WL. Note that the control electrode CG is not limited to the polycrystalline silicon film 22, but is composed of a single-layer film or a laminated film of a refractory metal, a silicide film, or a laminated film of a polycrystalline silicon film and a refractory metal film or a silicide film. May be. 9 corresponds to the EE cross section of FIG. 8 and also corresponds to the DD cross section of FIG.

  Here, in the peripheral circuit formation region, the gate electrode G for the selection MISFET S is formed by dry etching the silicon nitride film 24 and the polycrystalline silicon film 22 using a resist film (not shown) as a mask. (See FIG. 2).

Next, after ion-implanting an n-type impurity (for example, arsenic) into the p-type well 8 in the memory cell formation region, a heat treatment is performed to diffuse the impurity, whereby the n ⁺ -type semiconductor region 17 (source and drain regions). ). At this time, a channel implantation region (not shown) may be formed under the gate insulating film 9 by obliquely implanting p-type impurities (for example, boron).

Here, in the peripheral circuit formation region, an n-type impurity (for example, arsenic) is ion-implanted into the p-type well 8 and then subjected to heat treatment to diffuse the impurity, thereby forming an n ⁻ type on both sides of the gate electrode G. A semiconductor region (not shown) is formed.

  Next, for example, a light oxide film (thermal oxide film) 26 is formed on the sidewalls of the polycrystalline silicon films 10 and 22 by performing heat treatment (light oxidation) at 850 ° C. The light oxide film 26 is formed under the same conditions as those for forming a silicon oxide film having a thickness of about 10 nm on the surface of the silicon substrate. In addition, this film is used to recover damage caused at the end of the gate insulating film 9 when the floating electrode FG (polycrystalline silicon film 10) and the control electrode (polycrystalline silicon film 22) are etched. Form.

  Next, an insulating film such as a silicon nitride film 28 is deposited on the semiconductor substrate 1 by, eg, CVD.

Here, in the peripheral circuit formation region, sidewall spacers (not shown) are formed on the sidewalls of the gate electrode G in the peripheral circuit formation region by anisotropically etching the silicon nitride film 28. Next, after ion-implanting an n-type impurity (phosphorus P or arsenic As) into the p-type well 8 in the peripheral circuit formation region, a heat treatment is performed at 950 ° C. for 10 seconds to diffuse the impurity, thereby selecting MISFET. An n ⁺ type semiconductor region 27 (source and drain regions) for S is formed.

  Through the above process, the NOR type nonvolatile memory cell having the control electrode CG (polycrystalline silicon film 22), the ONO film 21, the floating electrode FG (polycrystalline silicon film 10), and the gate insulating film 9 in the memory cell formation region is obtained. Thus, the selection MISFET S is formed in the peripheral circuit formation region.

Next, as shown in FIG. 10, after an insulating film such as a silicon oxide film 30 of about 200 nm is formed on the silicon nitride film 28 by, for example, a CVD method, the plug DC shown in FIG. In order to form a pattern of (P1) and plug SC (P1), the silicon oxide film 30 is dry-etched by dry etching using a resist film (not shown) as a mask, and then the silicon nitride film 28 is dry-etched. Thus, a contact hole C1 and a wiring trench HM1 are formed above the n ⁺ type semiconductor region 17 (source and drain regions). That is, the contact hole C1 is formed on the drain region (17), and the wiring trench HM1 is formed on the source region (17).

  The etching of the silicon oxide film 30 is performed under such a condition that the etching rate of silicon oxide with respect to silicon nitride is increased so that the silicon nitride film 28 is not completely removed.

  Further, the etching of the silicon nitride film 28 is performed under the condition that the etching rate of silicon nitride with respect to silicon or silicon oxide is increased so that the substrate 1 and the silicon oxide film are not etched deeply. Further, this etching is performed under the condition that the silicon nitride film 28 is anisotropically etched so that the silicon nitride film 28 is left on the side walls of the control electrode CG and the floating electrode FG. Thereby, the contact hole C1 having a diameter smaller than the minimum dimension determined by the resolution limit of photolithography and the wiring groove HM1 having a fine width are formed in a self-alignment (self-alignment) with respect to the control electrode CG and the floating electrode FG. Is done.

Next, after ion-implanting an n-type impurity (for example, arsenic) through the contact hole C1 and the wiring trench HM1, an n ⁺ -type semiconductor region 19 is formed by performing heat treatment and diffusing the impurity. The n ⁺ type semiconductor region 19 is formed in order to reduce the contact resistance with the plug formed in the contact hole C1.

  Next, as shown in FIG. 11, an insulating film such as a thin silicon nitride film 32 is formed on the silicon oxide film 30 including the inside of the contact hole C1 and the wiring trench HM1. Next, the silicon nitride film 32 on the silicon oxide film 30 and at the bottom of the contact hole C1 and the wiring groove HM1 is removed by etching back. This silicon nitride film 32 is formed in order to prevent the silicon oxide film 30 above the control electrode CG from being etched and shorting between the plugs and the like when the semiconductor substrate 1 described later is cleaned.

  Next, after the semiconductor substrate 1 is cleaned using, for example, a hydrofluoric acid-based cleaning liquid, a conductive film is deposited on the silicon oxide film 30 including the inside of the contact hole C1 and the wiring trench HM1. For example, Ti (titanium) of about 10 nm and TiN (titanium nitride) of about 80 nm are sequentially deposited by sputtering (not shown), and a W (tungsten) film of about 350 nm is deposited by CVD.

  Next, the plug P1 is formed by removing the conductive film made of the W film, the TiN film, and the Ti film outside the contact hole C1 and the wiring groove HM1 by the CMP method. That is, the plug DC (P1) is formed in the contact hole C1 on the drain region (17), and the plug SC (P1) is formed in the wiring groove HM1 on the source region (17). As described above, the plug SC (P1) is a wiring extending in the Y direction and constitutes the source line SL.

  Next, an insulating film such as a silicon oxide film 35 of about 300 nm is deposited on the silicon oxide film 30 including the plug P1 by, for example, the CVD method.

  Next, the contact hole C2 is formed by removing the silicon oxide film 35 on the plug P1. In FIG. 12, only the contact hole C2 on the plug DC (P1) on the drain region appears, and the contact hole C2 on the plug SC (P1) on the source region has a cross section different from that in FIG. Appear in

  Next, a conductive film is deposited on the silicon oxide film 35 including the inside of the contact hole C2. For example, a W film (not shown) of about 100 nm is deposited by a sputtering method, and further a W film 40 of about 250 nm is deposited by a CVD method.

  Next, the first layer wiring M1 and the connection portion (plug P2) between the first layer wiring M1 and the plug P1 are formed by dry etching the conductive film made of the W film 40 or the like using a resist film (not shown) as a mask. . That is, the plug DC (P2) and the plug SC (P2) are formed. The first layer wiring M1 in the figure becomes the sub-bit line SBL in FIG. 1, and the first layer wiring M1 on the plug SC (P2) that does not appear in the cross section shown in FIG. 12 becomes the common source line CSL.

  Thereafter, an insulating film such as a silicon oxide film is deposited on the silicon oxide film 35 including the first layer wiring M1 by, for example, a CVD method, and a conductive film made of a W film or the like is further formed thereon. The second layer wiring is formed by depositing, but illustration of these is omitted.

  In the method of manufacturing a semiconductor integrated circuit device described in detail above, for example, 1) heat treatment for densification of the silicon oxide film 6, 2) heat treatment for forming a through oxide film, 3) semiconductor substrate 1 ( Various heat treatments such as oxidation (pre-oxidation) for cleaning the surface of the p-type well 8), 4) heat treatment for forming the gate insulating film 9, and 5) heat treatment for forming the light oxide film 26. Process.

  In such a heat treatment process, the silicon oxide film 6 embedded in the groove formed in the semiconductor substrate, particularly a thin thermal oxide film (oxidized film) formed to recover from dry etching damage generated on the inner wall of the groove. As the oxidation of the silicon film 5) proceeds, the stress applied to the element formation region increases.

Also, stress is applied to the element formation region by ion implantation when forming the n ⁺ type semiconductor region 17 (source and drain regions) and the n ⁺ type semiconductor region 19.

  Further, since the silicon nitride film is a film having a large film stress, for example, even when the silicon nitride film 28 used for forming the contact hole C1 and the wiring groove HM1 in a self-aligned manner is deposited, the stress is applied to the element formation region. Will be added.

  However, according to the present embodiment, as described above, since the end portion of the element formation region Ac is extended, even if the stress is applied, the defect does not extend to the region where the memory cell is formed, and the memory cell The effect of reducing the leakage current can be obtained.

(Embodiment 2)
FIG. 13 is a plan view of the main part of the semiconductor integrated circuit device according to the present embodiment. The right part of FIG. 13 shows the memory cell formation region MCFR, and the left part shows the peripheral circuit formation region PCFR. NOR type nonvolatile memory cells are arranged in an array in the memory cell formation region, and a selection MISFET S is formed in the peripheral circuit formation region as an example of a peripheral circuit. As apparent from the comparison with FIG. 1, the semiconductor integrated circuit device of the present embodiment has the same configuration as that of the first embodiment except that the end portion of the element forming portion Ac1 is connected by the connection portion Ac2. Therefore, detailed description is omitted, and only characteristic portions will be described.

  That is, as shown in FIG. 13, in the memory cell formation region, element formation portions Ac1 extending in the X direction are arranged at regular intervals in the Y direction, and the end portions of the element formation portions Ac1 are Are connected by a connecting portion Ac2 extending in the Y direction.

  Thus, in this Embodiment, since the edge part of element formation part Ac1 was connected by connection part Ac2, as shown in FIG. 14, the direction where stress is added can be changed. Therefore, in addition to the effect of the first embodiment, it is possible to further reduce the concentration of stress on the element formation portion Ac1. As a result, the defect De1 does not extend to a region where the substantial memory cell is formed (memory cell array MCFR), and the leakage current of the memory cell can be reduced.

  In FIG. 13, all of the element forming portions Ac1 are connected by the connecting portion Ac2. However, as shown in FIG. 15, every two element forming portions Ac1 (in the case of FIG. 15, two element forming portions). A connecting portion Ac2 may be provided for each Ac1).

(Embodiment 3)
FIG. 16 is a plan view of the main part of the semiconductor integrated circuit device according to the present embodiment. The right part of FIG. 16 shows the memory cell formation region MCFR, and the left part shows the peripheral circuit formation region PCFR. NOR type nonvolatile memory cells are arranged in an array in the memory cell formation region, and a selection MISFET S is formed in the peripheral circuit formation region as an example of a peripheral circuit. As apparent from the comparison with FIG. 1, the semiconductor integrated circuit device of the present embodiment includes the outermost element formation region AcW among the plurality of element formation regions Ac and AcW arranged in the memory cell formation region. Since the configuration is the same as that of the first embodiment except that the width is wider than the width of the other element formation regions Ac, detailed description is omitted, and only characteristic portions will be described.

  That is, as shown in FIG. 16, in the memory cell formation region, element formation regions Ac, AcW extending in the X direction are arranged at regular intervals in the Y direction. The element formation regions Ac, AcW Among them, the width in the Y direction of the element formation region AcW located at the extreme end in the Y direction is wider than that of the other element formation regions Ac.

  Thus, in the present embodiment, since the outermost element formation region AcW is formed wider than the other element formation regions Ac, the influence of stress can be reduced as shown in FIG. The occurrence rate of defects (De2) in the outermost element formation region AcW can be reduced. As a result, the leakage current of the memory cell can be reduced.

  Further, as described in the first embodiment, if the end portions of the element formation regions Ac and AcW are extended, it is possible to prevent the defect (De1) from extending to the region where the memory cell is formed. The effect demonstrated in the form 1 can be acquired.

(Embodiment 4)
FIG. 18 is a plan view of the main part of the semiconductor integrated circuit device according to the present embodiment. The right part of FIG. 18 shows the memory cell formation region MCFR, and the left part shows the peripheral circuit formation region PCFR. NOR type nonvolatile memory cells are arranged in an array in the memory cell formation region, and a selection MISFET S is formed in the peripheral circuit formation region as an example of a peripheral circuit. 19 is a schematic view of the AA cross section of FIG. 18, and FIG. 20 is a schematic view of the BB cross section of FIG.

  In the semiconductor integrated circuit device according to the present embodiment, as apparent from the comparison with FIG. 13, the element formation region DAc is provided in the memory cell formation region at the outermost of the plurality of element formation portions Ac1 arranged. Since the configuration is the same as that of the second embodiment, detailed description is omitted and only characteristic portions will be described.

  That is, as shown in FIG. 18, in the memory cell formation region, element formation portions Ac1 extending in the X direction are arranged at regular intervals in the Y direction. An element formation region DAc is arranged on the outer side of the element formation part Ac1 located in the position.

  No memory cell that functions as a memory cell is formed on the element formation region DAc. That is, the control electrode CG extends in the Y direction on the element formation region DAc, but the plug DC and the plug SC are not formed at both ends of the control electrode CG.

  In addition, lead portions (connection portions between the control electrodes CG and upper layer wirings) CA of the control electrodes CG are alternately formed at the ends of the control electrodes CG in the Y direction. The control electrode CG in which such a region (CA) is not formed in FIG. 18 has the lead-out portion at the other end that does not appear in FIG.

  Thus, in the present embodiment, since the element formation region DAc is provided at the outermost part of the plurality of element formation portions Ac1, stress can be concentrated in this region, that is, the region where the Mori cell is formed, that is, The defect (De2) does not extend to the element formation portion Ac1 shown in FIG. 21, and the leakage current of the memory cell can be reduced.

  Further, since the element formation region DAc is formed using the area under the lead portion CA, it is possible to take a countermeasure against defects without increasing the memory cell formation region.

  Further, as described in the second embodiment, if the end portions of these element forming portions (Ac1, DAc) are connected by the connection portion Ac2, the effect described in the second embodiment (reduction of the influence of the defect De1) is achieved. ) Can be obtained.

  FIG. 22 shows a circuit diagram corresponding to the semiconductor integrated circuit device of the present embodiment. As shown in the figure, memory cells MC are arranged in an array. However, the memory cell on DAc (element formation region) does not operate as a memory cell. Further, the pseudo memory cell described in the first embodiment is formed on the DSG (dummy conductive film). MBL represents a main bit line. S represents the above-described selection MISFET. These memory cells use a block as one unit. For example, data can be erased at once for each block. One well (WELL) can be made one block. The circuit diagram corresponding to the semiconductor integrated circuit device described in the first to third embodiments is the same except that there is no memory cell on DAc (element formation region) in FIG.

  Although the first to fourth embodiments have been specifically described above, the present invention is not limited to such embodiments. For example, the end portions of the element formation regions Ac and AcW of the third embodiment are implemented. You may connect by connection part Ac2 like the form 2. Further, the end portions of the element formation regions Ac1 and DAc of the fourth embodiment may not be connected by the connection portion Ac2, and the end portions of these element formation regions may be simply extended as in the first embodiment. Thus, the configurations described in these embodiments may be combined as appropriate.

(Embodiment 5)
The semiconductor integrated circuit device described in Embodiments 1 to 4 can be used in a computer system described below.

  FIG. 23 shows a computer system in which the semiconductor integrated circuit device (nonvolatile memory) described in the first to fourth embodiments is incorporated, and this system is connected to host CPUs (Central Processing) connected to each other via a system bus SB. Unit) 231, input / output device 232, RAM (Random Access Memory) 233, and memory card 234.

  The memory card 234 includes, for example, a non-volatile memory (EEPROM chip 1 to chip 4) having a mass storage capacity of several tens of gigabytes as a replacement for a hard disk storage device. In addition, the present invention has advantages such as reduction of defects in the device, reduction of leakage current, or improvement of device yield and reliability, and thus has sufficient industrial advantages as a storage device as a final product.

  The present invention is not limited to the relatively thin memory card 234. Even when the thickness is relatively large, the interface with the host bus system and the command of the host system are analyzed to be non-volatile. Needless to say, the present invention can be applied to any nonvolatile memory device including an intelligent controller capable of controlling a nonvolatile memory.

  Data stored for a long period of time is stored in this nonvolatile storage device, while data that is processed and frequently changed by the host CPU 231 is stored in the RAM 233 of the volatile memory.

  The card 234 has a system bus interface SBI connected to the system bus SB, and enables a standard bus interface such as an ATA system bus. The controller CR connected to the system bus interface SBI receives commands and data from the host system of the host CPU 231 and the input / output device 232 connected to the system bus SB.

  When the command is a read command, the controller CR accesses one or more necessary ones of the plurality of chips 1 to 4 (CH1 to 4) having the nonvolatile memory described in the first to fourth embodiments to host read data. Transfer to system.

  When the command is a write command, the controller CR accesses one or more necessary ones of the plurality of chips 1 to 4 (CH1 to CH4) and stores write data from the host system therein. This storing operation includes a program operation and a verify operation for a necessary block, sector or memory cell of the nonvolatile memory.

  When the command is an erase command, the controller accesses one or more necessary ones of the plurality of chips 1 to 4 (CH1 to CH4) and erases data stored therein. This erase operation includes an erase operation and a verify operation for a necessary block, sector or memory cell of the nonvolatile memory.

  The non-volatile memory according to the embodiment of the present invention is not only a technique for storing one bit of digital data in one memory cell, but also a technique in which a binary threshold voltage is given to one memory cell. Needless to say, the present invention is also applicable to a technique in which a memory cell has a multilevel threshold voltage of four or more in order to store bits.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  In particular, in this embodiment, a NOR type nonvolatile memory has been described as an example. However, the present invention can be widely applied to AND type, NAND type, and other semiconductor integrated circuit devices having an elongated element formation region. is there.

  The present invention can be widely used in the manufacturing industry for manufacturing semiconductor integrated circuit devices.

1 is a plan view of an essential part of a substrate showing a semiconductor integrated circuit device according to a first embodiment of the present invention; 1 is a cross-sectional view of main parts of a substrate showing a semiconductor integrated circuit device according to a first embodiment of the present invention. 1 is a cross-sectional view of main parts of a substrate showing a semiconductor integrated circuit device according to a first embodiment of the present invention. FIG. 3 is a plan view of the essential part of the substrate showing the semiconductor integrated circuit device for explaining the effect of the first embodiment of the present invention; 1 is a plan view of an essential part of a substrate showing a semiconductor integrated circuit device according to a first embodiment of the present invention; It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is a principal part top view of the board | substrate which shows the semiconductor integrated circuit device which is Embodiment 2 of this invention. It is a principal part top view of the board | substrate which shows the semiconductor integrated circuit device which is Embodiment 2 of this invention. It is a principal part top view of the board | substrate which shows the semiconductor integrated circuit device which is Embodiment 2 of this invention. It is a principal part top view of the board | substrate which shows the semiconductor integrated circuit device which is Embodiment 3 of this invention. It is a principal part top view of the board | substrate which shows the semiconductor integrated circuit device which is Embodiment 3 of this invention. It is a principal part top view of the board | substrate which shows the semiconductor integrated circuit device which is Embodiment 4 of this invention. It is principal part sectional drawing of the board | substrate which shows the semiconductor integrated circuit device which is Embodiment 4 of this invention. It is principal part sectional drawing of the board | substrate which shows the semiconductor integrated circuit device which is Embodiment 4 of this invention. It is a principal part top view of the board | substrate which shows the semiconductor integrated circuit device which is Embodiment 4 of this invention. It is a circuit diagram corresponding to the semiconductor integrated circuit device which is Embodiment 4 of this invention. It is a figure which shows the computer system using the semiconductor integrated circuit device of this invention.

Explanation of symbols

1 Semiconductor substrate 4 Element isolation trench 5 Silicon oxide film (thermal oxide film)
6 Silicon oxide film (insulating film)
8 p-type well 9 gate insulating film 9b gate insulating film 10 polycrystalline silicon film 17 n ⁺ type semiconductor region 19 n ⁺ type semiconductor region 21 ONO film (insulating film)
22 Polycrystalline silicon film 24 Silicon nitride film 26 Light oxide film 27 n ⁺ type semiconductor region 28 Silicon nitride film 30 Silicon oxide film 32 Silicon nitride film 35 Silicon oxide film 40 W film Ac Element formation area Ac1 Element formation part Ac2 Connection part AcW Element formation region DAc Element formation region LAc Element formation region C1 Contact hole C2 Contact hole CA Lead part SC plug DC plug P1 plug P2 plug CG Control electrode FG Floating electrode FG 'Pattern G Gate electrode DSG Dummy conductive film De1, De2 Defect MBI Main bit line SBL Sub bit line SL Source line WL Word line M1 First layer wiring D, d1, d2 Distance MC Memory cell S MISFET for selection
232 I / O device 233 RAM
234 Memory card SB system bus SBI system bus interface CR controller CH1 to CH4 chip MCFR memory cell formation area PCFR peripheral circuit formation area MCAR memory cell array

Claims (7)

(A) An element formation region formed on the surface of the semiconductor substrate and partitioned by the first insulating film and extending in the first direction in a second direction perpendicular to the first direction 3 a above, an element forming region and a connecting portion for connecting the ends of the three or more element forming portion, extending in the second direction,
(B) a plurality of memory cells formed on the main surface of the element formation region;
(C) a memory cell array composed of the plurality of memory cells;
(D) a first conductive film formed on the outer periphery of the memory cell array so as to extend at least in the first and second directions;
A semiconductor integrated circuit device comprising:
The first insulating film is embedded in a groove formed in the semiconductor substrate;
The semiconductor integrated circuit device , wherein the connection portion is formed under the first conductive film extending in the second direction . (A) An element formation region formed on the surface of the semiconductor substrate and partitioned by the first insulating film and extending in the first direction in a second direction perpendicular to the first direction An element formation region having three or more, connecting end portions of the three or more element formation portions, and having a connection portion extending in the second direction;
(B) a plurality of memory cells formed on the main surface of the element formation region;
(C) a memory cell array composed of the plurality of memory cells;
(D) a first conductive film formed on the outer periphery of the memory cell array so as to extend at least in the first and second directions;
A semiconductor integrated circuit device comprising:
Of the three or more element formation regions, the width of the outermost element formation region in the second direction is wider than the width of other element formation regions,
The first insulating film is embedded in a groove formed in the semiconductor substrate;
The semiconductor integrated circuit device, wherein the connection portion is formed under the first conductive film extending in the second direction. (A) An element formation region formed on the surface of the semiconductor substrate and partitioned by the first insulating film and extending in the first direction in a second direction perpendicular to the first direction An element formation region having three or more, connecting end portions of the three or more element formation portions, and having a connection portion extending in the second direction;
(B) a plurality of nonvolatile memory cells formed on the main surface of the element formation region;
(C) a memory cell array composed of the plurality of nonvolatile memory cells;
(D) a first conductive film formed on the outer periphery of the memory cell array so as to extend at least in the first and second directions;
A semiconductor integrated circuit device comprising:
Each of the plurality of nonvolatile memory cells is
(B1) a second conductive film formed on the element formation region via a second insulating film;
(B2) a third conductive film formed on the second conductive film via a third insulating film and extending in the second direction;
Have
The first conductive film is formed to include the same layer as the third conductive film,
The first insulating film is embedded in a groove formed in the semiconductor substrate;
The semiconductor integrated circuit device, wherein the connection portion is formed under the first conductive film extending in the second direction. The semiconductor integrated circuit device according to claim 3.
The second conductive film in the nonvolatile memory cell constitutes a floating gate of the nonvolatile memory cell,
The semiconductor integrated circuit device, wherein the third conductive film in the nonvolatile memory cell constitutes a control gate of the nonvolatile memory cell. The semiconductor integrated circuit device according to claim 1,
2. A semiconductor integrated circuit device according to claim 1, wherein a memory cell functioning as a memory cell is not formed on the outermost element forming region among the three or more element forming regions. The semiconductor integrated circuit device according to claim 1 or 2,
The semiconductor integrated circuit device, wherein the first conductive film is a dummy conductive film that is not connected to the plurality of memory cells. The semiconductor integrated circuit device according to claim 3 or 4,
The semiconductor integrated circuit device, wherein the first conductive film is a dummy conductive film that is not connected to the plurality of nonvolatile memory cells.

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