JPH0997762A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a micro wiring to be formed by a method wherein a groove- like dummy pattern is formed surrounding the periphery of patterns regularly arranged in lines. SOLUTION: A silicon oxide film 20 is formed on a semiconductor substrate 201, and a polysilicon film 203 is formed thereon. Positive resist 204 is applied onto the polysilicon film 203 so as to form grooves isolated and regularly arranged on the polysilicon film 203. Thereafter, the resist 204 is irradiated with ultraviolet rays through the intermediary of a photomask. At this point, a pattern on the photomask is composed of a pattern 205 which is used for forming regularly arranged grooves (gap W1 between grooves) and a dummy region 206 which surrounds the outermost groove distant from it by a distance of W1 ' (W1 '<=W1 ). Then, a thermal treatment is carried out at a temperature of 100 deg.C or above. At this point, the resist 204 is deformed due to a shrinkage action, but the regularly arranged grooves are hardly affected by the shrinkage of the resist 204 because the resist 204 is isolated from a wide resist region by the dummy region 206.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a regularly arranged pattern.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor device having a regularly arranged pattern, in particular, a fine wiring pattern (eg, bit line) regularly arranged like a memory cell array in a semiconductor memory, the wiring in the array is on the outer periphery of the array. The same dummy wiring pattern as the pattern was provided in several rows and several columns (see USP 5,066,997). This is to improve the process controllability of the regularly arranged fine wiring pattern. In the photolithography process for forming such a dummy wiring pattern, as shown in FIG. 7 and FIG. 8, in the case of the projection type resist pattern 101 in which the resist pattern forming the array pattern is formed independently. Is valid.

On the other hand, regarding the resist pattern, there is a groove type resist pattern in which the resist patterns forming the array pattern are continuously extended to the outer periphery thereof. For example, a resist pattern having a groove-shaped pattern 103 formed regularly as shown in FIGS. 9 and 10 and a resist 102 surrounding the groove-shaped pattern 103 corresponds to this.

[0004]

In the case of the above-mentioned groove type resist pattern, after the pattern is formed, a heat treatment is carried out in order to harden the resist pattern. In order to perform heat treatment after resist development in this photolithography process,
The resist shrinks, and the resist that forms the regular array pattern (the resist between neighboring grooves) is pulled by the resist on the outer periphery that is wider than the resist dimension in the regular array pattern. (See FIG. 11), and as a result, it has become difficult to form fine wiring having a desired wiring length or wiring width, particularly fine wiring existing in a memory or the like.

[0005]

SUMMARY OF THE INVENTION A problem to be solved by the present invention is a semiconductor device having a regularly arranged pattern, and in order to improve dimensional controllability, the outer periphery of a regularly arranged groove-type resist pattern is used. It is characterized by forming a dummy pattern on the moat. By providing such a dummy pattern, the regular array pattern and the resist in a wide area around the regular array pattern are separated by the dummy pattern. As a result, it is possible to prevent the pattern from collapsing due to the contraction of the resist in the outer peripheral region.
At this time, it is more effective when the resist width between the dummy pattern and the outermost periphery of the regular array pattern is equal to or smaller than the resist width between adjacent patterns in the regular array pattern.

[0006]

DETAILED DESCRIPTION OF THE INVENTION An embodiment of the present invention will be described with reference to FIGS. In FIG. 1, a silicon oxide film (202) having a thickness of, for example, 20 nm is formed on a semiconductor substrate (201).
Next, it is a cross-sectional view when a polysilicon film (203) is formed to a thickness of 100 nm. Then, a general lithography process is performed to form regularly arranged isolated trenches in the polysilicon. That is, a positive resist (for example, a mixture of a cresol novolac resin and a naphthoquinonediazide compound of a photosensitive material) on a polysilicon (203) (204)
Is applied (FIG. 2). Then, the resist (204) is irradiated with ultraviolet rays (for example, 436 nm (so-called g-line) or 365 nm (so-called i-line)) through a photomask. At this time, the pattern on the photomask is a pattern (205) for forming regularly arranged grooves (groove spacing W1) and W1 ′ (≦ W
A dummy area (206) surrounding the array of grooves at a distance of 1)
(FIG. 3). After that, development is performed using a positive resist developer (for example, an organic alkali such as tetramethylammonium hydroxide or choline) (FIG. 4). Next, heat treatment is performed at a high temperature of 100 ° C. or higher in order to improve the adhesion between the base film and the resist and to solidify the resist and improve the RIE (Reactive Ion Etching) resistance. At this time, the resist is deformed due to the contraction of the resist, but since the dummy region is divided from the wider resist region, the regularly arranged grooves are not affected by the contraction of the resist.

According to our experiments, in the case where the above-mentioned dummy region is not provided, when a resist pattern in which grooves having a width of 0.4 μm and a length of 15 μm are regularly arranged is formed, the groove 1 is formed.
It was affected by resist shrinkage over zero. On the other hand, when the dummy region was formed, no groove was affected by the resist shrinkage.

As described above, according to the present invention, the outer periphery of the regularly arranged pattern is surrounded by the dummy regions in which the resist is continuously peeled off, so that the resist shrinkage due to the heat treatment after the resist development is affected. And the processing controllability of the array pattern is significantly improved. This is particularly effective in a semiconductor device having a regularly arranged fine pattern, such as a memory cell array in a semiconductor memory, when each of the regularly arranged patterns is a pattern formed by an isolated resist opening. There is.

FIG. 5 is a plan view showing a method of manufacturing the nonvolatile semiconductor memory device used in the present invention. Further, FIG. 6 shows a sectional view taken along line 9B and 9B ′ of FIG.
These FIG. 5 and FIG. 6 will be described in detail.

Reference numeral 12 is an element isolation region made of an oxide film formed by the LOCOS method, and a thin oxide film 11 is formed in a region surrounded by the element isolation region. In this state, a Poly-Si layer serving as a floating gate is formed on the upper surface of the substrate, and then a resist is overcoated on the upper surface. In this resist, a groove type resist pattern having a plurality of grooves is formed by the above-mentioned lithography process. The groove 14 of the resist is formed on the Poly-Si on the element isolation region 12 in order to etch the Poly-Si on the element isolation region 12. At this time, the pattern on the photomask is a pattern for forming regularly arranged grooves (groove spacing W1) and the outermost grooves W1 ′, W1 ″ (≦ W1) from the outermost groove on the outer periphery thereof.
The dummy pattern 14 'is formed at the same time because it has a dummy region surrounding the array of grooves separated by the distance.

It is most desirable that the relationship between W1, W1 'and W1 "is equal in the distance. This is because the exposure amount is determined in consideration of the distance between the grooves and the depth of the formed grooves. Therefore, when the grooves (the moat 14 ′) under the same conditions are formed at the same time, it is desirable to form the grooves and the moat under the same conditions as much as possible. This is because the resist is prevented from being deformed due to the shrinkage stress of W.sub.1, and the effect is reduced when W1 'and W2 "are larger than W1. Therefore, it can be understood that the above conditions are desired from the object of the present application and the exposure conditions. I think that the.

Next, a resist having a groove-shaped resist pattern and a dummy pattern is used to improve the adhesion between the base film and the resist.
To improve E (Reactive Ion Etching) resistance, 1
Heat treatment is performed at a high temperature of 00 ° C. or higher. At this time, the resist is deformed due to the contraction of the resist, but since the dummy region is divided from the wider resist region, the regularly arranged grooves are not affected by the contraction of the resist.

After that, a floating gate pattern is formed using a resist having a groove-shaped resist pattern and a dummy pattern. At this time, a non-functional Poly-Si pattern is formed on the outer periphery of the floating gate pattern. Then, a conductive layer for the control gate is formed on the entire surface of the substrate, and a resist is overlaid thereon. A pattern is formed in this resist to form a control gate by a lithography process, and RIE is performed using this resist to simultaneously form the control gate 15 and the floating gate 13. In a memory device requiring fine processing, the present invention has improved dimensional controllability and can improve yield.

Although the present invention has been described with reference to the above embodiments, various applications are possible without departing from the effects of the present invention. For example, although a positive resist was used in the above-mentioned examples, a negative resist may be used, and a representative example of the resist material at that time is a mixture of a cyclized polyisoprene rubber and a bisazide compound of a photosensitive material. When using a negative resist, the light-shielding area of the photomask is
This is an inversion in the case of a positive type resist.

[0015]

By using the present invention, the dimensional controllability of fine processing is improved without being affected by the resist deformation due to the heat treatment of photolithography, and
It is possible to minimize the number of dummy patterns. Therefore, it is possible to provide a semiconductor device capable of reducing the chip area.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process of a semiconductor device of the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing process of a semiconductor device of the present invention.

FIG. 3 is a plan view showing a manufacturing process of a semiconductor device of the present invention.

FIG. 4 is a cross-sectional view showing a manufacturing process of a semiconductor device of the present invention.

FIG. 5 is a plan view showing the manufacturing process of the semiconductor device of the invention.

FIG. 6 is a cross-sectional view showing the manufacturing process of the semiconductor device of the invention.

FIG. 7 is a plan view showing a manufacturing process of a conventional semiconductor device.

FIG. 8 is a sectional view showing a manufacturing process of a conventional semiconductor device.

FIG. 9 is a plan view showing a manufacturing process of a conventional semiconductor device.

FIG. 10 is a cross-sectional view showing a manufacturing process of a conventional semiconductor device.

FIG. 11 is a cross-sectional view showing a manufacturing process of a conventional semiconductor device.

[Explanation of symbols]

 11 gate oxide film 12 element isolation region 13 floating gate 14 groove pattern 15 control gate 100 conductive layer 101 isolated resist pattern 102 continuous resist pattern 103 isolated resist opening (groove pattern) 201 semiconductor substrate 202 silicon oxide film 203 polysilicon Layer 204 Positive resist 205 Isolated resist opening (groove pattern) 206 Dummy pattern surrounding the outermost periphery

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 29/792

Claims (10)

[Claims] 1. A method of manufacturing a semiconductor device, including the step of forming a regularly arranged pattern on a semiconductor substrate by using photolithography, the step of forming a conductive layer on the semiconductor substrate; A step of applying a resist on the layer; and a step of selectively opening the resist in a predetermined pattern, wherein the predetermined pattern is a regularly arranged matrix pattern or the matrix pattern. A method for manufacturing a semiconductor device, comprising: a dummy pattern having a moat shape surrounding an outer peripheral portion. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate is a bare semiconductor substrate or a semiconductor substrate having a film formed on a surface thereof. 3. The resist width between the outermost periphery of the matrix pattern and the dummy pattern is equal to or smaller than the resist width between adjacent patterns of the matrix pattern. The method of manufacturing a semiconductor device according to claim 1, wherein 4. The method of manufacturing a semiconductor device according to claim 1, wherein the resist is a positive resist or a negative resist. 5. The method of manufacturing a semiconductor device according to claim 1, wherein after the step of selectively opening, the semiconductor substrate is subjected to heat treatment at 100 ° C. or higher. 6. A step of forming a device isolation oxide film and a thin film oxide film for a gate oxide film on a semiconductor substrate, and a floating gate for the device isolation oxide film and a thin film oxide film for the gate oxide film. A step of forming a conductive layer, a step of applying a resist on the conductive layer, with respect to the resist, a groove-shaped predetermined pattern for forming a floating gate and a moat shape surrounding the outer periphery of the predetermined pattern A method of manufacturing a semiconductor device, comprising the step of simultaneously forming a dummy pattern. 7. The resist width between the outermost periphery of the matrix pattern and the dummy pattern is equal to or smaller than the resist width between adjacent patterns of the matrix pattern. The method of manufacturing a semiconductor device according to claim 1, wherein 8. The method of manufacturing a semiconductor device according to claim 1, wherein the resist is a positive resist or a negative resist. 9. The method of manufacturing a semiconductor device according to claim 1, wherein after the step of selectively opening, the semiconductor substrate is heat-treated at 100 ° C. or higher. 10. A step of forming a conductive layer on a semiconductor substrate, a step of applying a resist on the conductive layer, a step of forming at least two groove patterns in the resist, and a moat shape surrounding the groove. Forming the dummy pattern simultaneously, heating the resist having the groove pattern and the dummy pattern, and patterning the conductive layer using the heated resist having the groove pattern and the dummy pattern A method of manufacturing a semiconductor device, comprising: