JP2008139424A - Base material for manufacturing semiconductor device and method of manufacturing semiconductor device using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a substrate from warping by a stress relaxation pattern, to eliminate the problem of a decrease in strength of a stress relaxation pattern, and to suppress outflow of cooling gas through the stress relaxation pattern according to need. <P>SOLUTION: A base material has the substrate 1, a mask layer 2 having a processing pattern 4 for etching processing of the substrate 1, and the stress relaxation pattern 3 provided in a peripheral area 4b of the mask layer 2 to relax internal stress warping the substrate 1, and the stress relaxation pattern 3 is provided in a discontinuous pattern shape from an inside position to an outer circumferential position of the substrate 1 and includes a hole pattern portion 3a. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device manufacturing base material applied to manufacturing a semiconductor device by etching through a mask layer on a substrate and a semiconductor device manufacturing method using the same.

  In manufacturing a semiconductor device, a thin film such as a mask layer or a pattern forming layer for patterning is formed on a substrate by a film forming method such as vapor deposition or plating, and patterning is performed by etching through the mask layer. A thin film such as a mask layer formed on such a substrate warps the substrate by its own internal stress. Although the warpage of the substrate is released by patterning, the patterning performed in the warped state is displaced by the amount of the return of the warpage of the substrate. Such warpage of the substrate and the positional deviation caused thereby become more problematic as the substrate becomes thinner, and the pattern formed on the substrate becomes finer and more accurate, and the permissible width has recently become smaller.

  In order to solve such a problem, a technique for forming a slit that relaxes the internal stress in a thin film that causes warpage of the substrate is already known (see, for example, Patent Documents 1 and 2).

  Patent Document 1 discloses a technique for forming a pattern-shaped light shielding portion on a substrate using a light shielding material, exposing the material to be exposed using the light shielding material, transferring the pattern, and forming various patterns on the material to be exposed. In an exposure mask having a frame-shaped light-shielding film on the periphery of the surface on which the pattern is formed, the frame-shaped light-shielding film is divided into quadrilaterals by slits extending from the inner periphery to the outer periphery. A technique is disclosed in which a negative pattern mask is used as a negative pattern mask and used by overlapping with a positive pattern mask. Stress due to a light shielding film is dispersed by the division, and pattern deviation due to warpage is reduced.

In Patent Document 2, in manufacturing a photomask layer used in an optical lithography process, a main pattern c as shown in FIG. 9 is provided in a pattern area b1 of a resist b provided on a substrate a as shown in FIGS. In addition, a technique for providing a stress relaxation pattern d as shown in FIGS. 7 and 8 for relaxing or blocking the transmission of internal stress is disclosed. The stress relaxation pattern d shown in FIG. 7 has a slit shape along the outer periphery of the pattern area b1, and the stress relaxation pattern d shown in FIG. 8 has a slit shape having a cross-girder-like pattern shape surrounding the pattern area b1. . Patent Document 2 discloses an example of a case where the pattern area b1 corresponds to the entire area of the substrate and a case where the pattern area b1 corresponds to each of a plurality of arranged chip areas. In any case, the main pattern c formed in the pattern area b1 is used for pattern transfer to the metal thin film e made of chromium which is the lower layer of the resist b.
Japanese Patent No. 3158515 JP 2004-29403 A

  By the way, as the substrate of the semiconductor device becomes thinner, so-called bulk etching in which etching is performed on the substrate itself is required.When a mask layer made of Ni or Cr is provided on the substrate and patterning is performed on the substrate, As in the case where patterning does not reach the substrate itself as described in Patent Documents 1 and 2, the substrate is warped by the internal stress of the mask layer, and patterning deviation is caused by releasing the warp of the substrate after patterning.

  Accordingly, the present inventors have made various attempts to form a stress relaxation pattern in the mask layer. In the case shown in FIG. 10D, a non-penetrating groove-like pattern g is formed in the mask layer f formed on the substrate j, and the strength decreases in the peripheral region of the substrate j that is not a predetermined processing pattern on the substrate j. Etching that causes this phenomenon does not occur, but a sufficient stress relaxation effect cannot be obtained. In the case shown in FIG. 10C, the slit pattern h penetrating the mask layer f is formed, and a sufficient stress relaxation effect can be obtained, but unnecessary etching to the substrate j corresponding to the slit pattern h. The portion i is generated with the same etching depth as the processed pattern portion. In particular, in order to sufficiently relieve stress, when the slit pattern h is continuously extended from the innermost side of the peripheral region of the mask layer f to the outer peripheral position of the substrate as shown in FIG. Since etching is performed on the substrate j itself, the strength of the substrate j is greatly reduced, which becomes a further problem. In addition, when the connected slit-like pattern h reaches the outer periphery from the innermost side of the peripheral area of the substrate j and is opened to the side, etching is performed with gas cooling on the back surface side one by one for both surfaces of the substrate. In this case, there is a problem that a large amount of cooling gas flows out through the slit pattern h and the cooling effect is lowered.

  On the other hand, the slit-shaped pattern h is extended to the peripheral area of the mask layer f in a discontinuous pattern shape that does not connect from the inside to the outer peripheral position of the substrate j, and a large number of slit patterns h are arranged or expanded in this way. Even if the slit-shaped patterns h to be arranged are continuous, the slit-shaped pattern h is formed under the condition that it is less than the effective width dimension of the processed pattern as illustrated in FIG. If an unnecessary etching process does not proceed to the normal etching depth in the etching process, and an etch regulation phenomenon is obtained, the slit-like pattern is sufficiently prevented from warping the substrate j with sufficient stress relaxation. It has been found that the strength reduction of the substrate j due to unnecessary etching through the h portion can be prevented.

  At the same time, the inventor formed the hole pattern k as shown in FIG. 10A, which is more effective in controlling the etching of the substrate j than the slit pattern h and is equal to the width of the slit pattern h. The etching depth to the substrate j as the hole pattern k having a diameter is sufficiently smaller than that of the slit pattern h. Depending on the diameter, as shown in FIG. 10A, the etching depth to the substrate j is provided even under the condition of almost zero.

  The object of the present invention is to prevent the warpage of the substrate by the stress relaxation pattern that relieves the internal stress that warps the substrate based on such new knowledge, and further, there is no problem of the strength reduction of the stress relaxation pattern substrate and is necessary. Accordingly, an object of the present invention is to provide a semiconductor device manufacturing substrate capable of suppressing the outflow of cooling gas through the stress relaxation pattern and a semiconductor device manufacturing method using the same.

  In order to achieve the above object, according to the semiconductor device manufacturing substrate of the first aspect of the present invention, a substrate, a mask layer having a processing pattern for performing etching on the substrate, and the mask A stress relaxation pattern provided in the peripheral area of the layer to relieve internal stress that warps the substrate, and this stress relaxation pattern is provided in a discontinuous pattern shape from the inner position to the outer peripheral position of the substrate, and the stress relaxation pattern is a hole pattern It is characterized by including a part.

  According to such a feature, by providing a stress relaxation pattern in the peripheral region of the mask layer having a processing pattern for performing etching processing on the substrate, the internal stress of the mask layer is sufficiently relaxed according to the pattern, and the substrate Since the stress relaxation pattern includes the hole pattern portion and is discontinuously formed from the inner position to the substrate outer peripheral position, the hole pattern portion allows the stress relaxation pattern to pass through the substrate during etching processing. While suppressing unnecessary etching more advantageously, even if etching proceeds in the same manner as the processing pattern except for the hole pattern, the strength reduction of the substrate can be sufficiently suppressed. In addition, even when a mask layer is provided on both sides of the substrate and etching is performed with gas cooling on the back side of each side, the stress relaxation pattern is discontinuous from the innermost side of the peripheral region of the mask layer to the outer peripheral position of the substrate. Thus, the cooling gas can be prevented from flowing out from the outer peripheral position of the substrate through the stress relaxation pattern. Moreover, even if the various pattern portions are hole pattern portions, in the relationship between the substrate and the mask layer, the internal stress is easily divided or dispersed in the peripheral area of the mask layer according to the direction and position where the stress needs to be relaxed. In addition, it is easy to arrange a large number of stress relaxation positions so as to increase the stress relaxation position, which is suitable for preventing warpage of the substrate due to stress relaxation.

  According to the semiconductor device manufacturing substrate of the second aspect of the present invention, in the first aspect, the hole pattern portion is further a round hole.

  According to such a feature, the round hole is particularly advantageous for suppressing etching of the substrate and has no direction in itself, but various directions are obtained depending on the arrangement, and internal stress in the direction intersecting the arrangement direction is divided. can do.

  According to the semiconductor device manufacturing substrate of the third aspect of the present invention, in any one of the first and second aspects, the stress relaxation pattern is less than a normal etch depth or an etch depth on the substrate. It is characterized in that the etching is suppressed to be less than the effective dimension of the processing pattern so that is substantially zero.

  According to such a feature, unnecessary etching through the stress relaxation pattern generated during the etching process on the substrate is processed according to the size of the stress relaxation pattern while preventing the warpage of the substrate by the stress relaxation of the mask layer by the stress relaxation pattern. Since it is possible to control the etching so that the etching depth is less than the normal etching depth or the etching depth is almost zero by the pattern, it is possible to further suppress the decrease in the strength of the substrate due to unnecessary etching, and the decrease in the strength of the substrate tends to be a problem. This is particularly effective as a stress relaxation pattern disposed in a mask layer of a thin substrate or in a range near the outer periphery of the mask layer. Note that the etch depth is substantially zero, which means that the etch depth is substantially 0 μm, and does not adversely affect stress relaxation. For example, an etch depth of about ± 1 μm is included in the etch depth range of substantially 0 μm. It is what

  According to the semiconductor device manufacturing substrate of the fourth aspect of the present invention, in any one of the first to third aspects, the stress relaxation pattern further includes an innermost slit along the outer periphery of the processing pattern area. The hole pattern part in a 1st aspect is arrange | positioned independently of the slit-shaped pattern part on the outer side of this slit-shaped pattern part, It is characterized by the above-mentioned.

  According to such a feature, the processing pattern area area and the peripheral area are separated from each other using the continuity such as the rectangular shape of the slit-shaped pattern portion along the outer periphery of the processing pattern area on the innermost side in the peripheral area of the mask layer. In addition to the dispersion of internal stress in the radial direction due to the substantial division, the peripheral region is provided by ensuring discontinuity of the hole pattern portion in the first aspect disposed independently of the slit-shaped pattern portion outside the slit-shaped pattern portion. By distributing the internal stress in the circumferential direction and in the radial direction, the stress relaxation effect can be enhanced without problems of substrate strength reduction or cooling gas outflow.

  According to the semiconductor device manufacturing substrate of the fifth aspect of the present invention, in the fourth aspect, the hole pattern portion is further provided in a row aligned from the slit-shaped pattern portion side toward the outer peripheral side of the substrate, The columns are arranged in units of single-row blocks, multiple-row blocks, and cross-row blocks.

  According to such a feature, the hole pattern portion intersects in the direction in which the holes are arranged while dividing and dispersing the internal stress proportional to the size of the holes and the arrangement pitch in the direction in which the holes are arranged. Since the internal stress in the direction can be divided, it is easy to prevent warping of the substrate while exhibiting high discontinuity and prevention of strength reduction of the substrate.

  According to the method for manufacturing a semiconductor device of the sixth aspect of the present invention, the substrate is warped with a processing pattern for etching the substrate and a discontinuous pattern shape in the peripheral area from the inner position to the outer peripheral position of the substrate. Etching of the substrate through a mask layer formed on the substrate having the stress relaxation pattern in the semiconductor device manufacturing substrate according to any one of the first to fifth aspects of the present invention for relaxing internal stress And a step of performing the process.

  According to such a feature, the internal stress of the mask layer is relaxed by the stress relaxation pattern on the substrate using any one of the semiconductor device manufacturing base materials of the first to fifth aspects of the present invention. Semiconductor devices are manufactured by etching the substrate with no warpage or reduced warpage, and the strength of the substrate decreases due to unnecessary etching of the substrate through the stress relaxation pattern when etching the substrate In addition, it is possible to prevent the cooling effect from deteriorating by suppressing the outflow of the cooling gas through the stress relaxation pattern when etching is performed with gas cooling on the back surface of each side of each side of the substrate. it can.

  According to the semiconductor device manufacturing substrate of the seventh aspect of the present invention, in any one of the first to fifth aspects, the mask layer is further formed on both surfaces of the substrate. .

  As described above, any one of the semiconductor device manufacturing substrates according to the first to fifth aspects of the present invention includes the seventh aspect of the present invention in which the mask layer is formed on both surfaces of the substrate. The method for manufacturing a semiconductor device according to the sixth aspect includes the eighth aspect of the present invention, wherein the substrate etching step is performed on both sides of the substrate one side at a time while gas cooling is performed on the back side.

  According to the semiconductor device manufacturing substrate and the semiconductor device manufacturing method using the same according to the present invention, the internal stress of the mask layer is sufficiently relaxed by the stress relaxation pattern provided in the peripheral area of the mask layer, and the substrate is warped. In addition, the substrate strength reduction due to unnecessary etching through the stress relaxation pattern accompanying the etching process to the substrate is not continuous from the innermost side of the mask layer to the substrate outer peripheral position, and the depth due to the hole pattern part Can be easily suppressed by suppressing to less than the normal etch depth including almost zero, and further, the cooling gas can be etched through the stress relaxation pattern to perform etching processing with gas cooling on one side for each side of the substrate. Outflow from the outer periphery to the outside can be suppressed.

  Hereinafter, a semiconductor device manufacturing substrate of the present invention and a semiconductor device manufacturing method using the same will be described with reference to FIGS. However, the following description is a specific example of the present invention and does not limit the content of the claims.

The semiconductor device manufacturing substrate of the present embodiment is a mask having a substrate 1 and a processing pattern 4 as shown in FIG. 5C for performing etching processing on the substrate 1, as in the example shown in FIG. The internal stress of the layer 2 and the mask layer 2 provided in the peripheral region of the mask layer 2 as shown in the example of FIG. 1, the example of FIG. 2, the example of FIG. 3, and the example of FIG. The stress relaxation pattern 3 is provided. Here, the substrate 1 is, for example, quartz, glass, PX, quartz, LT, LN, SiC, sapphire, Si, etc., and various types including difficult-to-etch materials can be adopted, and the thickness is about 400 μm or less. Generally used, it is thin and has a thickness of about 100 μm. The mask layer 2 is made of Al, Ti, SiN, SiO ₂ , Au, etc. in addition to Ni and Cr. These are formed on the substrate 1 by a film forming method such as vapor deposition or plating, exhibiting substantially shrinking internal stress, causing the substrate 1 to bend in the mask layer 2 side, and patterning by the etching process described above. This is a problem of displacement. However, the mask layer 2 has a tensile internal stress with respect to the substrate 1 and may warp the substrate 1 in the opposite direction. In general, the present invention is applied to the mask layer 2 made of a material having an internal stress that warps the substrate 1 regardless of the warping direction of the substrate 1.

  As described above, the stress relaxation pattern 3 relaxes the stress that causes the warpage of the substrate 1 by dispersing the internal stress of the mask layer 2, and prevents or reduces the warpage of the substrate 1. In order to manufacture a semiconductor device having a process of etching through the processing pattern 4, the warp due to the mask layer 2 of the substrate 1 is prevented and reduced by the stress relaxation pattern 3. Patterning deviation due to processing is reduced, and patterning accuracy is improved.

  However, the stress relaxation pattern 3 of the mask layer 2 also becomes an unnecessary etching portion that reduces the strength of the substrate 1 during the etching process on the substrate 1. In order to cope with this, as an example in the present embodiment, the stress relaxation pattern 3 provided in the peripheral region 4b of the mask layer 2 is as shown in each example individually shown in FIGS. In addition, it is provided in a discontinuous pattern shape from the inner position to the outer peripheral position of the substrate 1, and the stress relaxation pattern 3 includes a hole pattern portion 3a.

  Therefore, by providing the stress relaxation pattern 3 in the peripheral region 4b of the mask layer 2 having the processing pattern 4 for etching the substrate 1, the internal stress of the mask layer 2 is sufficiently relaxed according to the pattern shape. In addition to preventing or reducing the warpage of the substrate 1, the stress relaxation pattern 3 includes the hole pattern portion 3a and is formed discontinuously from the inner position of the peripheral area 4b to the outer peripheral position of the substrate 1. The hole pattern portion 3a shown in FIG. 5 (a) suppresses unnecessary etching through the stress relaxation pattern 3 during the etching process of the substrate 1 more advantageously than the slit-like pattern portion 3b shown in FIG. 5 (b). However, even if unnecessary etching through the stress relaxation pattern 3 proceeds in the same manner as the processing pattern when etching the substrate 1 other than the hole pattern portion 3a, unnecessary etching is performed. Compared to the case where the portions are not continuous, and unnecessary etched portions are continuously formed in a line along the slit connected from the inside to the outer peripheral position of the substrate 1 as in the preceding example shown in FIG. The strength reduction of the substrate 1 can be suppressed.

  Moreover, although not shown, even when the mask layer 2 is provided on both surfaces of the substrate 1 and etching is performed with gas cooling with a cooling gas such as He gas on the back surface of each surface, the stress relaxation pattern 3 is in the peripheral region of the mask layer 2. Since the discontinuity that does not connect from the innermost side of 4b to the outer peripheral position of the substrate 1 prevents the cooling gas from flowing out from the outer peripheral position of the substrate 1 through the stress relaxation pattern 3, the cooling efficiency seems to decrease. It is a long time.

  Here, as shown in FIGS. 5A and 5B, the stress relaxation pattern 3 has an etching depth H2 in unnecessary etching through the etching pattern 4 of the substrate 1 shown in FIG. 5C. It is provided with a size that suppresses etching so that the normal etching depth H1 by processing or less than the depth H2 becomes almost zero. This prevents unnecessary etching through the stress relaxation pattern 3 that occurs during etching processing on the substrate 1 depending on the size of the stress relaxation pattern 3 while preventing warping of the substrate 1 by stress relaxation of the mask layer 2 by the stress relaxation pattern 3. Since the etching can be controlled so that it is usually less than the etching depth H1, the strength of the substrate 1 is reduced by unnecessary etching caused by the stress relaxation pattern 3 from the inner side to the outer peripheral position of the substrate 1 as in the previous example. The range near the periphery of the mask layer 2 of the thin substrate 1 and the substrate 1 of various thicknesses can be sufficiently suppressed without the restriction of discontinuity, and the strength reduction of the substrate 1 is likely to be a problem. This is particularly effective as the stress relaxation pattern 3 or the like to be disposed on the surface. Note that the etch depth is substantially zero, which means that the etch depth is substantially 0 μm, and does not adversely affect stress relaxation. For example, an etch depth of about ± 1 μm is included in the etch depth range of substantially 0 μm. It is what

  For this purpose, as shown in FIGS. 5A and 5B, the width B2 or the diameter B2 of the stress relaxation pattern 3 is made smaller than the effective width B1 or the diameter of the processing pattern 4 shown in FIG. Is preferred. In this case, since the stress relaxation pattern 3 is set to the effective width B1 or the width B2 or the diameter B2 less than the diameter of the processing pattern 4, the correlation between the etching width or the diameter and the etching depth as shown in FIG. The substrate has the effect of suppressing the etching referred to as microloading effect, and suppresses unnecessary etching through the stress relaxation pattern 3 accompanying the etching process on the substrate 1 by reducing the width B2 and the diameter B2. It is possible to make H2 less than the normal etching depth H1 due to the etching process to 1, and the strength reduction of the substrate 1 can be further suppressed. In particular, the hole pattern portion 3a has a higher etching suppression effect than the slit pattern portion 3b. This seems to be due to the fact that the gas confinement action in the hole pattern portion 3a is high and is not easily updated. In particular, if the hole pattern portion 3a is a round hole as in each example shown in FIGS. 1 to 4, it is advantageous for suppressing etching of the substrate 1 and has no directivity in FIGS. Various orientations are obtained by the arrangement as shown in the examples, and the internal stress in the direction intersecting the arrangement direction can be divided.

  From the inventor's experience, the width B2 and the diameter B2 of the stress relaxation pattern 3 with respect to the width B1 of the processed pattern 4 are set to about 1/4 to 1/20, and the etch depth H2 is suppressed to about 5 to 20 μm. In the pattern portion 3a, as shown in FIG. 5A, the etch depth H2 of the substrate 1 can be made substantially zero.

  The cross-sectional shape of the hole pattern portion 3a formed as a round hole is a straight cross-sectional shape in FIGS. 5A and 5B, but may be a tapered shape whose cross-section narrows toward the substrate 1 side. Thereby, the etching depth to the substrate 1 is made less than the normal etching depth by the etching stop that regulates the progress of the etching early due to the residue falling from the tapered surface of the mask layer 2 to suppress the strength reduction of the substrate 1. Can do.

  In one embodiment, the processing pattern 4 is formed under processing conditions in which the thickness of the substrate 1 made of quartz is about 150 μm, the thickness of the mask layer 2 made of Ni is about 2 μm, and the normal etching depth H1 by etching is about 50 μm. The minimum effective width B1 is about 10 μm. On the other hand, the width B2 of the slit-like pattern portion 3b of the stress relaxation pattern 3 is set to about 2 μm or less, and the etch depth H2 of the substrate 1 is suppressed to about 10 μm or less. The diameter B2 of the hole pattern portion 3a of the hole was set to about 2 μm or less, and the etch depth H2 of the substrate 1 could be made substantially zero, and the strength reduction of the substrate 1 could be sufficiently suppressed.

The processing conditions are as follows. The dilution gas is argon or helium, and usually C ₄ F ₈ / dilution gas = 10-30 / 0-120 sccm, 0.5-2.0 Pa, ICP / Bias = 1000-2000 / 200-600 W, electrode temperature− Although it is set to 20 ° C., this time, C ₄ F ₈ / dilution gas = 30 sccm, pressure 0.5 Pa, ICP = 1500 W, Bias = 350 W, and CF type polymer deposition is generated, and etch stop effect Thus, the etching process in the hole pattern portion 3a can be particularly suppressed by the gas containment action in the hole pattern portion 3a. However, since the conditions have apparatus-specific parameters, some of the conditions may fall outside the above range (the apparatus under the present processing conditions was tested with model E-620 manufactured by Panasonic Factory Solutions). .

  The stress relaxation pattern 3 of the present embodiment has an innermost slit-like pattern portion 3b along the outer periphery of the processing pattern area 4a as in each example shown in FIGS. 1 to 4, and this slit-like pattern portion. A hole pattern portion 3a is disposed outside 3b independently of the slit pattern portion 3b. As a result, the processing pattern area 4a region using the continuity such as forming a rectangle of the slit-shaped pattern portion 3b along the outer periphery of the processing pattern area 4a on the innermost side in the peripheral region 4b of the mask layer 2 and the peripheral region 4b. In addition to the dispersion of the internal stress in the radial direction due to the division or almost the division, in the peripheral area 4b, the discontinuity of the hole pattern portion 3a arranged outside the slit-like pattern portion 3b is ensured. By distributing the internal stress in the circumferential direction and in the radial direction, the stress relaxation effect can be enhanced without problems of the strength reduction of the substrate 1 and the outflow of the cooling gas.

  The hole pattern portion 3a in each example shown in FIGS. 1, 2, 3, and 4 is provided in a row lined from the slit-shaped pattern portion 3b side to the outer peripheral side of the substrate 1. For example, the row is a diagram. 1 are arranged in units of a single row block, in units of a plurality of rows as in the examples shown in FIGS. 2 and 3, and in units of a cross block as in the example shown in FIG. Such a hole pattern portion 3a has an internal stress in a direction intersecting the direction in which the holes are arranged while dividing and dispersing the internal stress in proportion to the size of the holes and the arrangement pitch in the direction in which the holes are arranged. Therefore, it is easy to prevent warping of the substrate 1 while exhibiting high discontinuity and prevention of strength reduction of the substrate. As the arrangement density of the hole pattern portions 3a is higher as in the example shown in FIG. 2, the dispersion degree of the internal stress can be increased. In the staggered arrangement as in the examples shown in FIGS. A certain stress distribution can be realized in a wide area. In addition, in the cross-row arrangement as in the example shown in FIG. 4, in particular, in the XY2 direction perpendicular to each other along the cross, the stress can be distributed in the direction perpendicular to the XY2 direction, and in addition, the intermediate direction of these XY2 directions. Even in two oblique directions perpendicular to each other, stress distribution can be achieved in a direction perpendicular to the arrangement direction of the hole pattern portions 3a.

  Here, in order to manufacture a semiconductor device using various semiconductor device manufacturing bases as described above, the processing pattern 4 for performing etching processing on the substrate 1 and the outer periphery of the substrate 1 from the inner position to the peripheral region 4b. The discontinuous pattern shape is not connected to the position, and the etching depth H2 is set to have a size that suppresses etching so that the etching depth H2 is less than the normal etching depth H1 by the etching process through the processing pattern 4 of the substrate 1. What is necessary is just to provide the process of etching the board | substrate 1 through the mask layer 2 formed on the board | substrate 1 with the stress relaxation pattern 3 containing the hole pattern part 3a. As a result, the stress relaxation pattern 3 provided in the peripheral region 4b of the mask layer 2 sufficiently relaxes the internal stress of the mask layer 2 and prevents the substrate 1 from warping, and is accompanied with the etching process to the substrate 1. The unnecessary etching through the stress relaxation pattern 3 is a discontinuity that cannot be connected from the innermost side to the outer peripheral position of the substrate 1 in the peripheral region 4b of the mask layer 2, and is suppressed to less than the normal etching depth H1. 1 can be easily suppressed from causing a decrease in strength, and etching is performed with gas cooling on the back surface of each side of each side of the substrate 1, but the cooling gas flows out from the outer periphery of the substrate 1 through the stress relaxation pattern 3. Can be suppressed.

  In the bulk etching through the mask of the substrate, the present invention prevents the substrate from being warped by the stress relaxation pattern provided in the mask layer, while reducing the strength of the substrate due to unnecessary etching caused by the stress relaxation pattern, and through the stress relaxation pattern. The outflow of cooling gas can be prevented.

It is a top view of the important section showing the 1st example of the semiconductor device manufacture base material of the embodiment concerning the present invention. It is a top view which shows the 2nd example of the semiconductor device manufacturing base material of embodiment which concerns on this invention. It is a partial top view which shows the 3rd example of the semiconductor device manufacturing base material of embodiment which concerns on this invention. It is a partial top view which shows the 4th example of the semiconductor device manufacturing base material of embodiment which concerns on this invention. The hole pattern example (a) and the slit pattern example (b) of the stress relaxation pattern having the etching suppression effect of the mask applied to the substrate shown in FIGS. 1 to 4 are compared with the processing pattern example (c). FIG. It is a graph which shows the microloading effect characteristic by the correlation with the stress relaxation pattern and the width | variety of a process pattern, and an etch depth. It is a top view which shows one example of the conventional semiconductor device manufacture base material. It is a top view which shows another example of the conventional semiconductor device manufacture base material. It is sectional drawing which shows the mask in the conventional base material shown in FIG. 7, FIG. 8, and the patterning state by it. It is sectional drawing shown to (a)-(d) of the three types of experiment examples which the inventor did in the process leading to this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate 2 Mask layer 3 Stress relaxation pattern 3a Hole pattern portion 3b Slit pattern portion 4 Processing pattern 4a Processing pattern area 4b Peripheral region

Claims (8)

A substrate, a mask layer having a processing pattern for performing etching on the substrate, and a stress relaxation pattern provided in a peripheral area of the mask layer for relaxing internal stress that warps the substrate, the stress relaxation pattern being A semiconductor device manufacturing base material provided with a discontinuous pattern shape from an inner position to a substrate outer peripheral position, and the stress relaxation pattern includes a hole pattern portion. The semiconductor device manufacturing substrate according to claim 1, wherein the hole pattern portion is a round hole. 3. The etching according to claim 1, wherein the stress relaxation pattern is controlled to be less than an effective dimension of the processing pattern so that the stress relaxation pattern is less than a normal etch depth to the substrate or an etch depth is substantially zero. Semiconductor device manufacturing base material. The stress relaxation pattern has an innermost slit-shaped pattern portion along the outer periphery of the processing pattern area, and the hole pattern portion according to claim 1 is independent of the slit-shaped pattern portion outside the slit-shaped pattern portion. The semiconductor device manufacturing base material according to claim 1, wherein the semiconductor device manufacturing base material is disposed. 5. The hole pattern portion is provided in a row aligned from the slit-shaped pattern portion side toward the outer peripheral side of the substrate, and the rows are arranged in units of single-row blocks, multi-row blocks, or cross-row blocks. The semiconductor device manufacturing base material as described in 2. The processing pattern for performing etching processing on the substrate and the internal stress that has a discontinuous pattern shape from the inner position to the outer peripheral position of the substrate in the peripheral area and relaxes the internal stress that warps the substrate. And a step of etching the substrate through a mask layer formed on the substrate having the stress relaxation pattern in the manufactured semiconductor device manufacturing substrate. A method for manufacturing a semiconductor device, comprising: The semiconductor device manufacturing base material according to claim 1, wherein the mask layer is formed on both surfaces of the substrate. The method for manufacturing a semiconductor device according to claim 6, wherein the substrate etching step is performed on each side of the substrate one side at a time while gas cooling is performed on the back side.

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