KR20090067707A

KR20090067707A - Semiconductor device

Info

Publication number: KR20090067707A
Application number: KR1020070135458A
Authority: KR
Inventors: 이혜성
Original assignee: 주식회사 동부하이텍
Priority date: 2007-12-21
Filing date: 2007-12-21
Publication date: 2009-06-25

Abstract

A semiconductor device is provided to form uniformly a photoresist layer by improving coating uniformity of a BARC(Bottom-Anti-Reflect-Coating) layer through a dummy pattern insertion process. A semiconductor device includes a substrate, a semiconductor device layer, and a metal line layer. The semiconductor device layer is formed on an upper surface of the substrate. The semiconductor device layer includes a plurality of wiring circuit patterns. A plurality of dummy patterns(100) are formed on a region on which the wiring circuit patterns are not formed. The dummy patterns are arranged in a matrix structure. The dummy patterns are inserted to improve coating uniformity of a BARC layer. An upper metal line layer is formed on the semiconductor device layer.

Description

Semiconductor device

Embodiments disclose a semiconductor device including a dummy pattern.

Various kinds of semiconductor elements and circuit elements are integrated on one wafer, and various types of semiconductor designs are made. In particular, in the case of a semiconductor device designed with an irregular pattern density, the process control is very difficult because a lot of changes occur in the process progress conditions.

In the case of the etching process, a low pattern density may cause the photoresist to be coated at a non-uniform height, defocused during exposure to form a size and shape outside the design criteria, or some patterns may not be formed at all. .

FIG. 1 is a diagram illustrating a pattern layout of a semiconductor device, and FIG. 2 is an enlarged view of part “A” of FIG. 1, and FIG. 3 is a layer structure of a semiconductor device with and without a low density pattern. A side cross-sectional view shown in comparison.

When the pattern is evenly distributed at a density of about 20% to 40%, the photoresist may be faithfully formed in the pattern design. However, when the pattern is formed at a density of less than 5% as shown in FIG. 1, only a part of the pattern as shown in FIG. This phenomenon occurred.

In order to examine the cause of this phenomenon, as a result of observing the side cross-sectional image of the semiconductor device, it was confirmed that the photoresist is irregularly coated as shown in FIG.

FIG. 3A is a side cross-sectional view when there is a low density pattern, that is, the area "A" of FIG. 1, and (b) is a side cross-sectional view of the "B" area when there is no pattern, that is, FIG.

In the " A " region, there is an active layer 12 having a low density pattern formed on the substrate 10, and a BARC (Bottom-Anti-Reflect-Coating) layer 14 and a photoresist layer 16 thereon.

At this time, the level difference generated due to the low density pattern of the active layer 12 is not canceled by the BARC layer 14 and affects the upper photoresist layer 16.

That is, the low density pattern affects the coating uniformity of the BARC layer 14, resulting in a phenomenon such as defocusing upon exposure.

On the other hand, in the "B" region, since there is no pattern, it can be seen that the thicknesses of the substrate 20, the active layer 22, the BARC layer 24, and the photoresist layer 26 are uniformly formed.

The BARC layer used in the photolithography process is classified into a planar type coated flat regardless of the topology of the lower layer and a conformal type coated along the topology of the lower layer. Even in the case of the known planar type, it was confirmed that the BARC layer could not play a sufficient role in the low density pattern.

The embodiment provides a semiconductor device having an improved structure so that the photoresist layer can be uniformly formed even when a low density pattern is formed in the lower layer.

A semiconductor device according to the embodiment includes a substrate; A semiconductor device layer formed on the substrate and including a wiring circuit pattern and having a dummy pattern formed in a region where the wiring circuit pattern is not formed; It includes an upper metal wiring layer formed on the semiconductor device layer.

According to the embodiment, the following effects are obtained.

First, through the insertion of the dummy pattern, it is possible to improve the coating uniformity of the BARC layer, and thus has the effect of forming the photoresist layer at a uniform height.

Second, since the photoresist layer can be formed at a uniform height, there is an effect that can be accurately formed in accordance with the design criteria during the exposure process.

Second, as the photoresist pattern is uniformly formed, problems such as dishing may be prevented when the planarization process is performed.

A semiconductor device according to an embodiment will be described in detail with reference to the accompanying drawings.

4 is a top view illustrating an arrangement structure of a dummy pattern 100 according to an exemplary embodiment, and FIG. 5 is an enlarged view of portion “C” of FIG. 4.

As shown in FIG. 4, a plurality of dummy patterns 100 according to the embodiment are arranged in a matrix structure.

The dummy pattern 100 according to the embodiment is formed in the semiconductor device layer, which includes a source electrode, a gate electrode, a drain electrode, a source region, a drain region, and the like, and a wiring circuit pattern is formed.

When the upper metal wiring layer is formed on the semiconductor device layer, a BARC layer and a photoresist layer are formed, and a photoresist pattern is formed through a photolithography process.

Thereafter, the upper metal wiring layer may be formed through an etching process, a metal filling process, a planarization process, an insulating layer deposition process, or the like.

However, in this case, the thickness of the BARC layer and the photoresist layer may be unevenly formed depending on the region where the semiconductor structure including the wiring circuit pattern is densely formed and the region where the semiconductor structure is not formed.

In order to prevent such a case, the dummy pattern 100 is disposed in a region in which a wiring circuit pattern is not formed in the semiconductor device layer, as in the “B” region of FIG. 1.

The number, size, and arrangement of the dummy patterns 100 can be adjusted according to the pattern density on the mask design, and are to ensure the uniformity of the photoresist layer. Therefore, the dummy patterns 100 need not be formed as large as the dummy patterns for other applications.

In addition, the substrate may be formed by etching, or may be formed on another layer such as a metal wiring layer, an insulating layer, or the like.

As shown in FIG. 5, the dummy pattern 100 has a width d1 of 300 nm to 1 μm, a length d2 of 1 μm to 3 μm, and an interval d3 of 0.5 μm to 2 μm with an adjacent dummy pattern. Its size, number and arrangement can be adjusted.

6 is a diagram illustrating a pattern layout of the semiconductor device according to the embodiment.

FIG. 6 illustrates a pattern layout when the dummy pattern 100 is formed in the remaining region except for the region D in which the wiring circuit pattern of the semiconductor device layer is formed.

In this case, the photoresist layer may be formed at a uniform height over the entire region of the semiconductor device.

7 is a side cross-sectional view illustrating a layer structure of a semiconductor device according to an embodiment.

The layer structure of the semiconductor device illustrated in FIG. 7 illustrates a region of the semiconductor device layer 120 in which the dummy pattern 100 is formed without a wiring circuit pattern formed.

In addition, FIG. 7 illustrates the layer structure of the semiconductor device in a process formed up to the semiconductor device layer 120 and before the upper metal wiring layer is formed.

Referring to FIG. 7, the semiconductor device includes a substrate 110 such as a silicon wafer, a semiconductor device layer 120 on which a dummy pattern 100 is formed, a BARC layer 130, and a photoresist layer 140.

The BARC layer 130 suppresses the optical interference phenomenon from the substrate 110 to secure the resolution, which is the most important characteristic of the semiconductor exposure process, and improve the uniformity of the pattern size.

Due to the influence of the dummy pattern 100, the uniformity of the BARC layer 130 and the photoresist layer 140 is secured, which enables accurate focus of the light source during the exposure process.

In addition, when the exposure process and the etching process are processed, and the planarization process is performed, it is possible to prevent a phenomenon that the planarization is not performed well, such as dishing due to the step difference of the photoresist layer 140.

As described above, the BARC layer 130 and the photoresist 140 having a uniform thickness are applied, and as described above, the upper metal wiring layer (not shown) may be formed as the subsequent process is performed.

The present invention has been described above with reference to the preferred embodiments, which are merely examples and are not intended to limit the present invention, and those skilled in the art to which the present invention pertains do not depart from the essential characteristics of the present invention. It will be appreciated that various modifications and applications are not possible that are not illustrated above. For example, each component specifically shown in the embodiment of the present invention can be modified. And differences relating to such modifications and applications will have to be construed as being included in the scope of the invention defined in the appended claims.

1 is a diagram illustrating a pattern layout of a semiconductor device.

FIG. 2 is an enlarged view of a portion “A” of FIG. 1.

3 is a side cross-sectional view comparing the layer structure of a semiconductor device with and without a low density pattern.

4 is a top view illustrating an arrangement structure of a dummy pattern according to an embodiment.

5 is an enlarged view of a portion “C” of FIG. 4.

6 illustrates a pattern layout of a semiconductor device in accordance with an embodiment.

7 is a side cross-sectional view illustrating a layer structure of a semiconductor device according to the embodiment.

Claims

Board;

A semiconductor device layer formed on the substrate and including a wiring circuit pattern and having a dummy pattern formed in a region where the wiring circuit pattern is not formed;

A semiconductor device comprising an upper metal wiring layer formed on the semiconductor device layer.

The method of claim 1, wherein the dummy pattern

A semiconductor device having a width of 300 nm to 1 μm and a length of 1 μm to 3 μm.

The method of claim 1, wherein the dummy pattern

A plurality of semiconductor devices, characterized in that arranged in a matrix structure.

The method of claim 1, wherein the dummy pattern

A semiconductor device, characterized in that the adjacent dummy pattern having a spacing of 0.5μm to 2μm.