JP2004336065A - Semiconductor integrated circuit device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce leakage current by reducing defects in an element formation region in which memory cells of a nonvolatile memory are formed. <P>SOLUTION: By elongating an end of a element formation region Ac, in which nonvolatile memory cells are formed, by length D using a region under a dummy conductive film DSG, stress added from an insulating film 6 surrounding the element formation region Ac is concentrated to the elongated region. As a result, since defects are not extended to a region in which memory cells are formed, leakage current of the memory cells can be reduced. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same, and more particularly to a technique effective when applied to a semiconductor integrated circuit device having elongated element formation regions formed in parallel.

  2. Description of the Related Art A semiconductor integrated circuit device includes elements and wirings formed on a main surface of an element forming region (active) partitioned by an insulating film. This element formation region is separated from other element formation regions by, for example, an element isolation region, and the element isolation region is formed by, for example, an element isolation insulating film. The element isolation insulating film is formed using, for example, STI (Shallow Trench Isolation) technology. This STI means that an insulating film such as a silicon oxide film is deposited on a groove formed in a semiconductor substrate, and the silicon oxide film outside the groove is removed by a chemical mechanical polishing (CMP) method or the like. A silicon oxide film is buried inside the groove, and this is used for isolation between elements.

  For example, a memory LSI (Large Scale Integrated Circuit) such as a nonvolatile memory (EEPROM: Electrically Erasable Programmable Read Only Memory) capable of electrically writing and erasing is an elongated element arranged in parallel at a fixed interval (pitch). It is formed on the formation area.

  Such element formation regions tend to be smaller in width and arranged at a narrower pitch as memory cells are miniaturized and highly integrated.

In order to cope with miniaturization of memory cells, a NOR-type flash memory in which a drain contact is formed using a so-called Self-Aligned Contact (SAC) technique is described in, for example, International Electron Devices Meeting (IEDM), 1998, pp979. -982, "A Novel 4.6F2 NOR Cell Technology With Lightly Doped Source (LDS) Junction For High Density Flash Memories" (Non-Patent Document 1).
IEDM (International Electron Devices Meeting), 1998, pp 979-982, "A Novel 4.6F2 NOR Cell Technology With Lightly Doped Source (LDS) Junction For High Density Flash Memories"

  The present inventors have studied the semiconductor memory device, in particular, the nonvolatile memory as described above, and have found the following unknown problem.

  That is, as the element becomes finer, the number of defective memory cells increases. As a result of examining the cause, it is considered that a crystal defect generated at an end of the element formation region may be the cause.

  That is, a peripheral circuit forming region in which a logic circuit and the like (hereinafter, referred to as a peripheral circuit) necessary for driving the memory cell are formed at an outer peripheral portion of the memory cell forming region in the semiconductor integrated circuit device. Therefore, other element formation areas where peripheral circuits are formed are arranged around the narrow element formation areas where the memory cells are formed, which are arranged at a narrow pitch. Separated by a wide insulating film.

  Therefore, as will be described in detail in an embodiment to be described later, stress concentrates at an end portion of an elongated element formation region where a memory cell is formed, and crystal defects easily occur.

  When such a defect occurs, a leak current increases between the drain region of the memory cell and the semiconductor substrate or between the source region and the drain region. Further, when the leak current is equal to or more than the operating current of the sense amplifier, it becomes defective.

  Further, as described above, since a plurality of memory cells are formed on the elongated element formation region, even if a defect occurs in one memory cell, the memory cell is connected to the same data line as the memory cell. All the defective memory cells become defective.

  An object of the present invention is to reduce defects of a semiconductor substrate in an element formation region.

  Another object of the present invention is to reduce leakage current by reducing defects of a semiconductor substrate in an element formation region.

  It is another object of the present invention to improve the yield and reliability of products by reducing leakage current.

  The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

  The outline of typical inventions among the inventions disclosed in the present application will be briefly described as follows.

  (1) In a semiconductor integrated circuit device according to the present invention, an element formation region in which a memory cell is formed is partitioned by an insulating film, and an element formation region extending in a first direction is perpendicular to the first direction. The end of each of the element formation regions arranged two or more in the second direction extends to below the conductive film formed so as to surround the memory cell.

  (2) In the semiconductor integrated circuit device according to the present invention, two or more element forming portions partitioned by the insulating film and extending in the first direction are arranged in a second direction perpendicular to the first direction. The ends of the sections are connected by connecting sections extending in the second direction.

  (3) In the semiconductor integrated circuit device according to the present invention, the element formation region in which the memory cell is formed is partitioned by the insulating film, and the element formation region extending in the first direction is perpendicular to the first direction. The width of the outermost element formation region in the second direction among the plurality of element formation regions arranged in the second direction is made wider than the width of the other element formation regions.

  (4) In the semiconductor integrated circuit device according to the present invention, the element formation region in which the memory cell is formed is partitioned by the insulating film, and the element formation region extending in the first direction is perpendicular to the first direction. A memory cell functioning as a memory cell is not formed on an outermost element formation region among a plurality of element formation regions arranged in the second direction.

  The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.

  An element forming area in which a memory cell is formed, wherein at least two element forming areas defined by an insulating film and extending in a first direction are arranged in a second direction perpendicular to the first direction. Since the end of the formation region is extended below the conductive film formed so as to surround the memory cell, stress can be concentrated on the extended region, and the defect does not extend to the region where the memory cell is formed. In addition, the leak current of the memory cell can be reduced.

  In addition, two or more element forming portions defined by the insulating film and extending in the first direction are arranged in a second direction perpendicular to the first direction, and the ends of the element forming portions extend in the second direction. Since the connection is made at the existing connection portion, the direction in which the stress is applied can be changed, and the leak current of the memory cell can be reduced.

  Also, a plurality of element forming regions, which are formed by an insulating film and extend in the first direction, are arranged in a second direction perpendicular to the first direction. Since the width in the second direction of the outermost element formation region among the element formation regions is wider than the width of the other element formation regions, the influence of stress can be reduced and the leak current of the memory cell can be reduced. can do.

  Also, a plurality of element forming regions, which are formed by an insulating film and extend in the first direction, are arranged in a second direction perpendicular to the first direction. Since the memory cell functioning as a memory cell is not formed on the outermost element formation area in the element formation area, stress can be concentrated on the outermost element formation area, and the leakage current of the memory cell can be reduced. Can be reduced.

  As a result, it is possible to improve product yield and reliability.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1)
FIG. 1 is a plan view of a main part of a semiconductor integrated circuit device according to the present embodiment. The right part of FIG. 1 shows the memory cell formation area MCFR, and the left part shows the peripheral circuit formation area PCFR. NOR type nonvolatile memory cells are arranged in an array MCAR in the memory cell formation region MCFR, and a selection MISFET S is formed as an example of a peripheral circuit in the peripheral circuit formation region. FIG. 2 is a schematic diagram of a cross section taken along the line AA of FIG. 1, and FIG.

  As shown in FIG. 1, in the memory cell formation region, element formation regions (active) Ac extending in the X direction are arranged at regular intervals in the Y direction. This element formation region Ac is partitioned (defined) by an insulating film 6 made of, for example, a silicon oxide film 6 or the like. That is, the element formation regions Ac are separated by the insulating film 6 which is an element isolation insulating film. As shown in FIGS. 2 and 3, the insulating film 6 has, for example, an STI structure embedded in a groove in a semiconductor substrate. The element formation region Ac is a region where the p-type well 8 is exposed on the surface of the semiconductor substrate 1.

  The width W in the Y direction of the element formation region Ac is, for example, about 0.3 μm, and the interval SW between the element formation areas Ac is, for example, about 0.4 μm. The length (width in the X direction) of the element formation region Ac corresponds to, for example, a 128-bit memory cell MC formed in the X direction, and is about 80 μm. That is, a plurality of memory cells MC are formed in the element formation region Ac in the X direction.

  Above the element formation region Ac, control electrodes (second electrodes) CG extending in the Y direction are arranged at regular intervals. The width L of the control electrode CG in the X direction is, for example, about 0.3 μm, and the interval LS between the control electrodes CG is, for example, about 0.35 μm. The control electrode CG is formed integrally with the control electrode CG of the memory cell MC arranged in the Y direction, and becomes a word line WL extending in the Y direction.

  As shown in FIGS. 2 and 3, between the control electrode CG and the element formation region Ac, for example, a stacked film (hereinafter referred to as an ONO film) in which a silicon oxide film, a silicon nitride film, and a silicon oxide film are sequentially stacked ), A floating electrode (first electrode) FG, and a gate insulating film 9 such as a thermal oxide film. The floating electrode FG is formed independently for each memory cell (see FIG. 3).

An n ⁺ -type semiconductor region 17 (source and drain regions) is formed in the element formation region Ac at both ends of the control electrode CG, and a plug (drain contact) DC (P1) is formed on the drain region 17. On the source region 17, a plug (source contact) SC (P1) is formed. The plug DC (P1) is formed independently for each memory cell, but the plug SC (P1) is electrically connected to each of the source regions 17 of the memory cells MC connected to the same word line WL. The source lines SL are connected and extend in the Y direction. That is, the plug (source contact) SC (P1) is a wiring extending in the Y direction and forms the source line SL. As described later, the plug DC (P1) and the plug SC (P1) are formed in the same manufacturing process.

  The drain region 17 has a two-layer structure including a plug DC (P1) and a plug DC (P2), and a sub-bit line SBL is formed on the plug DC (P2). This sub-bit line SBL extends in the X direction.

  The plug SC (P1) is connected to the common source line CSL via the plug SC (P2) as shown in FIG. The common source line CSL also extends in the X direction, and is formed in the same wiring layer as the sub-bit line SBL. As described later, the plug DC (P2) and the plug SC (P2) are formed in the same manufacturing process.

As described above, the memory cell MC mainly includes a pair of n ⁺ -type semiconductor regions 17 serving as source and drain regions, a channel formation region (p-type well) 8 (Ac) formed between them, A gate insulating film 9 formed on the formation region, a floating electrode (floating gate) FG formed on the gate insulating film 9, an insulating film 21 formed on the floating electrode FG, and formed on the insulating film 21 Control electrode (control gate) CG. The source / drain regions 17 of the memory cells MC adjacent in the Y direction are separated by the insulating film 6, and the control electrodes CG of the memory cells MC arranged in the Y direction are formed integrally with the word lines WL. The drain region 17 of the memory cell MC arranged in the Y direction is electrically connected to different sub-bit lines SBL via plugs DC (P1) and DC (P2), and the memory cell arranged in the Y direction. Each of the source regions 17 of the MC is electrically connected by a source line SL. The drain regions of the memory cells MC adjacent in the X direction are configured in common and are electrically connected to the sub-bit line SBL. Source regions 17 of memory cells MC adjacent in the X direction are commonly configured and electrically connected to a source line SL.

  Here, write, read, and erase operations of the memory cell will be described.

  First, the write operation will be described. To write data in the memory cell, a voltage of, for example, 9 V is applied to the control electrode CG (word line WL) of the memory cell, and a voltage of, for example, 4 V is applied to the drain region (sub-bit line SBL) of the memory cell. A voltage of, for example, 3 V is applied to the formation region Ac (the p-type well 8), and the source region (source line SL) of the memory cell is maintained at, for example, 0 V (ground potential). As a result, hot electrons are generated in the channel region (between the source and drain regions) of the memory cell and injected into the floating electrode FG.

  Next, a read operation will be described. To read data from the memory cell, a voltage of, for example, 2.7 V is applied to the control electrode CG (word line WL) of the memory cell, and a voltage of, for example, 0.8 V is applied to the drain region (sub-bit line SBL) of the memory cell. By applying the voltage, the element formation region Ac (p-type well 8) and the source region (source line SL) of the memory cell are maintained at, for example, 0V. At this time, data (“1” or “0”) of the memory cell is read depending on whether or not a current flows between the source and drain regions of the memory cell. When a current flows, it is understood that electrons have not been injected into the floating electrode FG of the memory cell (below the threshold voltage), and for example, data of “0” has been stored. When no current flows, electrons are injected into the floating electrode FG of the memory cell (not less than the threshold voltage), and for example, it is found that "1" data is stored.

  Next, the erase operation will be described. To erase the data written in the memory cell, a voltage of, for example, 10.5 V is applied to the control electrode CG (word line WL) of the memory cell, and the element formation region Ac (p-type well 8) and the drain of the memory cell are drained. A voltage of, for example, 10.5 V is applied to the region (sub-bit line SBL) to maintain the source region (source line SL) of the memory cell in a floating state (open state, open state). As a result, electrons are emitted from the control electrode CG to the channel region (between the source and drain regions) of the memory cell due to the Fowler-Nordheim (FN) tunnel phenomenon.

  In addition, a dummy conductive film DSG formed of the same layer as the control electrode CG is formed on the outer peripheral portion of the memory cell array. This dummy conductive film DSG is formed to reduce the influence of foreign matter generated at the time of forming a memory cell, to reduce a step between a memory cell forming region and a peripheral circuit forming region, and the like.

  This dummy conductive film DSG is also formed on the element formation region (p-type well 8), and between this and the element formation region Ac, for example, an insulating film made of the ONO film 21 or the like, a floating electrode (first electrode). 2) A gate insulating film 9 made of FG, a thermal oxide film and the like is formed (see FIGS. 2 and 3).

On the other hand, a peripheral circuit element forming area LAc is also formed in the peripheral circuit forming area, and a conductive film constituting the gate electrode G of the selection MISFET S is formed on the element forming area LAc. As shown in FIG. 2, the gate electrode G is formed of the same layer as the control electrode CG, and a gate insulating film 9b is formed thereunder. In the element forming region LAc at both ends of the gate electrode G, n ⁺ type semiconductor regions 27 (source and drain regions) are formed.

  Here, as shown in FIG. 1, the element formation region Ac of the memory cell formation region extends from the end of the drain region of the outermost memory cell by the length D in the X direction. In the length D, the distance d1 is a distance in consideration of a shift of a mask used most for forming the element formation region Ac, and the distance d2 is a distance in consideration of a region where a crystal defect occurs. In the present embodiment, d1 is about 0.2 μm and d2 is about 0.3 μm. The size of d2 was set because the length of the crystal defect generated in the element formation region Ac when the memory cell was formed according to the above-described rule was about 0.3 μm.

  As described above, in the present embodiment, since the end of the element formation region Ac is extended, the influence of crystal defects generated in the element formation region Ac can be avoided. As a result, the occurrence of leakage current can be reduced, and the incidence of defective memory cells can be reduced.

  That is, as shown in FIG. 4, the insulating film 6 exists between the element forming regions Ac, and a stress is applied to the element forming region Ac by the insulating film 6 on the outer peripheral portion. In particular, since the insulating film 6 is formed over a wide area on the outer peripheral portion of the memory cell formation region to separate from the peripheral circuit, stress is applied to the end of the element formation region Ac. concentrate. When such a large stress is applied, defects (De1, De2) such as dislocations are generated in the crystal constituting the element formation region Ac. A leak current is generated through the defect, and as described above, if the leak current is equal to or larger than the operating current of the sense amplifier, it becomes defective.

  However, in the present embodiment, since the end of the element formation region Ac is extended, as shown in FIG. 5, the defect De1 extends to the region where the substantial memory cell is formed (memory cell array MCAR). Instead, the leakage current of the memory cell can be reduced.

  A dummy conductive film DSG is formed on the extended portion of the element formation region Ac, and an insulating film such as the ONO film 21, a floating electrode (first electrode) FG, and a thermal oxide film are formed thereunder. A gate insulating film 9 is formed. Therefore, the configuration has a pseudo memory cell structure (however, there is no source region), but since the dummy conductive film DSG is in a floating state without being applied with a potential, No channel is formed, and no leak current occurs.

  Further, in the present embodiment, since the element formation region Ac is extended by using the area under the dummy conductive film DSG, it is possible to take measures against defects without enlarging the memory cell formation region.

  Next, an example of a method for manufacturing the semiconductor integrated circuit device of the present embodiment will be described. 6 to 12 are cross-sectional views of a main part of a substrate showing a method of manufacturing a semiconductor integrated circuit device according to the present embodiment. FIGS. 6 to 8 correspond to the CC cross-section in FIG. FIG. 12 corresponds to a section taken along line DD of FIG.

  First, as shown in FIG. 6, a semiconductor substrate 1 made of p-type single crystal silicon having a specific resistance of, for example, about 1 to 10 Ωcm is thermally oxidized, for example, so that a pad oxide film (FIG. (Not shown). Then, an insulating film such as a silicon nitride film (not shown) is deposited on the pad oxide film, and a photoresist film (not shown) (hereinafter simply referred to as a “resist film”) is used as a mask to form an insulating film on the element isolation region. The silicon nitride film is removed.

  Next, the resist film is removed, and the semiconductor substrate 1 is etched using the silicon nitride film as a mask to form an element isolation groove 4 having a depth of about 250 nm.

  Thereafter, by thermally oxidizing the semiconductor substrate 1 at about 1150 ° C., a thermal oxide film such as a silicon oxide film 5 having a thickness of about 30 nm is formed on the inner wall of the groove. This silicon oxide film 5 recovers the damage of the dry etching generated on the inner wall of the groove and relieves the stress generated at the interface between the silicon oxide film 6 embedded in the groove and the semiconductor substrate 1 in the next step. Formed.

  Next, an insulating film made of, for example, a silicon oxide film 6 having a thickness of about 600 nm is deposited on the semiconductor substrate 1 including the inside of the element isolation groove 4 by a CVD method, and then heat treatment (annealing) is performed at 1150 ° C. for 60 minutes. ) To make the silicon oxide film 6 denser. Next, the silicon oxide film 6 above the groove is polished by the CMP method, the surface thereof is flattened, and then the silicon nitride film is removed. At this time, although the surface of the silicon oxide film 6 protrudes from the surface of the semiconductor substrate 1 by the thickness of the silicon nitride film, it is oxidized by a cleaning process of the semiconductor substrate 1 and a surface oxidation and oxide film removal process. The surface of the silicon film 6 gradually recedes.

  Through the above steps, an element isolation in which the silicon oxide film 6 is embedded is formed in the element isolation groove 4.

  Next, as shown in FIG. 7, after the surface of the semiconductor substrate 1 is wet-cleaned, the semiconductor substrate 1 is subjected to, for example, thermal oxidation, so that a surface such as a through oxide film (not shown) is formed on the surface of the semiconductor substrate 1. An insulating film is formed. Next, a p-type impurity (for example, boron) is ion-implanted into the semiconductor substrate 1 and then heat treatment is performed to diffuse the impurity, thereby forming a p-type well 8 in the memory cell formation region. A region where the p-type well 8 is exposed on the surface of the semiconductor substrate 1 is an element formation region Ac. Here, also in the peripheral circuit formation region, the element formation region LAc is similarly formed.

  Next, after a thermal oxide film having a thickness of, for example, about 8 nm is formed on the surface of the p-type well 8 by thermal oxidation (pre-oxidation), the thermal oxide film is removed, and the semiconductor substrate 1 (p-type well 8) is removed. Clean surface. Next, heat treatment is performed to form a thermal oxide film having a thickness of about 10.5 nm, for example. This thermal oxide film forms the gate insulating film 9 of the nonvolatile memory cell.

  Next, a conductive film such as a phosphorus-doped polycrystalline silicon film 10 having a thickness of about 100 nm is deposited on the gate insulating film 9 by a CVD method. Next, the polycrystalline silicon film 10 is dry-etched using a resist film (not shown) as a mask, so that a stripe-shaped pattern FG ′ (10) having a longitudinal direction extending in the X direction is formed in the memory cell formation region. To form

  Next, as shown in FIG. 8, an insulating film such as an ONO film 21 is formed on the semiconductor substrate 1 in order to separate the pattern FG '(10) from a control electrode CG described later. The ONO film 21 is a laminated film of a silicon oxide film, a silicon nitride film, and a silicon oxide film. For example, a silicon oxide film having a thickness of about 5 nm, a silicon nitride film having a thickness of about 7 nm, and a film thickness of about 4 nm are formed by a CVD method. Is formed by sequentially depositing silicon oxide films. Note that a silicon nitride film of about 10 nm may be further deposited on the uppermost silicon oxide film.

  Here, in the peripheral circuit formation region, the ONO film 21, the polycrystalline silicon film 10, and the gate insulating film 9 on the peripheral circuit formation region are removed. Next, after the surface of the semiconductor substrate 1 in the peripheral circuit formation region is wet-cleaned, a gate insulating film 9b having a thickness of about 8 nm is formed on the surface of the p-type well 8 in the peripheral circuit formation region by, for example, thermal oxidation. This gate insulating film 9b becomes the gate insulating film 9b of the MISFET S for selection formed in the peripheral circuit formation region (see FIG. 2).

Next, a polycrystalline silicon film 22 doped with, for example, about 4.75 × 10 ²⁰ / cm ^{3 of} phosphorus is deposited as a conductive film on the semiconductor substrate 1 to a thickness of about 200 nm by a CVD method. Subsequently, an insulating film such as a silicon nitride film 24 having a thickness of, for example, about 300 nm is deposited thereon by a CVD method. This polycrystalline silicon film 22 becomes a gate electrode G of the selection MISFET S formed in the peripheral circuit formation region, and also becomes a control electrode CG of a nonvolatile memory cell formed in the memory cell formation region.

  Next, as shown in FIG. 9, a silicon nitride film 24, a polycrystalline silicon film 22, an ONO film 21 and a pattern FG ′ (polycrystalline silicon film 10) are formed using a resist film (not shown) in the memory cell formation region as a mask. ) Is dry-etched.

  By this dry etching, a control electrode CG (22) made of polycrystalline silicon 22 and a floating electrode FG (10) made of polycrystalline silicon film 10 are formed. The floating electrode FG (10) is divided for each memory cell arranged in the X direction, and the control electrode CG is formed so as to extend in the Y direction, and forms a word line WL. Note that the control electrode CG is not limited to the polycrystalline silicon film 22, but is composed of a single layer film or a laminated film of a high melting point metal or a silicide film, or a laminated film of a polycrystalline silicon film and a high melting point metal film or a silicide film. May be. FIG. 9 corresponds to the EE section of FIG. 8 and also corresponds to the DD section of FIG.

  Here, in the peripheral circuit formation region, the silicon nitride film 24 and the polycrystalline silicon film 22 are dry-etched using a resist film (not shown) as a mask to form the gate electrode G for the selection MISFET S. (See FIG. 2).

Next, an n-type impurity (for example, arsenic) is ion-implanted into the p-type well 8 in the memory cell formation region, and a heat treatment is performed to diffuse the impurity, thereby forming the n ⁺ -type semiconductor region 17 (source and drain regions). ) Is formed. At this time, a channel implantation region (not shown) may be formed below the gate insulating film 9 by oblique ion implantation of a p-type impurity (for example, boron).

Here, in the peripheral circuit formation region, an n-type impurity (for example, arsenic) is ion-implanted into the p-type well 8 and then heat treatment is performed to diffuse the impurity, so that the n ^- type is formed on both sides of the gate electrode G. A semiconductor region (not shown) is formed.

  Next, a light oxide film (thermal oxide film) 26 is formed on the side walls of the polycrystalline silicon films 10 and 22 by performing a heat treatment (light oxidation) at 850 ° C., for example. This light oxide film 26 is formed under the same conditions as those for forming a silicon oxide film having a thickness of about 10 nm on the surface of a silicon substrate. In addition, this film is used to recover damage caused at the end of the gate insulating film 9 during the etching of the floating electrode FG (polycrystalline silicon film 10) and the control electrode (polycrystalline silicon film 22). Form.

  Next, an insulating film such as the silicon nitride film 28 is deposited on the semiconductor substrate 1 by, for example, a CVD method.

Here, in the peripheral circuit formation region, a side wall spacer (not shown) is formed on the side wall of the gate electrode G in the peripheral circuit formation region by anisotropically etching the silicon nitride film 28. Next, an n-type impurity (phosphorus P or arsenic As) is ion-implanted into the p-type well 8 in the peripheral circuit formation region, and then a heat treatment is performed at 950 ° C. for 10 seconds to diffuse the impurity, thereby selecting the MISFET for selection. An n ⁺ type semiconductor region 27 (source, drain region) for S is formed.

  By the above steps, a NOR type nonvolatile memory cell having the control electrode CG (polycrystalline silicon film 22), the ONO film 21, the floating electrode FG (polycrystalline silicon film 10), and the gate insulating film 9 is formed in the memory cell formation region. The MISFET S for selection is formed in the peripheral circuit formation region.

Next, as shown in FIG. 10, an insulating film such as a silicon oxide film 30 having a thickness of about 200 nm is formed on the silicon nitride film 28 by, for example, a CVD method, and then the plug DC shown in FIG. (P1) and dry etching of the silicon oxide film 30 by dry etching using a resist film (not shown) as a mask, followed by dry etching of the silicon nitride film 28 to form a pattern of the plug SC (P1). Thereby, a contact hole C1 and a wiring trench HM1 are formed above the n ⁺ type semiconductor region 17 (source and drain regions). That is, the contact hole C1 is formed on the drain region (17), and the wiring groove HM1 is formed on the source region (17).

  The etching of the silicon oxide film 30 is performed under such conditions that the etching rate of silicon oxide with respect to silicon nitride is increased, so that the silicon nitride film 28 is not completely removed.

  The etching of the silicon nitride film 28 is performed under such conditions that the etching rate of silicon nitride with respect to silicon or silicon oxide is increased, so that the substrate 1 and the silicon oxide film are not etched deeply. Further, this etching is performed under such a condition that the silicon nitride film 28 is anisotropically etched so that the silicon nitride film 28 is left on the side walls of the control electrode CG and the floating electrode FG. Thereby, the contact hole C1 having a diameter smaller than the minimum dimension determined by the resolution limit of the photolithography and the wiring groove HM1 having a fine width are formed by self-alignment (self-alignment) with the control electrode CG and the floating electrode FG. Is done.

Next, an n ⁺ -type impurity (for example, arsenic) is ion-implanted through the inside of the contact hole C1 and the wiring groove HM1, and then heat treatment is performed to diffuse the impurity, thereby forming an n ⁺ -type semiconductor region 19. This n ⁺ type semiconductor region 19 is formed to reduce the contact resistance with the plug formed in contact hole C1.

  Next, as shown in FIG. 11, an insulating film such as a thin silicon nitride film 32 is formed on the silicon oxide film 30 including the inside of the contact hole C1 and the wiring groove HM1. Next, the silicon nitride film 32 on the silicon oxide film 30, the contact hole C1, and the bottom of the wiring groove HM1 is removed by etching back. The silicon nitride film 32 is formed in order to prevent the silicon oxide film 30 on the control electrode CG from being etched when the semiconductor substrate 1 to be described later is cleaned, thereby preventing a short circuit between plugs and the like.

  Next, after cleaning the semiconductor substrate 1 using, for example, a hydrofluoric acid-based cleaning solution, a conductive film is deposited on the silicon oxide film 30 including the inside of the contact hole C1 and the wiring groove HM1. For example, Ti (titanium) of about 10 nm and TiN (titanium nitride) of about 80 nm are sequentially deposited by a sputtering method (not shown), and a W (tungsten) film of about 350 nm is deposited by a CVD method.

  Next, the plug P1 is formed by removing the conductive film formed of the W film, the TiN film, and the Ti film outside the contact hole C1 and the wiring groove HM1 by the CMP method. That is, the plug DC (P1) is formed in the contact hole C1 on the drain region (17), and the plug SC (P1) is formed in the wiring groove HM1 on the source region (17). As described above, the plug SC (P1) is a wiring extending in the Y direction, and forms the source line SL.

  Next, an insulating film such as a silicon oxide film 35 having a thickness of about 300 nm is deposited on the silicon oxide film 30 including the plug P1 by, for example, a CVD method.

  Next, the contact hole C2 is formed by removing the silicon oxide film 35 on the plug P1. In FIG. 12, only the contact hole C2 on the plug DC (P1) on the drain region is shown, and the contact hole C2 on the plug SC (P1) on the source region is different in cross section from FIG. Appears in

  Next, a conductive film is deposited on the silicon oxide film 35 including the inside of the contact hole C2. For example, a W film (not shown) of about 100 nm is deposited by sputtering, and a W film 40 of about 250 nm is deposited by CVD.

  Next, the first layer wiring M1 and a connection portion (plug P2) between the first layer wiring M1 and the plug P1 are formed by dry-etching a conductive film made of the W film 40 or the like using a resist film (not shown) as a mask. . That is, the plug DC (P2) and the plug SC (P2) are formed. The first layer wiring M1 in the figure becomes the sub-bit line SBL in FIG. 1, and the first layer wiring M1 on the plug SC (P2) which does not appear in the cross section shown in FIG. 12 becomes the common source line CSL.

  Thereafter, an insulating film such as a silicon oxide film is deposited on the silicon oxide film 35 including the first layer wiring M1 by, for example, a CVD method, and a conductive film such as a W film is further formed thereon. The second layer wiring is formed by the deposition, but these are not shown.

  In the method of manufacturing a semiconductor integrated circuit device described in detail above, for example, 1) heat treatment for densification of the silicon oxide film 6, 2) heat treatment for forming a through oxide film, and 3) semiconductor substrate 1 ( Various heat treatments such as oxidation for cleaning the surface of the p-type well 8) (pre-oxidation), 4) heat treatment for forming the gate insulating film 9, and 5) heat treatment for forming the light oxide film 26. Process.

  In such a heat treatment step, the silicon oxide film 6 buried inside the groove formed in the semiconductor substrate, particularly, a thin thermal oxide film (oxidized film) formed to recover from the dry etching damage generated on the inner wall of the groove. The oxidation of the silicon film 5) progresses, and the stress applied to the element formation region increases.

Further, stress is also applied to the element formation region by ion implantation when forming the n ⁺ type semiconductor region 17 (source and drain regions) and the n ⁺ type semiconductor region 19.

  Further, since the silicon nitride film is a film having a large film stress, for example, even when the silicon nitride film 28 used for forming the contact hole C1 and the wiring groove HM1 in a self-aligning manner, the element formation region has a stress. Joins.

  However, according to the present embodiment, as described above, since the end of the element formation region Ac is elongated, even if the stress is applied, the defect does not extend to the region where the memory cell is formed. Can be obtained.

(Embodiment 2)
FIG. 13 is a plan view of a main part of the semiconductor integrated circuit device according to the present embodiment. The right part of FIG. 13 shows the memory cell formation area MCFR, and the left part shows the peripheral circuit formation area PCFR. NOR type nonvolatile memory cells are arranged in an array in the memory cell formation region, and a selection MISFET S as an example of a peripheral circuit is formed in the peripheral circuit formation region. As is apparent from comparison with FIG. 1, the semiconductor integrated circuit device according to the present embodiment has the same configuration as that of the first embodiment except that the end of the element forming portion Ac1 is connected to the connection portion Ac2. Therefore, detailed description will be omitted, and only characteristic portions will be described.

  That is, as shown in FIG. 13, in the memory cell forming region, element forming portions Ac1 extending in the X direction are arranged at regular intervals in the Y direction, and the ends of the element forming portions Ac1 are , Are connected by a connection portion Ac2 extending in the Y direction.

  As described above, in the present embodiment, since the ends of the element formation portion Ac1 are connected by the connection portion Ac2, the direction in which the stress is applied can be changed as shown in FIG. Therefore, in addition to the effects of the first embodiment, it is possible to further reduce the concentration of stress on the element formation portion Ac1. As a result, the defect De1 does not extend to the region where the substantial memory cell is formed (memory cell array MCFR), and the leak current of the memory cell can be reduced.

  In FIG. 13, all of the element formation portions Ac1 are connected by the connection portions Ac2. However, as shown in FIG. 15, for every several element formation portions Ac1 (in FIG. 15, two element formation portions Ac1 are connected). (For each Ac1), a connection portion Ac2 may be provided.

(Embodiment 3)
FIG. 16 is a plan view of a main part of the semiconductor integrated circuit device according to the present embodiment. The right part of FIG. 16 shows the memory cell formation area MCFR, and the left part shows the peripheral circuit formation area PCFR. NOR type nonvolatile memory cells are arranged in an array in the memory cell formation region, and a selection MISFET S as an example of a peripheral circuit is formed in the peripheral circuit formation region. As is apparent from comparison with FIG. 1, the semiconductor integrated circuit device according to the present embodiment has the outermost element formation area AcW of the plurality of element formation areas Ac and AcW arranged in the memory cell formation area. Except that the width is wider than the width of the other element formation region Ac, the configuration is the same as that of the first embodiment. Therefore, detailed description will be omitted, and only characteristic portions will be described.

  That is, as shown in FIG. 16, in the memory cell formation region, element formation regions Ac and AcW extending in the X direction are arranged at regular intervals in the Y direction. Among them, the width in the Y direction of the element formation region AcW located at the end in the Y direction is wider than that of the other element formation regions Ac.

  As described above, in the present embodiment, the width of the outermost element formation region AcW is formed wider than the other element formation regions Ac, so that the influence of stress can be reduced as shown in FIG. The occurrence rate of defects (De2) in the outermost element formation region AcW can be reduced. As a result, the leak current of the memory cell can be reduced.

  Further, as described in the first embodiment, if the ends of the element formation regions Ac and AcW are extended, it is possible to prevent the defect (De1) from extending to the region where the memory cell is formed. The effect described in the first embodiment can be obtained.

(Embodiment 4)
FIG. 18 is a plan view of a main part of the semiconductor integrated circuit device according to the present embodiment. The right part of FIG. 18 shows the memory cell formation area MCFR, and the left part shows the peripheral circuit formation area PCFR. NOR type nonvolatile memory cells are arranged in an array in the memory cell formation region, and a selection MISFET S as an example of a peripheral circuit is formed in the peripheral circuit formation region. FIG. 19 is a schematic view of the AA cross section of FIG. 18, and FIG. 20 is a schematic view of the BB cross section of FIG.

  In the semiconductor integrated circuit device of the present embodiment, as apparent from comparison with FIG. 13, an element formation area DAc is provided in the memory cell formation area at the outermost part of the plurality of element formation parts Ac1 arranged. Except for this point, the configuration is the same as that of the second embodiment. Therefore, detailed description is omitted, and only characteristic portions will be described.

  That is, as shown in FIG. 18, in the memory cell forming region, element forming portions Ac1 extending in the X direction are arranged at regular intervals in the Y direction. The element formation region DAc is arranged further outside the element formation portion Ac1 located at the position.

  No memory cell functioning as a memory cell is formed on element formation region DAc. That is, the control electrode CG extends in the Y direction over the element formation region DAc, but the plug DC and the plug SC are not formed at both ends of the control electrode CG.

  At the end of the control electrode CG in the Y direction, lead-out portions (connection portions between the control electrode CG and the upper layer wiring) CA of the control electrode CG are alternately formed. The control electrode CG in which the area (CA) is not formed in FIG. 18 has the lead-out portion at the other end not shown in FIG.

  As described above, in the present embodiment, since the element formation region DAc is provided at the outermost of the plurality of element formation portions Ac1, stress can be concentrated in this region, and the region where the molycell is formed, that is, The defect (De2) does not extend to the element formation portion Ac1 shown in FIG. 21, and the leakage current of the memory cell can be reduced.

  Further, since the element formation region DAc is formed by utilizing the area under the lead portion CA, a defect countermeasure can be taken without enlarging the memory cell formation region.

  Further, as described in the second embodiment, by connecting the ends of these element forming portions (Ac1, DAc) by the connection portion Ac2, the effect described in the second embodiment (reduction of the influence of the defect De1) can be obtained. ) Can be obtained.

  FIG. 22 shows a circuit diagram corresponding to the semiconductor integrated circuit device of the present embodiment. As shown, the memory cells MC are arranged in an array. However, a memory cell on DAc (element formation region) does not operate as a memory cell. On the DSG (dummy conductive film), the pseudo memory cell described in the first embodiment is formed. Note that MBL represents a main bit line. S represents the selection MISFET described above. In addition, these memory cells use a certain block as one unit, and for example, data can be collectively erased for each block. One well can be one block. The circuit diagrams corresponding to the semiconductor integrated circuit devices described in the first to third embodiments are the same except that there is no memory cell on DAc (element formation region) in FIG.

  As described above, the first to fourth embodiments have been specifically described. However, the present invention is not limited to such an embodiment. For example, the ends of the element formation regions Ac and AcW of the third embodiment may be implemented. As in Embodiment 2, the connection may be made by the connection part Ac2. Further, the ends of the element formation regions Ac1 and DAc of the fourth embodiment may not be connected by the connection part Ac2, and the ends of these element formation regions may be simply extended as in the first embodiment. As described above, the configurations described in these embodiments may be appropriately combined.

(Embodiment 5)
The semiconductor integrated circuit devices described in the first to fourth embodiments can be used for a computer system described below.

  FIG. 23 shows a computer system in which the semiconductor integrated circuit device (non-volatile memory) described in the first to fourth embodiments is incorporated. This system is composed of a host CPU (Central Processing) mutually connected via a system bus SB. Unit 231, an input / output device 232, a RAM (Random Access Memory) 233, and a memory card 234.

  The memory card 234 includes, for example, a nonvolatile memory (EEPROM chip 1 to chip 4) having a large capacity of several tens of gigabytes as a replacement application of a hard disk storage device, and has the advantages of the nonvolatile memory described in the first to fourth embodiments. In addition, the memory device has advantages such as reduction of defects in the device, reduction of leak current, and improvement of the yield and reliability of the device, and therefore has sufficient industrial advantages as a storage device as a final product.

  Note that the present invention is not limited to the memory card 234 having a relatively small thickness. Even when the memory card 234 has a relatively large thickness, the interface with the host bus system and the command of the host system are analyzed to obtain the nonvolatile memory card. It is needless to say that the present invention can be applied to any nonvolatile storage device including an intelligent controller capable of controlling a nonvolatile memory.

  Data stored for a long period of time is stored in this nonvolatile storage device, while data that is processed and frequently changed by the host CPU 231 is stored in the volatile memory RAM 233.

  The card 234 has a system bus interface SBI connected to the system bus SB, and enables a standard bus interface such as an ATA system bus. The controller CR connected to the system bus interface SBI receives commands and data from the host CPU 231 and the host system of the input / output device 232 connected to the system bus SB.

  When the command is a read command, the controller CR accesses necessary one or more of the plurality of chips 1 to 4 (CH1 to 4) having the non-volatile memory described in the first to fourth embodiments to host read data. Transfer to system.

  If the command is a write command, the controller CR accesses one or more of the required chips 1 to 4 (CH1 to CH4) and stores write data from the host system therein. This storage operation includes a program operation and a verify operation for a necessary block, sector, or memory cell of the nonvolatile memory.

  If the command is an erase command, the controller accesses one or more of the required chips 1 to 4 (CHs 1 to 4) and erases data stored therein. The erasing operation includes an erasing operation for a necessary block, sector or memory cell of the nonvolatile memory and a verifying operation.

  The non-volatile memory according to the embodiment of the present invention includes not only a technique of providing a memory cell with a binary threshold voltage to store one bit of digital data in one memory cell, but also a technique of storing a large amount of digital data in one memory cell. It is needless to say that the present invention can be applied to a technology in which a memory cell has a four-valued or more multi-valued threshold voltage for storing bits.

  As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say.

  In particular, in this embodiment, a NOR type nonvolatile memory has been described as an example. However, the present invention can be widely applied to a semiconductor integrated circuit device having an elongated element formation region, such as a nonvolatile memory such as an AND type or a NAND type. is there.

  INDUSTRIAL APPLICATION This invention can be utilized widely for the manufacturing industry which manufactures a semiconductor integrated circuit device.

FIG. 2 is a plan view of a principal part of a substrate showing the semiconductor integrated circuit device according to the first embodiment of the present invention; FIG. 2 is a cross-sectional view of a principal part of the substrate, illustrating the semiconductor integrated circuit device according to the first embodiment of the present invention; FIG. 2 is a cross-sectional view of a principal part of the substrate, illustrating the semiconductor integrated circuit device according to the first embodiment of the present invention; FIG. 2 is a plan view of a principal part of the substrate showing the semiconductor integrated circuit device for describing the effect of the first embodiment of the present invention. FIG. 2 is a plan view of a principal part of a substrate showing the semiconductor integrated circuit device according to the first embodiment of the present invention; FIG. 5 is a cross-sectional view of a principal part of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention. FIG. 5 is a cross-sectional view of a principal part of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention. FIG. 5 is a cross-sectional view of a principal part of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention. FIG. 5 is a cross-sectional view of a principal part of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention. FIG. 5 is a cross-sectional view of a principal part of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention. FIG. 5 is a cross-sectional view of a principal part of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention. FIG. 5 is a cross-sectional view of a principal part of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention. FIG. 9 is a plan view of a principal part of a substrate showing a semiconductor integrated circuit device according to a second embodiment of the present invention; FIG. 9 is a plan view of a principal part of a substrate showing a semiconductor integrated circuit device according to a second embodiment of the present invention; FIG. 9 is a plan view of a principal part of a substrate showing a semiconductor integrated circuit device according to a second embodiment of the present invention; FIG. 13 is a plan view of a principal part of a substrate showing a semiconductor integrated circuit device according to a third embodiment of the present invention; FIG. 13 is a plan view of a principal part of a substrate showing a semiconductor integrated circuit device according to a third embodiment of the present invention; FIG. 15 is a plan view of a principal part of a substrate showing a semiconductor integrated circuit device according to a fourth embodiment of the present invention; FIG. 14 is a cross-sectional view of a principal part of a substrate showing a semiconductor integrated circuit device according to a fourth embodiment of the present invention; FIG. 14 is a cross-sectional view of a principal part of a substrate showing a semiconductor integrated circuit device according to a fourth embodiment of the present invention; FIG. 15 is a plan view of a principal part of a substrate showing a semiconductor integrated circuit device according to a fourth embodiment of the present invention; FIG. 14 is a circuit diagram corresponding to a semiconductor integrated circuit device according to a fourth embodiment of the present invention. 1 is a diagram illustrating a computer system using a semiconductor integrated circuit device of the present invention.

Explanation of reference numerals

Reference Signs List 1 semiconductor substrate 4 element isolation groove 5 silicon oxide film (thermal oxide film)
6. Silicon oxide film (insulating film)
Reference Signs List 8 p well 9 gate insulating film 9b gate insulating film 10 polycrystalline silicon film 17 n ⁺ type semiconductor region 19 n ⁺ type semiconductor region 21 ONO film (insulating film)
Reference Signs List 22 polycrystalline silicon film 24 silicon nitride film 26 light oxide film 27 n ⁺ type semiconductor region 28 silicon nitride film 30 silicon oxide film 32 silicon nitride film 35 silicon oxide film 40 W film Ac element formation area Ac1 element formation part Ac2 connection part AcW Element forming area DAc Element forming area LAc Element forming area C1 Contact hole C2 Contact hole CA Leader SC plug DC plug P1 plug P2 plug CG Control electrode FG Floating electrode FG 'Pattern G Gate electrode DSG Dummy conductive film De1, De2 Defect MBI Main bit line SBL Sub bit line SL Source line WL Word line M1 First layer wiring D, d1, d2 Distance MC Memory cell S MISFET for selection
232 I / O device 233 RAM
234 memory card SB system bus SBI system bus interface CR controller CH1 to CH4 chip MCFR memory cell formation area PCFR peripheral circuit formation area MCAR memory cell array

Claims (20)

(A) An element formation region formed on a surface of a semiconductor substrate and partitioned by an insulating film, and having two or more element formation portions extending in a first direction in a second direction perpendicular to the first direction. An element formation region connecting end portions of the two or more element formation portions and having a connection portion extending in the second direction;
(B) a plurality of memory cells formed on a main surface of the element formation region;
A semiconductor integrated circuit device comprising: The semiconductor integrated circuit device according to claim 1,
The semiconductor integrated circuit device further includes:
(C) having a conductive film formed so as to surround the plurality of memory cells,
The semiconductor integrated circuit device, wherein the connection part is formed below the conductive film. (A) An element formation region formed on the surface of a semiconductor substrate and having three or more element formation regions partitioned by an insulating film and extending in a first direction in a second direction perpendicular to the first direction. ,
(B) a plurality of memory cells formed on the main surface of the three or more element formation regions;
A semiconductor integrated circuit device having
The semiconductor integrated circuit device according to claim 3, wherein a width in the second direction of an outermost element formation region among the three or more element formation regions is larger than a width of another element formation region. The semiconductor integrated circuit device according to claim 3,
The semiconductor integrated circuit device further includes:
(C) having a conductive film formed so as to surround the plurality of memory cells,
The semiconductor integrated circuit device, wherein the element formation region extends to below the conductive film extending in the second direction. The semiconductor integrated circuit device according to claim 1,
The semiconductor integrated circuit device has three or more element forming portions in a second direction perpendicular to the first direction,
The semiconductor integrated circuit device according to claim 3, wherein a width in the second direction of an outermost element formation region among the three or more element formation sections is wider than a width of another element formation section. The semiconductor integrated circuit device according to claim 5,
The semiconductor integrated circuit device further includes:
(C) having a conductive film formed so as to surround the plurality of memory cells,
The semiconductor integrated circuit device, wherein the connection part is formed below the conductive film. (A) An element formation region formed on the surface of a semiconductor substrate and having three or more element formation regions partitioned by an insulating film and extending in a first direction in a second direction perpendicular to the first direction. ,
(B) a plurality of memory cells formed on the main surface of the element formation region other than the outermost element formation region among the three or more element formation regions;
A semiconductor integrated circuit device, wherein a memory cell functioning as a memory cell is not formed on the outermost element formation region. (A) An element formation region formed on the surface of a semiconductor substrate and having three or more element formation regions partitioned by an insulating film and extending in a first direction in a second direction perpendicular to the first direction. ,
(B) a memory cell formed on the element formation region,
(B ₁ ) a first electrode made of a first conductive film formed via a first insulating film;
(B ₂ ) a _second electrode made of a second conductive film formed on the first electrode with a second insulating film interposed therebetween, the second electrode extending in the second direction;
(B ₃ ) a semiconductor region formed in the element formation region on both sides of the second electrode;
Having a plurality of memory cells including
A semiconductor integrated circuit device, wherein a memory cell on an outermost element formation region among the three or more element formation regions does not function as a memory cell. 9. The semiconductor integrated circuit device according to claim 8,
The semiconductor integrated circuit device further includes:
(C) a wiring formed above the memory cell;
(D) a conductive portion formed on a semiconductor region of the memory cell for electrically connecting the wiring and the memory cell;
Has,
The semiconductor integrated circuit device, wherein the conductive portion is not formed on the outermost element formation region. 9. The semiconductor integrated circuit device according to claim 8,
2. The semiconductor integrated circuit device according to claim 1, wherein the second electrodes of the plurality of memory cells do not extend beyond the outermost element formation region. 9. The semiconductor integrated circuit device according to claim 8,
2. The semiconductor integrated circuit device according to claim 1, wherein the second electrodes of the plurality of memory cells extend alternately beyond the outermost element formation region and alternately do not. The semiconductor integrated circuit device according to claim 11,
A semiconductor integrated circuit device, wherein a lead portion of an adjacent second electrode is arranged at an end of the second electrode that does not extend beyond the outermost element formation region. 9. The semiconductor integrated circuit device according to claim 7, wherein
The semiconductor integrated circuit device further includes:
(C) having a conductive film formed so as to surround the plurality of memory cells,
The semiconductor integrated circuit device, wherein the element formation region extends to below the conductive film extending in the second direction. (A) An element forming region formed on a surface of a semiconductor substrate and partitioned by an insulating film, and having three or more element forming portions extending in a first direction in a second direction perpendicular to the first direction. An element formation region connecting end portions of the three or more element formation portions and having a connection portion extending in the second direction;
(B) a memory cell formed on the element formation region,
(B ₁ ) a first electrode made of a first conductive film formed via a first insulating film;
(B ₂ ) a _second electrode made of a second conductive film formed on the first electrode with a second insulating film interposed therebetween, the second electrode extending in the second direction;
(B ₃ ) a semiconductor region formed in the element formation region on both sides of the second electrode;
Having a plurality of memory cells including
A semiconductor integrated circuit device, wherein a memory cell of an outermost element formation portion among the three or more element formation portions does not function as a memory cell. The semiconductor integrated circuit device according to claim 14,
The semiconductor integrated circuit device further includes:
(C) a wiring formed above the memory cell;
(D) a conductive portion formed on a semiconductor region of the memory cell for electrically connecting the wiring and the memory cell;
Has,
The semiconductor integrated circuit device, wherein the conductive portion is not formed on the outermost element forming portion. The semiconductor integrated circuit device according to claim 14,
The second electrodes of the plurality of memory cells are alternately arranged so as to extend beyond the outermost element formation portion and to not extend.
A semiconductor integrated circuit device, wherein a lead-out portion of an adjacent second electrode is arranged at an end of the second electrode that does not extend beyond the outermost element formation portion. The semiconductor integrated circuit device according to claim 14,
The semiconductor integrated circuit device further includes:
(C) having a conductive film formed so as to surround the plurality of memory cells,
The semiconductor integrated circuit device, wherein the connection part is formed below the conductive film. The semiconductor integrated circuit device according to any one of claims 2, 4, 6, 13, and 17,
The semiconductor integrated circuit device, wherein the conductive film is in a floating state. The semiconductor integrated circuit device according to claim 1,
The semiconductor integrated circuit device,
Around the element formation area where the memory cell is formed, another element formation area where a peripheral circuit is formed,
The semiconductor integrated circuit device, wherein the insulating film exists between the element formation region and another element formation region. A method for manufacturing a semiconductor integrated circuit device, comprising:
Forming an insulating film on the semiconductor substrate on which the semiconductor element is formed,
Forming a connection hole and a wiring groove in the insulating film;
Forming a pre-cleaning protective film on the side walls of the connection holes and the wiring grooves;
After performing pre-cleaning on the semiconductor substrate, burying a conductive film in the connection hole and the wiring groove;
A method for manufacturing a semiconductor integrated circuit device, comprising:

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