JPH1022480A - Nonvolatile semiconductor storage device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a flash memory allowing the compatibility of a reduction crystalline defects in an element isolation region with high reliability of a tunnel insulating film. SOLUTION: A flash memory is composed of floating gate 101, a word line 102, a word line 102 connected to a control gate, a source line 103 connected a source in an Si substrate a data line 104 connected to a drain and a transistor 108 selecting the above source line and the data line. At the time of forming an element isolation oxide film 105 between memory cells, after processing a polycrystalline Si film to be the floating gate so as to completely cover an element isolation region 109 between selection transistor with a pattern 106, a nitriding film is formed on the side wall and oxidation is performed using the nitride film as a mask and the element isolation oxide film 105 is formed by self-alignment with a gate pattern 106. Thereby, connection leakage is reduced so as to improve an yield. Further, due to a low temperature process, a trap during tunnel oxidation caused by heat stress is reduced so as to improve the number of rewriting.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device and a method of manufacturing the same, and more particularly, to a method for reducing a crystal defect generated between an element isolation region between memory cells and an element isolation region between select transistors to improve reliability. And a method of manufacturing the same.

[0002]

2. Description of the Related Art A flash memory, which is a typical non-volatile semiconductor memory device, has excellent portability and shock resistance, and can be electrically erased on-board at one time. Are gathering. A flash memory generally has a silicon (Si) substrate having source and drain diffusion layers, a floating gate and a control gate mainly formed of polycrystalline Si formed on the Si substrate, and an interlayer insulating layer separating the two gates. Film and a tunnel insulating film separating the floating gate and the Si substrate.
A memory cell having an S-type field effect transistor as one storage unit; a plurality of memory cells arranged in a matrix to connect between control gates; a source line connecting between source diffusion layers; And data lines connecting the layers. A MOS field effect transistor called a select transistor is connected to each source line and data line, and the select transistor selects a write / erase bit.

The memory cells and the selection transistors are separated from each other by element isolation regions mainly made of silicon dioxide (SiO ₂ ). Each element isolation region between the memory cells and between the selection transistors is a so-called LOCO.
They were simultaneously formed using the S (Local Oxidation on Si) method. At this time, since the element isolation region between the memory cells is positioned using the resist mask with respect to the floating gate, there is a problem that the pitch between the data lines cannot be reduced. As a conventional technique for solving this, an element isolation region between a peripheral circuit and a selection transistor is provided by a LOCO.
After forming by the S method, a nitride film is formed on the side wall of the floating gate, and using this as a mask, a device isolation oxide film between memory cells is formed in a self-aligned manner with respect to the gate to reduce the pitch between data lines. Have been reported. Related to this prior art is, for example, International Electron Devices Meeting Technical Digest, 1994, pp. 921-923 (International Electron Devices Meeting Technica).
l Digest, 1994 pp921-923).

[0004]

However, in the above-mentioned prior art in which the element isolation region between memory cells is formed in a self-aligned manner, the portion where the element isolation region between the select transistors and the element isolation region between the memory cells are connected. In such a case, a crystal defect is likely to occur, and as a result, a junction leak occurs in a neighboring bit, and the yield of the flash memory is reduced. This is because re-oxidation of the select transistor element isolation region in which the stress remained remained caused a larger stress at the connection portion of the element isolation region. In order to alleviate this stress and reduce crystal defects, it is effective to increase the forming temperature of the element isolation region between memory cells. However, the high temperature of the process of forming the element isolation region between the memory cells causes a decrease in the reliability of the tunnel insulating film,
In particular, there is a problem that the rewriting durability is deteriorated.

It is an object of the present invention to provide a nonvolatile semiconductor memory device in which crystal defects in an element isolation region are reduced, and a method of manufacturing the same. It is another object of the present invention to provide a nonvolatile semiconductor memory device capable of improving the reliability of a tunnel insulating film and increasing the number of rewrites, and a method of manufacturing the same. It is still another object of the present invention to provide a nonvolatile semiconductor memory device capable of achieving both a reduction in crystal defects in an element isolation region and an improvement in reliability of a tunnel insulating film, and a method of manufacturing the same.

[0006]

According to the present invention, there is provided a nonvolatile semiconductor memory device comprising: a diffusion layer serving as a source and a drain in a semiconductor substrate; a floating gate on a semiconductor substrate via an insulating film; A memory cell array in which a plurality of memory cells are arranged in a matrix with a MOS type field effect transistor having a control gate interposed therebetween through an insulating film as one memory cell; A word line to be connected, a data line to connect between drain diffusion layers of the memory cell, a source line to connect between source diffusion layers of the memory cell, and a select MOS field effect transistor to select the data line and the source line, respectively. Device isolation region between memory cells and device isolation region between select MOS type field effect transistors With at least a portion of both composed of silicon dioxide formed below the semiconductor substrate surface, selecting an element isolation region between memory cells MO
A portion formed below the surface of the semiconductor substrate in the element isolation region of the S field effect transistor is divided by the semiconductor substrate. That is, by forming a structure in which the element isolation oxide film between the select transistors and the element isolation film between the memory cells are separated, crystal defects in the element isolation region can be reduced.

In the above-mentioned nonvolatile semiconductor memory device, it is preferable that an electrode is formed so as to cover an upper portion where a device isolation region between memory cells and a device isolation region between select MOS type field effect transistors are separated. is there.

In this case, the MO constituting the memory cell is
When the S-type field-effect transistor is an n-channel MOS field-effect transistor, the electrode covering the upper part of the divided portion is grounded or a negative voltage is applied, and the p-channel
In the case of an S-type field effect transistor, it may be configured to apply a ground or a positive voltage. With such a configuration, it is possible to prevent the degradation of the resistance of the parasitic MOS that may occur in the portion where the element isolation region is divided, and to ensure the withstand voltage.

It is preferable that the electrode covering the upper part of the divided portion is made of a polycrystalline silicon film or a metal silicide film, or a laminated film containing at least one of them.

Further, at least one of an element isolation region between the memory cells and an element isolation region between the select MOS type field effect transistors may be a region formed by oxidizing the semiconductor substrate, Alternatively, it may be a region formed by filling at least silicon dioxide in a groove formed in a semiconductor substrate.

Further, according to the present invention, there is provided a method for manufacturing a nonvolatile semiconductor memory device, comprising: an element isolation region formed by selectively oxidizing a semiconductor substrate; a diffusion layer serving as a source and a drain in the semiconductor substrate; A plurality of memory cells are arranged in a matrix with a MOS type field effect transistor in which a floating gate having an insulating film interposed and a control gate having an insulating film interposed above the floating gate are arranged as one memory cell. A memory cell array, a word line connecting between control gates of memory cells, a data line connecting between drain diffusion layers of memory cells, a source line connecting between source diffusion layers of memory cells, In a method for manufacturing a nonvolatile semiconductor memory device having a selection MOS type field effect transistor for selecting a source line,
Depositing a silicon nitride film after forming the floating gate of the memory cell, forming a resist pattern in which a portion forming the memory cell array and separated from the element isolation region formed by the selective oxidation is exposed; The silicon nitride film is removed by anisotropic dry etching using the resist pattern as a mask, and thermal oxidation is performed using the remaining silicon nitride film as a mask to self-align the element isolation region between the memory cells with respect to the floating gate. The method is characterized in that a forming step is provided. By adopting such a manufacturing method, the crystal defect density can be reduced, the yield can be improved, and the temperature of the element isolation oxide film formation process can be reduced, so that the insulating film between the floating gate and the semiconductor substrate, that is, the tunnel oxide film In this case, the number of rewrites increases because the number of traps due to thermal stress in the memory cell also decreases.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of a nonvolatile semiconductor memory device according to the present invention is a method of manufacturing an n-type diffusion layer serving as a source and a drain in a p-type well region formed on an n-type Si substrate. An n-channel MOS field effect transistor in which a floating gate on a substrate with a tunnel oxide film interposed and a control gate with an oxide film over the floating gate is arranged as one memory cell, and a plurality of memory cells are provided. A memory cell array arranged in rows and columns, a word line connecting between control gates of memory cells, a data line connecting between drain diffusion layers of memory cells, and a source line connecting between source diffusion layers of memory cells And an n-channel selection MOS for selecting a data line and a source line, respectively
In a nonvolatile semiconductor memory device, that is, a flash memory having a field effect transistor, at least a part of both an element isolation region between the memory cells and an element isolation region between the select MOS type field effect transistors is S.
It is composed of silicon dioxide formed below the surface of the i-substrate, that is, an oxide film formed by the LOCOS method, and is located between the element isolation region between the memory cells and the Si substrate surface in the element isolation region of the selective MOS field effect transistor. This is a flash memory in which a lower portion is divided by a Si substrate, and an upper portion of the divided portion is covered with an electrode to which a ground or a negative voltage is applied.

As described above, since the element isolation region between the select MOS type field-effect transistors and the element isolation region between the memory cells are separated from each other, a crystal defect generated at a connection portion between the two element isolation regions in the conventional example. In addition, since the upper portion of the divided portion is covered with the electrode to which the ground or the negative voltage is applied, a decrease in the breakdown voltage due to the parasitic MOS can be prevented, and the yield and reliability of the flash memory can be improved.

A preferred embodiment of a method for manufacturing a nonvolatile semiconductor memory device according to the present invention is directed to a device isolation method in which a P-well region is formed on an n-type Si substrate and then the n-type Si substrate is selectively oxidized. An n-channel MOS in which a region, a diffusion layer serving as a source and a drain in a Si substrate, a floating gate on a Si substrate via a tunnel oxide film, and a control gate via an oxide film on the floating gate Type field effect transistor as one memory cell, a memory cell array in which a plurality of the memory cells are arranged in a matrix, and a word line connecting between control gates of the memory cell and a drain diffusion layer of the memory cell are connected. Data line, a source line connecting the source diffusion layers of the memory cells, and an n-channel selection MOS type field effect transistor for selecting the data line and the source line, respectively. The method of manufacturing a nonvolatile semiconductor memory device including a transistor, a silicon nitride film is deposited after forming the floating gates of the memory cells, a portion forming the memory cell array LOCOS
Forming a resist pattern in which a portion separated from the element isolation region formed by selective oxidation by the method is exposed, and using the resist pattern as a mask, the silicon nitride film is removed by anisotropic dry etching by reactive ion etching;
A method of manufacturing a flash memory, comprising a step of forming an element isolation region between memory cells in a self-aligned manner with respect to the floating gate by performing thermal oxidation using a remaining silicon nitride film as a mask. .

By using such a method of manufacturing a flash memory, crystal defects occurring at the connection between the two element isolation regions in the conventional example are reduced, and the temperature of the element isolation oxide film forming step can be reduced. By lowering the temperature of the element isolation oxide film formation step, traps in the tunnel oxide film due to thermal stress are reduced, so that the reliability of the tunnel oxide film is improved and the number of times of rewriting of the flash memory is improved.

[0016]

Next, more specific embodiments of the nonvolatile semiconductor memory device and the method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

<Embodiment 1> FIG. 1 is a layout diagram showing an embodiment of a nonvolatile semiconductor memory device according to the present invention, showing patterns of a memory cell portion and a select transistor portion of a flash memory. is there. Actually, a larger number of memory cells and a larger number of selection transistors are formed, and the required number of bits is realized by repeating this pattern many times. In the present embodiment, when forming the element isolation oxide film between the memory cells, the element isolation oxide film of the select transistor is covered with the floating gate, and the stress caused by the collision of the two element isolation oxide films is relaxed. It is configured to reduce crystal defects.

In FIG. 1, reference numeral 101 denotes a floating gate, and a memory cell includes a floating gate 101, a word line 102 connected to a control gate, a source line 103 connected to a source in a Si substrate, and a drain. And a data line 104 connected thereto. After processing the polycrystalline Si film serving as the floating gate as shown in the pattern 106, a nitride film is formed on the side wall of the polycrystalline Si film, and oxidation is performed using the nitride film as a mask, thereby forming an element isolation oxide film between memory cells. 105 is formed in self-alignment with the floating gate 101. Reference numeral 108 denotes a layout pattern serving as a gate of a selection transistor, and each selection transistor is separated by an element isolation oxide film 109.
The source line 103 and the data line 104 are connected to the diffusion layer 1 respectively.
07, the layout pattern is connected to the selection transistor.

As described above, the present invention is characterized by a layout in which the element isolation region 105 between memory cells and the element isolation region 109 between select transistors are not connected, that is, divided. The reason for this division is that if the layout is such that the element isolation regions 105 and 109 overlap, a large mechanical stress is generated at the portion where the element isolation regions 105 and 109 overlap, and crystal defects are induced in the Si substrate. As a result, the junction leakage increases and the reliability of the tunnel oxide film deteriorates. Note that the element isolation region 10
If 5 and 109 are divided, there is a possibility that the breakdown voltage of the parasitic MOS is deteriorated. Therefore, in this embodiment, the electrode 110 is formed on a portion where the element isolation oxide film is not connected, and when the memory cell is formed in the p-type well region, that is, in the case of an n-type MOS transistor, this electrode 110 is grounded. Or,
Alternatively, when a negative voltage is applied, in the case where the transistor is formed in the n-type well region, that is, in the case of a p-type MOS transistor, a ground voltage or a positive voltage is applied to the electrode 110 to ensure a withstand voltage.

Next, an example of a method of manufacturing the flash memory according to the present embodiment will be described in the order of steps with reference to FIGS. 2 and 3 are cross-sectional views taken along the line AA 'in the layout drawing of FIG.

First, a p-type well region 220 was formed in a Si substrate 201. Subsequently, a thermal oxide film 202 having a thickness of 500 nm was formed by a selective oxidation (LOCOS) method to form a device isolation region for a select transistor and a peripheral circuit (see FIG. 2A).

Next, a tunnel oxide film 203, a polycrystalline Si film 204 serving as a lower floating gate, a CVD oxide film 205,
After sequentially forming the CVD nitride film 206, patterning was performed using the mask pattern 106 of FIG. 1 so as to cover the entire element isolation region 109 of the select transistor, that is, the thermal oxide film 202 (see FIG. 2B). After that, CV
A D nitride film 207 was deposited, and anisotropic dry etching using reactive ion etching was performed to leave the CVD nitride film 207 only on the side wall of the floating gate (see FIG. 2C). Next, wet oxidation was performed to form an oxide film 208 having a thickness of about 300 nm, thereby completing an element isolation region of the memory cell. As a result of cross-sectional observation with a scanning electron microscope, it was confirmed that the element isolation region between memory cells and the element isolation region between select transistors were completely separated (see FIG. 2D).

Subsequently, after removing the CVD nitride films 206 and 207 with a hot phosphoric acid aqueous solution and forming n-type source and drain diffusion layers of the memory cell by ion implantation,
A CVD oxide film 209 is deposited and anisotropically etched to form a CVD oxide film 20 on the side wall of the polycrystalline Si film 204.
9 (see FIG. 3E). Further, the polycrystalline Si film 2
10 was deposited and processed to form an upper floating gate (see FIG. 3F).

Then, after forming a polycrystalline Si interlayer insulating film 211, the polycrystalline Si interlayer insulating film 211 in a portion other than the memory cell, such as a peripheral circuit and a selection transistor, and a polycrystalline Si
The i films 210 and 204 were removed (see FIG. 3G).

Subsequently, the gate of the select transistor and the peripheral circuit portion is oxidized, and a polycrystalline Si / WSi laminated film 212 is deposited.
02, 108, and 110 to process memory word lines, peripheral circuits / selection MOS transistor gate electrodes,
And an electrode for securing the withstand voltage of the parasitic MOS was formed (FIG. 3 (h)).
reference).

Finally, an interlayer insulating film was deposited, and reflow was performed by heat treatment. Thereafter, a contact hole was formed to reach a word line and a diffusion layer, and subsequently, a metal wiring was formed to complete a memory. As the reflowable interlayer insulating film, for example, BPSG, organic SOG, ozone TEOS, or the like may be used.

For comparison, FIG. 4 shows a conventional layout, and FIGS. 5 and 6 show cross-sectional structures along the line AA shown in FIG. 4 in the order of manufacturing steps. The same components as those of the present embodiment shown in FIGS. 1 to 3 are denoted by the same reference numerals for convenience of description, and detailed description thereof will be omitted. That is, the manufacturing method of this embodiment is the same as that of the conventional example.
06 differs from the conventional example in that the floating gate mask pattern 106 covers the entire element isolation region 109, whereas the present embodiment covers only a part of the select transistor element isolation region 109.

For this reason, as shown in FIG. 5D, it has been confirmed that in the conventional structure, two element isolation regions of the element isolation region 202 of the select transistor and the element isolation region 208 between the memory cells collide. Was. Observation by micro-Raman spectroscopy revealed that a greater stress was generated at the collision portion between the two element isolation regions than at the other Si substrate portions. In FIG. 4, reference numeral 112 denotes a pattern of a polycrystalline Si / WSi laminated film, and this pattern 112 is a pattern 108 of the same laminated film.
The electrode formed by the pattern 112 is called a remaining gate electrode, and is an electrode which is set to a ground or open state and is not used for circuit operation. .

FIG. 7 shows a state in which the wiring, oxide film and the like of the memory manufactured according to the present invention and the prior art are removed, and etching is performed using a mixed solution of dichromic acid / hydrofluoric acid with the Si substrate completely exposed. 5 is a result of measuring the oxidation temperature dependency of the crystal defect density near the line AA ′ shown in FIGS. 1 and 4. As can be seen from the characteristic line (I) shown in the figure, in the prior art, the formation temperature of the memory cell element isolation oxide film had to be 1000 ° C. or higher in order to reduce crystal defects.
On the other hand, it is clear from the characteristic line (II) shown in FIG. 3 that the use of the present invention can further reduce crystal defects even at an oxidation temperature of 900 ° C. or lower than the conventional case. In addition, as a result of measuring the write / erase time of the memory cell manufactured in this example, it became clear that the number of usable rewrites was increased four times as compared with the conventional case.

Therefore, according to the present embodiment, crystal defects can be reduced by forming the memory cell device isolation region by completely covering the select transistor device isolation region of the flash memory with the floating gate polycrystalline Si pattern. This has the effect of improving the yield. In addition, it becomes possible to lower the temperature of the element isolation oxide film formation process, and the number of traps in the tunnel oxide film due to thermal stress decreases.
This has the effect of increasing the number of rewrites.

<Embodiment 2> Another embodiment of the nonvolatile semiconductor memory device according to the present invention will be described with reference to FIGS. FIG. 8 is a layout diagram showing a nonvolatile semiconductor memory device according to the present invention, showing a pattern of a part of a memory cell part and a part of a select transistor part of a flash memory as in the first embodiment. 9 and 10 show FIG.
FIG. 3 is a cross-sectional view showing a portion indicated by a line AA ′ in the order of manufacturing steps. This embodiment is different from the first embodiment in that a cover for the select transistor element isolation region is replaced with a polycrystalline Si film and a CVD nitride film is used. 8 to 10, the same components as those shown in the first embodiment are denoted by the same reference numerals.

As shown in FIG. 8, a memory cell includes a floating gate 101 and a word line 102 connecting a control gate.
And a source line 103 connecting a source in the Si substrate;
And a data line 104 connected to the drain.
The method of forming the element isolation oxide film 105 between the memory cells is as follows. First, a polycrystalline Si film serving as a floating gate is processed like a pattern 106. Then, after depositing a nitride film on the entire surface, using the resist mask pattern 111, the nitride film only in the pattern is processed by anisotropic dry etching. In this case, the nitride film exists on the side wall inside the pattern 111 (memory cell) and on the entire surface outside the pattern. Thereafter, by performing thermal oxidation using the remaining nitride film as a mask, an element isolation region 105 is formed between memory cells in a self-aligned manner with respect to a polycrystalline Si film 106 serving as a floating gate. Further, similarly to the first embodiment, the source line 103 and the data line 104 are connected to the selection transistors via the diffusion layers 107, respectively. Note that the gate of the selection transistor is represented by a pattern 108. An element isolation oxide film 10 is provided between each selection transistor.
9. Further, an electrode 110 is formed on a portion where the element isolation oxide film is not connected, and when a memory cell is formed in a p-type well region, the electrode 110 is grounded or a negative voltage is applied to form an n-type well. When formed in a region, the withstand voltage of the parasitic MOS is ensured by grounding or by applying a positive voltage.

Next, the manufacturing method of the flash memory of this embodiment will be described with reference to FIGS.
The description will be given focusing on the cross section indicated by the line A '. First, a p-type well region 220 was formed in the Si substrate 201. Subsequently, a thermal oxide film 202 having a thickness of 500 nm was formed by a selective oxidation (LOCOS) method to form a device isolation region for a select transistor and a peripheral circuit (see FIG. 9A).

Next, a tunnel oxide film 203, a polycrystalline Si film 204 serving as a lower floating gate, a CVD oxide film 205,
After sequentially forming the CVD nitride film 206, patterning was performed using the mask pattern 106 of FIG. 8 (see FIG. 9B).

Thereafter, a CVD nitride film 207 was deposited on the entire surface, and only the inside of the pattern was anisotropically dry-etched using the resist mask pattern 111 of FIG. As a result, the nitride film remains only on the side wall of the floating gate in the memory cell portion and exists on the entire surface in the select transistor portion (see FIG. 9C). Next, wet oxidation is performed,
An oxide film 208 having a thickness of about 300 nm was formed to complete an element isolation region of a memory cell. As a result of cross-sectional observation with a scanning electron microscope, it was confirmed that the element isolation region between memory cells and the selection transistor element isolation region were completely separated (see FIG. 9D).

Subsequently, after removing the CVD nitride films 206 and 207 with a hot phosphoric acid aqueous solution and forming the n-type source and drain diffusion layers of the memory cell by ion implantation,
A CVD oxide film 209 was deposited and subjected to anisotropic dry etching to leave the CVD oxide film 209 on the side wall of the polycrystalline Si 204 (see FIG. 10E). Furthermore, polycrystalline S
An i-film 210 was deposited and processed to form an upper floating gate (see FIG. 10 (f)).

Thereafter, after forming the polycrystalline Si interlayer insulating film 211, the polycrystalline Si interlayer insulating film 211 other than the memory cell, such as a peripheral circuit and a select transistor, and the polycrystalline Si
The i films 210 and 204 were removed (see FIG. 10G). Subsequently, gate oxidation of the select transistor and the peripheral circuit portion is performed, and the polycrystalline Si / WSi laminated film 212 is formed.
Is deposited, and is deposited on the mask pattern 102, shown in FIG.
Processing was performed using 108 and 110 to form a word line of the memory, a gate electrode of the peripheral circuit / selection MOS transistor, and an electrode for securing the withstand voltage of the parasitic MOS (see FIG. 10H).

Finally, an interlayer insulating film was deposited, and reflow was performed by heat treatment. Thereafter, a contact hole was formed to reach a word line and a diffusion layer, and subsequently, a metal wiring was formed to complete a memory.

As in the first embodiment, the memory fabricated by the manufacturing method of the present embodiment has a higher crystal defect density in a portion where the device isolation region between memory cells and the device isolation region between select transistors are close to each other as compared with the conventional example. Was able to be reduced. In addition, the number of rewrites has increased four times as compared with the conventional example.

Therefore, according to the present embodiment, crystal defects can be reduced by forming the inter-memory-cell element isolation region by covering the whole of the inter-selection element isolation region of the flash memory with the nitride film pattern. This has the effect of improving the yield. Further, similarly to the first embodiment, the temperature of the element isolation oxide film forming process can be reduced, and the number of rewrites can be increased because traps in the tunnel oxide film due to thermal stress are reduced.

The preferred embodiment of the present invention has been described above. However, the present invention is not limited to the above-described embodiment, and various design changes can be made without departing from the spirit of the present invention. It is. For example, in each embodiment, only the thermal oxidation method was used as a method for forming the element isolation region.
Similar effects can be obtained even when a groove is formed in the substrate and filled with an oxide film. Further, in each of the embodiments, the element isolation region between the select transistors and the element isolation region between the memory cells are formed separately. However, even when they are formed at once, for example, the element isolation region is bent due to a reason such as bending. It is effective if applied to places where stress is likely to occur. Also,
In each of the embodiments, a laminated film of polycrystalline Si and WSi was used for an electrode formed on an unconnected portion between the element isolation region between select transistors and the element isolation region between memory cells, but other metal silicide was used instead of WSi. The same effect can be obtained by using, or by using any one of these materials.

[0042]

According to the present invention, it is possible to reduce the crystal defects caused by the formation of the element isolation region. As a result, the junction leakage is reduced, and the yield can be improved.
Further, the temperature of the formation process of the element isolation oxide film can be lowered, and the number of traps in the tunnel oxide film due to thermal stress is reduced, so that the number of rewrites can be improved.

[Brief description of the drawings]

FIG. 1 is a main part layout diagram showing one embodiment of a nonvolatile semiconductor memory device according to the present invention.

FIG. 2 is a cross-sectional view showing a cross-sectional structure of a portion indicated by line AA ′ in FIG. 1 in the order of manufacturing steps.

3 is a cross-sectional view showing a cross-sectional structure after the next step shown in FIG. 2 in the order of manufacturing steps.

FIG. 4 is a layout diagram of a conventional nonvolatile semiconductor memory device.

FIG. 5 is a cross-sectional view showing a cross-sectional structure of a portion indicated by line AA ′ in FIG. 4 in the order of manufacturing steps.

6 is a cross-sectional view showing the cross-sectional structure after the next step shown in FIG. 5 in the order of manufacturing steps.

FIG. 7 is a characteristic diagram showing the dependence of the crystal defect density on the oxidation temperature of the conventional example and the present invention in the portion indicated by the line AA ′ in FIGS. 1 and 4, respectively.

FIG. 8 is a main part layout diagram showing another embodiment of the nonvolatile semiconductor memory device according to the present invention.

9 is a cross-sectional view showing a cross-sectional structure of a portion indicated by line AA ′ in FIG. 8 in the order of manufacturing steps.

10 is a cross-sectional view showing a cross-sectional structure after the next step shown in FIG. 9 in the order of manufacturing steps.

[Explanation of symbols]

101: floating gate, 102: word line, 103: source line, 104: data line, 105: element isolation region between memory cells, 106: floating gate patterning region, 107
... diffusion layer, 108 ... selection transistor gate, 109 ...
Element isolation region between select transistors, 110 ... electrode, 11
DESCRIPTION OF SYMBOLS 1 ... Resist mask pattern, 201 ... Si substrate, 20
2: Element isolation oxide film, 203: Tunnel oxide film, 204
... Polycrystalline Si film, 205 oxide film, 206, 207 nitride film, 208 memory cell element isolation region, 209 oxide film, 210 polycrystalline Si film, 211 polycrystalline Si interlayer insulating film, 212 electrode , 220 ... p-type well.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Takami Sudo 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (72) Inventor Katsutaka Kimura 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo In-house Central Research Laboratory, Hitachi, Ltd.

Claims (10)

[Claims] A MOS having a diffusion layer serving as a source and a drain in a semiconductor substrate, a floating gate on the semiconductor substrate with an insulating film interposed therebetween, and a control gate on the floating gate with an insulating film interposed therebetween. Type field effect transistor as one memory cell, a memory cell array in which a plurality of the memory cells are arranged in a matrix, and a word line connecting between control gates of the memory cell and a drain diffusion layer of the memory cell are connected. A non-volatile semiconductor memory device comprising: a data line to be connected; a source line connecting between source diffusion layers of the memory cells; and a selection MOS field-effect transistor for selecting the data line and the source line, respectively. At least a part of both the element isolation region and the element isolation region between the selective MOS type field effect transistors is located between the surface of the semiconductor substrate. And a portion formed below the semiconductor substrate surface of the element isolation region between the memory cells and the element isolation region of the select MOS field-effect transistor is divided by the semiconductor substrate. A nonvolatile semiconductor memory device characterized in that: 2. The non-volatile memory according to claim 1, wherein an electrode is formed so as to cover an upper portion where a device isolation region between said memory cells and a device isolation region between said select MOS type field effect transistors are separated. Semiconductor storage device. 3. The MOS field-effect transistor constituting the memory cell is an n-channel MOS field-effect transistor, and an electrode covering an upper part of the divided portion is grounded or a negative voltage is applied. 14. The nonvolatile semiconductor memory device according to claim 1. 4. The MOS field-effect transistor constituting the memory cell is a p-channel MOS field-effect transistor, and an electrode covering an upper part of the divided portion is grounded or a positive voltage is applied. 14. The nonvolatile semiconductor memory device according to claim 1. 5. The non-volatile semiconductor memory device according to claim 3, wherein the electrode covering the upper part of the divided portion is made of a polycrystalline silicon film. 6. The nonvolatile semiconductor memory device according to claim 3, wherein the electrode covering the upper part of the divided portion is formed of a metal silicide film. 7. The nonvolatile semiconductor memory device according to claim 3, wherein the electrode covering the upper part of the divided portion is formed of a laminated film including at least one of a polycrystalline silicon film and a metal silicide film. 8. The semiconductor device according to claim 1, wherein at least one of an element isolation region between said memory cells and an element isolation region between said select MOS type field effect transistors is formed by oxidizing said semiconductor substrate. Item 14. The nonvolatile semiconductor memory device according to Item 1. 9. At least one of an element isolation region between the memory cells and an element isolation region between the select MOS type field effect transistors has a trench formed in the semiconductor substrate filled with at least silicon dioxide. The nonvolatile semiconductor memory device according to claim 1, wherein: 10. An element isolation region formed by selectively oxidizing a semiconductor substrate, a diffusion layer serving as a source and a drain in the semiconductor substrate, a floating gate on the semiconductor substrate via an insulating film, and an upper part of the floating gate. And a memory cell array in which a plurality of memory cells are arranged in a matrix, wherein a MOS field effect transistor in which a control gate with an insulating film is disposed is used as one memory cell. A word line to be connected, a data line to connect a drain diffusion layer of a memory cell, a source line to connect a source diffusion layer of a memory cell, and a selection MOS field effect transistor to select the data line and the source line, respectively. A method for manufacturing a nonvolatile semiconductor memory device comprising: forming a silicon nitride film after forming a floating gate of the memory cell; A resist pattern is formed in which a portion forming the memory cell array and a portion separated from the element isolation region formed by the selective oxidation is exposed, and the silicon nitride film is removed by anisotropic dry etching using the resist pattern as a mask. Forming a device isolation region between memory cells in a self-aligned manner with respect to the floating gate by performing thermal oxidation using the remaining silicon nitride film as a mask. Production method.