JP4939224B2 - 半導体基板を作製する方法 - Google Patents

半導体基板を作製する方法 Download PDF

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Publication number
JP4939224B2
JP4939224B2 JP2006541942A JP2006541942A JP4939224B2 JP 4939224 B2 JP4939224 B2 JP 4939224B2 JP 2006541942 A JP2006541942 A JP 2006541942A JP 2006541942 A JP2006541942 A JP 2006541942A JP 4939224 B2 JP4939224 B2 JP 4939224B2
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Japan
Prior art keywords
layer
semiconductor layer
crystalline semiconductor
substrate
temperature
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Expired - Fee Related
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JP2006541942A
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English (en)
Japanese (ja)
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JP2007513511A5 (https=
JP2007513511A (ja
Inventor
ベデル、ステファン
コーエン、ガイ
チェン、フアジー
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International Business Machines Corp
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International Business Machines Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90—Thermal treatments, e.g. annealing or sintering

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  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
JP2006541942A 2003-12-05 2004-12-01 半導体基板を作製する方法 Expired - Fee Related JP4939224B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/728,519 US6972247B2 (en) 2003-12-05 2003-12-05 Method of fabricating strained Si SOI wafers
US10/728,519 2003-12-05
PCT/EP2004/053204 WO2005055290A2 (en) 2003-12-05 2004-12-01 Method of fabricating a strained semiconductor-on-insulator substrate

Publications (3)

Publication Number Publication Date
JP2007513511A JP2007513511A (ja) 2007-05-24
JP2007513511A5 JP2007513511A5 (https=) 2007-11-22
JP4939224B2 true JP4939224B2 (ja) 2012-05-23

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ID=34633733

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JP2006541942A Expired - Fee Related JP4939224B2 (ja) 2003-12-05 2004-12-01 半導体基板を作製する方法

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US (1) US6972247B2 (https=)
EP (1) EP1695377A2 (https=)
JP (1) JP4939224B2 (https=)
KR (1) KR100940748B1 (https=)
CN (1) CN100505163C (https=)
TW (1) TWI313511B (https=)
WO (1) WO2005055290A2 (https=)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005112129A1 (ja) * 2004-05-13 2005-11-24 Fujitsu Limited 半導体装置およびその製造方法、半導体基板の製造方法
US7488670B2 (en) * 2005-07-13 2009-02-10 Infineon Technologies Ag Direct channel stress
FR2890489B1 (fr) * 2005-09-08 2008-03-07 Soitec Silicon On Insulator Procede de fabrication d'une heterostructure de type semi-conducteur sur isolant
US8319285B2 (en) * 2005-12-22 2012-11-27 Infineon Technologies Ag Silicon-on-insulator chip having multiple crystal orientations
US7560318B2 (en) * 2006-03-13 2009-07-14 Freescale Semiconductor, Inc. Process for forming an electronic device including semiconductor layers having different stresses
CN100431132C (zh) * 2006-03-30 2008-11-05 上海理工大学 一种采用相变方法实现绝缘体上应变硅的制作方法
DE102006030257B4 (de) * 2006-06-30 2010-04-08 Advanced Micro Devices, Inc., Sunnyvale Teststruktur zum Bestimmen der Eigenschaften von Halbleiterlegierungen in SOI-Transistoren mittels Röntgenbeugung
JP4943820B2 (ja) * 2006-11-10 2012-05-30 信越化学工業株式会社 ＧＯＩ（ＧｅｏｎＩｎｓｕｌａｔｏｒ）基板の製造方法
US8227020B1 (en) * 2007-03-29 2012-07-24 Npl Associates, Inc. Dislocation site formation techniques
US8603405B2 (en) 2007-03-29 2013-12-10 Npl Associates, Inc. Power units based on dislocation site techniques
WO2008156040A1 (en) * 2007-06-20 2008-12-24 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing semiconductor device
KR100868643B1 (ko) * 2007-07-20 2008-11-12 주식회사 동부하이텍 이미지센서 및 그 제조방법
US8329260B2 (en) 2008-03-11 2012-12-11 Varian Semiconductor Equipment Associates, Inc. Cooled cleaving implant
FR2931293B1 (fr) 2008-05-15 2010-09-03 Soitec Silicon On Insulator Procede de fabrication d'une heterostructure support d'epitaxie et heterostructure correspondante
US8138066B2 (en) * 2008-10-01 2012-03-20 International Business Machines Corporation Dislocation engineering using a scanned laser
JP2011254051A (ja) * 2010-06-04 2011-12-15 Sumitomo Electric Ind Ltd 炭化珪素基板の製造方法、半導体装置の製造方法、炭化珪素基板および半導体装置
US8486776B2 (en) 2010-09-21 2013-07-16 International Business Machines Corporation Strained devices, methods of manufacture and design structures
TW201227828A (en) * 2010-12-31 2012-07-01 Bo-Ying Chen Wafers for nanometer process and manufacturing method thereof
US8809168B2 (en) 2011-02-14 2014-08-19 International Business Machines Corporation Growing compressively strained silicon directly on silicon at low temperatures
GB201114365D0 (en) 2011-08-22 2011-10-05 Univ Surrey Method of manufacture of an optoelectronic device and an optoelectronic device manufactured using the method
FR3003686B1 (fr) * 2013-03-20 2016-11-04 St Microelectronics Crolles 2 Sas Procede de formation d'une couche de silicium contraint
FR3006438B1 (fr) * 2013-06-04 2015-06-26 Commissariat Energie Atomique Capteur de temperature
FR3014244B1 (fr) * 2013-11-29 2018-05-25 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede ameliore de realisation d'un substrat semi-conducteur contraint sur isolant
FR3041146B1 (fr) * 2015-09-11 2018-03-09 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de mise en tension d'un film semi-conducteur
FR3050569B1 (fr) * 2016-04-26 2018-04-13 Commissariat A L'energie Atomique Et Aux Energies Alternatives Fabrication amelioree de silicium contraint en tension sur isolant par amorphisation puis recristallisation
FR3091619B1 (fr) * 2019-01-07 2021-01-29 Commissariat Energie Atomique Procédé de guérison avant transfert d’une couche semi-conductrice
CN116092923B (zh) * 2023-01-16 2025-11-04 湖北九峰山实验室 一种基于碳膜的碳化硅欧姆接触结构及其制备方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1319252A (zh) * 1998-09-25 2001-10-24 旭化成株式会社 半导体衬底及其制造方法、和使用它的半导体器件及其制造方法
US6429061B1 (en) * 2000-07-26 2002-08-06 International Business Machines Corporation Method to fabricate a strained Si CMOS structure using selective epitaxial deposition of Si after device isolation formation
US6593625B2 (en) * 2001-06-12 2003-07-15 International Business Machines Corporation Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing
US6855649B2 (en) * 2001-06-12 2005-02-15 International Business Machines Corporation Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing
US20030077882A1 (en) * 2001-07-26 2003-04-24 Taiwan Semiconductor Manfacturing Company Method of forming strained-silicon wafer for mobility-enhanced MOSFET device
JP2003158250A (ja) * 2001-10-30 2003-05-30 Sharp Corp ＳｉＧｅ／ＳＯＩのＣＭＯＳおよびその製造方法
US6812114B2 (en) * 2002-04-10 2004-11-02 International Business Machines Corporation Patterned SOI by formation and annihilation of buried oxide regions during processing
US6774015B1 (en) * 2002-12-19 2004-08-10 International Business Machines Corporation Strained silicon-on-insulator (SSOI) and method to form the same
US6825102B1 (en) * 2003-09-18 2004-11-30 International Business Machines Corporation Method of improving the quality of defective semiconductor material

Also Published As

Publication number Publication date
WO2005055290A3 (en) 2005-09-09
EP1695377A2 (en) 2006-08-30
KR20060123255A (ko) 2006-12-01
US20050124146A1 (en) 2005-06-09
CN100505163C (zh) 2009-06-24
WO2005055290A2 (en) 2005-06-16
CN1890781A (zh) 2007-01-03
US6972247B2 (en) 2005-12-06
JP2007513511A (ja) 2007-05-24
TWI313511B (en) 2009-08-11
KR100940748B1 (ko) 2010-02-11
TW200529422A (en) 2005-09-01

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