JP4929979B2 - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly to a Schottky diode including a semiconductor layer made of silicon carbide (hereinafter referred to as SiC) and a method for manufacturing the Schottky diode.

  SiC is a material that is expected to be applied to next-generation power semiconductor devices because it has a wide band gap and a maximum insulation electric field that is about an order of magnitude larger than that of silicon (hereinafter referred to as Si). . So far, it is being applied to various electronic devices using a single crystal wafer called 4H—SiC or 6H—SiC, and is considered to be particularly suitable for high-temperature, high-power elements. The above crystal is an alpha phase SiC in which zinc blende type and wurtzite type are laminated. In addition, a semiconductor device is also experimentally manufactured using a beta phase SiC crystal called 3C-SiC. Recently, Schottky diodes, MOSFETs (Metal Oxide Semiconductor Field-Effect Transistors), thyristors, etc. have been prototyped as power elements and their characteristics have been confirmed to be very good compared to conventional Si semiconductor devices. Yes.

  In a semiconductor device having a semiconductor layer made of Si or SiC, the semiconductor layer is epitaxially grown so that the low index plane is inclined from the normal of the substrate surface (with an off angle). According to this method, scratches, dirt, or irregularities on the substrate surface are prevented from affecting the growth of the semiconductor layer, and the flatness of the semiconductor layer surface can be improved to some extent.

In addition, Kazuo Arai and Sadafumi Yoshida, “Basics and Applications of SiC Devices”, published by Ohm, pages 167 to 170 and pages 200 to 204 (Non-Patent Document 1) are electrodes having an off-angle. A Schottky diode used for the surface is disclosed. Non-Patent Document 1 describes basic characteristic values for each plane orientation of a semiconductor layer.
Edited by Kazuo Arai and Sadafumi Yoshida, "Basics and Applications of SiC Devices", published by Ohmsha, pp. 167-170 and 200-204

  However, even if the SiC layer is epitaxially grown at an off angle, a bunching step still exists and a sufficiently flat semiconductor layer surface cannot be obtained. For this reason, the contact between the Schottky electrode and the semiconductor layer is deteriorated, resulting in a problem that electric field concentration occurs. When the electric field concentration occurs, the leakage current increases and the characteristics of the semiconductor device are deteriorated.

  Accordingly, an object of the present invention is to provide a semiconductor device in which electric field concentration hardly occurs and a method for manufacturing the semiconductor device.

The semiconductor device of the present invention includes a semiconductor layer made of SiC, an anode electrode formed on one main surface of the semiconductor layer, and a cathode electrode formed on the other main surface of the semiconductor layer. The semiconductor layer has a facet on one main surface, and an anode electrode is formed so as to be in contact with the facet. In addition, the semiconductor device of the present invention further includes impurity regions of conductivity type that are formed at both ends of the facet and that are different from the semiconductor layer.

The method of manufacturing a semiconductor device of the present invention includes a step of forming a semiconductor layer made of SiC, a facet step of forming a facet on one main surface of the semiconductor layer, and a step of forming an anode electrode so as to contact the facet. And a step of forming a cathode electrode on the other main surface of the semiconductor layer, and a step of forming an impurity region of a conductivity type different from that of the semiconductor layer so as to be disposed at both ends of the facet .

According to the semiconductor device and the semiconductor device manufacturing method of the present invention, the flatness of the semiconductor layer is improved because the length of the flat portion of the facet is longer than the length of the flat portion of the bunching step. As a result, the contact between the anode electrode and the semiconductor layer is improved, and electric field concentration can be made difficult to occur. In addition, when a reverse voltage is applied (when the potential of the cathode electrode is higher than the potential of the anode electrode), the current path extending from the anode electrode to the cathode electrode is blocked by the depletion layer at the boundary between the semiconductor layer and the impurity region. Therefore, the breakdown voltage of the semiconductor device can be improved.

  In the semiconductor device of the present invention, at least one of the facets is preferably constituted by a {0001} plane or a {03-38} plane.

  The {0001} plane and the {03-38} plane in the semiconductor layer made of SiC are planes in which only one of Si or C appears, and are energetically stable planes. Therefore, by forming facets with these surfaces, the density of interface states can be reduced, and the mobility of carriers can be further reduced.

  Preferably, in the semiconductor device of the present invention, the semiconductor layer further includes a plurality of trenches on one main surface. Facets are formed between adjacent trenches, and an impurity region is formed on at least one of the bottom and side surfaces of each trench.

  Thereby, the semiconductor layer between the trenches becomes a current path. When a reverse voltage is applied, the semiconductor layer between the trenches is depleted, so that the current path can be easily cut off and the breakdown voltage of the semiconductor device can be improved.

  Preferably, in the above manufacturing method, the faceting step includes a heat treatment step of heat treating the semiconductor layer in a state where Si is supplied to the surface of the semiconductor layer.

  By heat-treating the semiconductor layer made of SiC while Si is supplied, the semiconductor layer made of SiC can be reconfigured into an energetically stable surface state. As a result, a facet having a period of 100 nm or more is obtained.

  Preferably, in the manufacturing method, the heat treatment step includes a step of forming a coating film containing Si as a main constituent element on one main surface of the semiconductor layer.

  Thereby, the state which supplied Si to the surface of the semiconductor layer which consists of SiC can be implement | achieved by the said coating film. Since the growth in the direction perpendicular to the terrace surface is suppressed at the portion of the semiconductor layer where the coating film is formed, the reconfiguration of the semiconductor layer along the terrace surface can be promoted.

  In the present specification, “Si is a main constituent element” means that Si is contained in an amount of 50% by mass or more.

  Preferably, in the manufacturing method, the faceting step includes a step of forming a resist having an opening whose width continuously decreases in the depth direction on one main surface of the semiconductor layer, and the semiconductor layer is formed using the resist as a mask. Etching.

  Thereby, the surface of the semiconductor layer has a shape corresponding to the shape of the resist, and the facet can be easily formed.

  Preferably, the above manufacturing method further includes a step of planarizing the surface of the semiconductor layer before the heat treatment step.

  Thereby, the semiconductor layer made of SiC is uniformly reconstructed, and the facet grows in a wide area.

  According to the semiconductor device and the manufacturing method of the semiconductor device of the present invention, it is possible to make electric field concentration difficult to occur.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the present specification, the individual orientation is indicated by [], the collective orientation is indicated by <>, the individual plane is indicated by (), and the collective plane is indicated by {}. As for the negative index, “−” (bar) is attached on the number in crystallography, but in this specification, a negative sign is attached before the number.

(Embodiment 1)
FIG. 1 is a cross-sectional view showing the configuration of the semiconductor device according to the first embodiment of the present invention. Referring to FIG. 1, Schottky diode 30 as a semiconductor device of the present embodiment includes an n-type SiC substrate 10 and an n-type SiC layer 11 as semiconductor layers made of SiC. The SiC crystal constituting the SiC substrate 10 has, for example, a (0001) plane inclined by 8 ° in the [11-20] direction (that is, has an off angle of 8 °), or 8 ° in the [1-100] direction. It is formed to have an off angle. The SiC layer 11 is a layer that is homoepitaxially grown on the SiC substrate 10 and inherits the crystal structure of the SiC substrate 10. The SiC layer 11 has a facet forming layer 11a on the upper main surface. In FIG. 1, for convenience of explanation, a boundary line is drawn between the SiC layer 11 and the facet forming layer 11a. However, such a boundary line does not actually exist, and the facet is formed in the SiC layer 11. Formed on the upper main surface.

  FIG. 2 is an enlarged perspective view showing the facet forming layer in FIG. Referring to FIG. 2, when viewed from a microscopic viewpoint, the surface of SiC layer 11 is not flat but uneven, and a plurality of facets 1 are formed on facet forming layer 11a. Each facet 1 is composed of a crystal plane 2 and a crystal plane 3. The crystal plane 3 has a flat portion longer than the crystal plane 2. The length P1 of one cycle of facet 1 is 100 nm or more. Here, the length of one cycle of facet 1 is the crystal plane 2 constituting one facet 1 in the direction along the surface of SiC layer 11 (lateral direction in FIG. 2) when viewed from a macro viewpoint. This is the total length with the crystal plane 3. When SiC layer 11 has a 4H type crystal structure, crystal plane 2 is, for example, a (0001) plane, and crystal plane 3 is, for example, (11-2n) (n is an arbitrary integer) or (03-38). ) Surface. That is, the inclination angle of the crystal plane 3 with respect to the horizontal direction in FIG. 2 is the off angle α of the SiC layer 11.

  Here, the (0001) plane and the (03-38) plane of the 4H type SiC crystal will be described. FIG. 3 is a diagram showing a crystal structure of the (0001) plane of a 4H type SiC crystal.

  Referring to FIG. 3, the (0001) plane of the 4H-type SiC crystal is a plane corresponding to the upper surface of the hexagonal column, and the A layer having the atomic arrangement represented by “A” is the uppermost layer. In the 4H-type SiC crystal, an A layer having an atomic arrangement represented by “A”, a B layer having an atomic arrangement represented by “B”, and a C layer having an atomic arrangement represented by “C”, The layers are stacked in the [0001] direction (a direction perpendicular to the paper surface) in the stacking order ABCCBCA. In the (0001) plane, arbitrary two atoms adjacent to each other among the six atoms arranged at the vertex of the regular hexagon are defined as atoms 5a and 5b, and a straight line connecting these atoms 5a and 5b is a straight line 6a. And Further, in the B layer adjacent to the A layer in the [0001] direction, an atom at a position between the atom 5a and the atom 5b when viewed from the (0001) plane is an atom 5c, and a straight line connecting the atom 5a and the atom 5c is formed. Let it be a straight line 6b. A straight line connecting the atoms 5b and 5c is defined as a straight line 6c. A plane including a triangle formed by the above three straight lines 6a to 6c is a (03-38) plane.

  The SiC layer 11 may have a 6H type crystal structure. In the 6H-type SiC crystal, an A layer having an atomic arrangement represented by “A”, a B layer having an atomic arrangement represented by “B”, and a C layer having an atomic arrangement represented by “C”, Stacked in the [0001] direction in the stacking order ABCACBA. In this case, the crystal plane 2 is, for example, the (0001) plane, and the crystal plane 3 is, for example, the (01-14) plane.

  When the SiC layer 11 having a 4H type crystal structure is formed, the off angle α of the SiC crystal constituting the SiC substrate 10 (the normal of the main surface of the SiC substrate 10 and the normal of the (0001) plane) The angle is preferably 0 degree or more and 55 degrees or less. Since the (03-38) plane is inclined 55 degrees with respect to the (0001) plane, the (0001) plane or the (03-38) plane is a wide faceted plane by setting the off angle α to 55 degrees or less. (Crystal plane 3 in FIG. 2). The off-angle α is more preferably 0 ° or more and 1 ° or less, or 1 ° or more and 10 ° or less. By setting the off angle α to 0 degree or more and 1 degree or less, a SiC crystal having a wide terrace can be obtained. Further, by setting it to 1 degree or more and 10 degrees or less, the SiC crystal can be easily epitaxially grown. When the off angle α is not less than 0 degrees and not more than 10 degrees, the (0001) plane can be obtained as a wide facet plane.

  In addition, when forming SiC layer 11 having a 6H-type crystal structure, the off-angle α of the SiC crystal constituting SiC substrate 10 is preferably 0 ° to 55 °. By setting the off angle α to 55 degrees or less, the (01-14) plane is inclined 55 degrees with respect to the (0001) plane, so the (0001) plane or the (01-14) plane is a wide faceted plane. Can be obtained as The off-angle α is more preferably 0 ° or more and 1 ° or less, or 1 ° or more and 10 ° or less. By setting the off angle α to 0 degree or more and 1 degree or less, a SiC crystal having a wide terrace can be obtained. Further, by setting it to 1 degree or more and 10 degrees or less, the SiC crystal can be easily epitaxially grown. When the off angle α is not less than 0 degrees and not more than 10 degrees, the (0001) plane can be obtained as a wide facet plane.

  With reference to FIGS. 1 and 2, the detailed structure of Schottky diode 30 in the present embodiment will be described. The Schottky diode 30 further includes an anode electrode 13, a cathode electrode 12, a p-type impurity region 15, and an insulating film 14. Anode electrode 13 is formed on upper main surface of SiC layer 11 so as to be in contact with crystal surface 3 of facet 1. The anode electrode 13 and the SiC layer 11 form a Schottky junction. The p-type impurity regions 15 are formed at both ends of the facet 1 on the upper main surface of the SiC layer 11. Insulating film 14 is formed on upper main surface of SiC layer 11 so as to be in contact with crystal surface 2 of facet 1. In other words, the insulating film 14 is formed immediately above the p-type impurity region 15. Cathode electrode 12 is formed on the lower main surface of the SiC substrate. The cathode electrode 12 and the SiC substrate 10 form a Schottky junction.

  The anode electrode 13 is made of, for example, W (tungsten), Ti (titanium), Ni (nickel), or Mo (molybdenum), and the cathode electrode 12 is made of, for example, Al (aluminum).

  Next, the operation of the Schottky diode 30 in the present embodiment will be described. When the anode electrode 13 and the cathode electrode 12 are at the same potential, or when the potential of the cathode electrode 12 is higher than the potential of the anode electrode 13 (when a reverse voltage is applied), the SiC layer 11 and the anode electrode 13 The depletion layer spreads into the n-type SiC layer 11 from the boundary. In addition, depletion layer V extends from SiC layer 11 and p-type impurity region 15 into SiC layer 11. As a result, the current path between the anode electrode 13 and the cathode electrode 12 is interrupted.

  On the other hand, when the potential of the anode electrode 13 is higher than the potential of the cathode electrode 12 (when a forward voltage is applied), the depletion layer at the boundary between the SiC layer 11 and the anode electrode 13 contracts, and the SiC layer 11 The depletion layer V at the boundary with the p-type impurity region 15 contracts. As a result, a portion that is not depleted is formed in SiC layer 11 immediately below anode electrode 13, and current flows between anode electrode 13 and cathode electrode 12 using SiC layer 11 and SiC substrate 10 as current paths.

  Next, an example of a method for manufacturing the Schottky diode 30 in the present embodiment will be described with reference to FIGS.

First, referring to FIG. 4, SiC layer 11 is epitaxially grown on SiC substrate 10. Thereby, a semiconductor layer made of SiC is formed. At this time, many irregular irregularities (steps) exist on the surface of the SiC layer 11. Subsequently, the surface of the SiC layer 11 is planarized. Specifically, the entire surface of SiC layer 11 is etched by etching using HCl (hydrogen chloride) or H ₂ (hydrogen) or reactive ion etching. Further, the entire surface of the SiC layer 11 may be polished by CMP (Chemical Mechanical Polish). Thereby, unevenness existing on the surface of SiC layer 11 and damage to SiC layer 11 due to ion implantation are removed, and the surface of SiC layer 11 is flattened.

  Next, referring to FIG. 5, coating film 20 containing Si as a main constituent element is formed so as to cover SiC layer 11. As a result, Si is supplied to the surface of the SiC layer 11. Subsequently, the SiC layer 11 is heat-treated at a temperature of about 1500 ° C., for example. Thereby, the surface of SiC layer 11 is reconfigured, and a facet forming layer 11a (FIG. 9) described later is formed on the surface of SiC layer 11.

In the above description, the SiC layer 11 is heat treated at 1500 ° C., but the heat treatment temperature of the SiC layer 11 is preferably in the following range. In order to prevent SiC from sublimating and completely decomposing, it is preferably 2545 ° C. or lower. Moreover, in order to suppress to some extent that SiC sublimates in the state of SiC ₂ , Si, Si ₂ C or the like, the temperature is preferably 2000 ° C. or lower. Further, in order to sufficiently suppress the sublimation of SiC in the state of SiC ₂ , Si, Si ₂ C, or the like, and to easily control the surface morphology of the SiC layer 11, the temperature is preferably 1800 ° C. or lower. Furthermore, in order to improve the surface morphology of the SiC layer 11, the temperature is preferably 1600 ° C. or lower. On the other hand, in order to grow SiC and promote facet formation, the temperature is preferably 1300 ° C. or higher. Moreover, in order to make the surface morphology of the SiC layer 11 favorable, it is preferable that it is 1400 degreeC or more.

  Further, the heat treatment time of SiC layer 11 may be longer than 0, and is preferably in the following range. In order to form a relatively large facet, it is preferably 10 minutes or longer. In order to form a facet having a length of one cycle of 0.5 μm or more, it is preferably 30 minutes or more. On the other hand, considering the productivity of the semiconductor device, it is preferably 4 hours or less. In order to efficiently form a facet having a length of one cycle of 1.0 μm or more, it is preferably 2 hours or less. The “heat treatment time” means a time for holding the SiC film at a predetermined temperature, and the “heat treatment time” does not include the temperature raising time and the temperature lowering time.

  Here, how the facet forming layer 11a is formed on the surface of the SiC layer 11 will be described with reference to FIGS. 6 to 8 are enlarged views of a portion B in FIG. Referring to FIG. 6, a number of bunching steps 7 exist on the surface of SiC layer 11 before the heat treatment. Each of the bunching steps 7 includes a crystal face 2a and a crystal face 3a. The crystal surface 3 a has a flat portion longer than the crystal surface 2 a and serves as a terrace surface of the bunching step 7. The length P2 of one cycle of the bunching step 7 is about 10 nm. When the SiC layer 11 is heat-treated in a state where Si is supplied to the surface of the SiC layer 11, the SiC layer 11 does not grow in a direction perpendicular to the crystal plane 3a, and the crystal plane 2a is formed as shown by an arrow in FIG. It grows in the direction along the crystal plane 3a as a starting point. As a result, each of the bunching steps 7 is converged to form a facet 1b having a crystal face 3b wider than the crystal face 3a of the bunching step 7 as shown in FIG. The facet 1b further grows in the direction along the crystal plane 3b starting from the crystal plane 2b. As a result, each of the facets 1b converges to form a facet 1c having a crystal face 3c wider than the crystal face 3b of the facet 1b as shown in FIG. The facet 1c further grows in the direction along the crystal plane 3c starting from the crystal plane 2c. As a result, each of the facets 1c is converged to form a facet 1 having a crystal plane 3 wider than the crystal plane 3c of the facet 1c, as shown in FIG. In this way, facet forming layer 11 a is formed on the upper main surface of SiC layer 11. After forming the facet forming layer 11a, the coating film 20 is removed.

  In the present embodiment, the case where the coating film 20 is formed has been described. However, instead of forming the coating film 20, by introducing a Si-based gas into the surface of the SiC layer 11, Si may be supplied to the surface. Further, Si may be supplied to the surface of the SiC layer 11 by applying a liquid containing Si to the surface of the SiC layer 11.

  Next, referring to FIG. 10, a resist 31 a is formed on crystal face 3 of facet 1. Then, using resist 31a as a mask, ions such as Al are implanted into the upper main surface of SiC layer 11 (crystal surface 2 of facet 1). Thereby, p-type impurity region 15 is formed in the upper main surface of SiC layer 11.

Next, referring to FIG. 11, SiC layer 11 is oxidized to form insulating film 14 made of SiO ₂ (silicon oxide) on the entire upper main surface of SiC layer 11. Subsequently, the cathode electrode 12 is formed on the lower main surface of the SiC substrate 10.

  Next, referring to FIG. 12, a resist 31 b is formed on insulating film 14 immediately above crystal face 2 of facet 1. Then, the insulating film 14 is etched using the resist 31b as a mask. As a result, the insulating film 14 remains only directly above the crystal face 2 of the facet 1.

  Next, referring to FIG. 13, metal film 13 a is formed on resist 31 b and facet crystal plane 3 using a method such as CVD (Chemical Vapor Deposition).

  Next, referring to FIG. 1, resist 31b and metal film 13a on resist 31b are removed by lift-off. Thereby, the anode electrode 13 in contact with the crystal face 3 of the facet 1 is formed. Through the above steps, the Schottky diode 30 according to the present embodiment is completed.

  Schottky diode 30 in the present embodiment includes SiC layer 11, anode electrode 13 formed on the upper main surface of SiC layer 11, and cathode electrode 12 formed on the lower main surface of SiC substrate 10. Yes. The SiC layer 11 has a facet 1 on the upper main surface, and an anode electrode 13 is formed so as to be in contact with the facet 1.

  The manufacturing method of Schottky diode 30 according to the present embodiment includes a step of forming SiC layer 11, a facet step of forming facet 1 on the upper main surface of SiC layer 11, and a contact with crystal plane 3 of facet 1. The step of forming the anode electrode 13 and the step of forming the cathode electrode 12 on the lower main surface of the SiC substrate 10 are provided.

  According to Schottky diode 30 and the manufacturing method thereof in the present embodiment, since the length P1 of the flat portion of facet 1 is longer than the length of flat portion P2 of the bunching step, the flatness of SiC layer 11 is improved. As a result, the contact between the anode electrode 13 and the SiC layer 11 becomes good, and electric field concentration can be made difficult to occur.

  Schottky diode 30 in the present embodiment further includes p-type impurity regions 15 formed at both ends of facet 1. Thereby, when a reverse voltage is applied (when the potential of the cathode electrode 12 is higher than the potential of the anode electrode 13), the depletion layer V at the boundary between the SiC layer 11 and the p-type impurity region 15 causes the anode electrode 13 to Since the current path extending to the cathode electrode 12 is interrupted, the breakdown voltage of the Schottky diode 30 can be improved.

  In Schottky diode 30 according to the present embodiment, facet 1 is configured with (0001) and (03-38) planes. The (0001) plane and the (03-38) plane in the SiC layer 11 are planes on which only one of Si or C appears, and are energetically stable planes. Therefore, by constituting the facet 1 with these surfaces, the interface state density can be reduced, and the carrier mobility can be further reduced.

  In the method for manufacturing Schottky diode 30 in the present embodiment, the facet process includes a heat treatment process in which the SiC layer is heat treated with Si supplied to the surface of SiC layer 11. Thereby, the SiC layer 11 can be reconfigured in an energetically stable surface state by heat-treating the SiC layer 11 with Si supplied. As a result, a facet 1 having one period of 100 nm or more is obtained.

  In the method for manufacturing Schottky diode 30 in the present embodiment, the heat treatment step includes a step of forming coating film 20 containing Si as a main constituent element on the upper main surface of the SiC layer. Thereby, the state in which Si is supplied to the surface of the SiC layer 11 can be realized by the coating film 20. Since the growth in the direction perpendicular to the terrace surface is suppressed at the location where the coating film 20 in the SiC layer 11 is formed, the reconstruction of the SiC layer 11 along the terrace surface can be promoted.

  The method for manufacturing Schottky diode 30 in the present embodiment further includes a step of planarizing the surface of SiC layer 11 before the heat treatment step. Thereby, the SiC layer 11 is uniformly reconfigure | reconstructed and a facet grows in a wide area.

  In the present embodiment, the case where the Schottky diode 30 includes the insulating film 14 and the p-type impurity region 15 has been described, but these configurations may be omitted. Further, although a plurality of anode electrodes 13 are shown in FIG. 1, these electrodes are only required to have the same potential, and may be electrically connected to each other at a position not shown, for example.

  In the manufacturing method of the present embodiment, the method of forming facet 1 by growing SiC layer 11 has been described. However, facet 1 may be formed by the following method, for example. Referring to FIG. 14A, a resist 31c is formed on SiC layer 11. At this time, the resist 31c is patterned so as to have an opening 32 whose width (length in the lateral direction in FIG. 14A) continuously decreases in the depth direction (downward in FIG. 14A). Is done. Subsequently, referring to FIG. 14B, SiC layer 11 is etched using resist 31c as a mask. As a result, facet 1 is formed on the upper main surface of SiC layer 11. According to this method, the surface of the SiC layer 11 has a shape corresponding to the shape of the resist 31c, and the facet 1 can be easily formed.

(Embodiment 2)
FIG. 15 is a cross-sectional view showing the configuration of the semiconductor device according to the second embodiment of the present invention. Referring to FIG. 15, in Schottky diode 30 in the present embodiment, SiC layer 11 has a plurality of trenches 17 on the upper main surface thereof. The trenches 17 are formed at regular intervals, and a facet forming layer 11 a is formed on the upper surface of the SiC layer 11 between adjacent trenches 17. An anode electrode 13 is formed in contact with the facet 17. A p-type impurity region 15 is formed on each bottom surface 17a of the trench 17, and an anode electrode 16 is formed on the bottom surface 17a in contact with the type impurity region 15. The anode electrodes 13 and 16 may be electrically connected to each other to have the same potential, or may be electrically insulated from each other and given different potentials.

  Specific dimensions of the Schottky diode 30 are as follows, for example. The width W of the trench 17 is 2 μm, the distance D between the trenches 17 is 1 μm, and the height H of the trench 17 is 0.5 μm.

  Since the other configuration is substantially the same as that of Schottky diode 30 shown in the first embodiment, the same reference numeral is given to the same configuration, and the description thereof will not be repeated.

  Next, an example of a method for manufacturing the Schottky diode 30 in the present embodiment will be described with reference to FIGS.

  First, referring to FIG. 16, SiC layer 11 is formed on SiC substrate 10 by the same method as in the first embodiment. Subsequently, a resist 31 d having a predetermined shape is patterned on the upper main surface of the SiC layer 11. Then, SiC layer 11 is etched using resist 31d as a mask. Thereby, trench 17 is formed in SiC layer 11.

  Next, referring to FIG. 17, coating film 20 containing Si as a main constituent element is formed so as to cover the upper surface of SiC layer 11 between trenches 17. Subsequently, heat treatment similar to that of the first embodiment is performed, and facet forming layer 11a is formed on the upper surface of SiC layer 11 as shown in FIG. Thereafter, the coating film 20 is removed.

  Subsequently, referring to FIG. 19, a resist 31 e is formed on the upper main surface of SiC layer 11 between trenches 17. With this resist 31 e as a mask, ions such as Al are applied to the SiC layer on bottom surface 17 a of trench 17. 11 is injected. Thereby, the p-type impurity region 15 is formed on the bottom surface 17a of the trench. Thereafter, the resist 31e is removed.

  Next, referring to FIG. 15, cathode electrode 12 is formed on the lower main surface of SiC substrate 10. Then, anode electrode 13 is formed on the upper main surface of SiC layer 11, and anode electrode 13 is formed on bottom surface 17 a of trench 17. As a result, the Schottky diode 30 in the present embodiment is completed.

  According to the Schottky diode 30 of the present embodiment, the following effects can be obtained in addition to substantially the same effects as the Schottky diode of the first embodiment.

  In Schottky diode 30 in the present embodiment, SiC layer 11 further includes a plurality of trenches 17 in the upper main surface. Facets 1 are formed between adjacent trenches 17, and p-type impurity regions 15 are formed on the bottom surfaces 17 a of the trenches 17. Thereby, the SiC layer 11 between the trenches 17 becomes a current path. When a reverse voltage is applied, depletion layer V extends in SiC layer 11 between trenches 17, so that the current path can be easily cut off and the breakdown voltage of the semiconductor device can be improved.

  In the present embodiment, the p-type impurity region 15 is formed on the bottom surface 17a of the trench 17. However, as shown in FIG. 20, for example, the p-type impurity is formed on the bottom surface 17a and the side surface 17b of the trench. Region 15 may be formed. Further, the p-type impurity region 15 may be formed only on the side surface 17 b of the trench 17.

  In the above embodiment, the crystal plane may be described by individual planes such as the (0001) plane and the (03-38) plane. If the plane is the (0001) plane, the {0001} plane, (03-38) The same effect can be obtained if it is a collective surface equivalent to these individual surfaces, such as {03-38} surface.

  Further, in the above embodiment, the case where SiC substrate 10 and SiC layer 11 are n-type and impurity region 15 is p-type has been described, but SiC substrate 10 and SiC layer 11 are p-type and impurity region 15 may be n-type.

In this example, the Schottky diode shown in FIG. 15 was manufactured. Specifically, a 4H type SiC substrate having a thickness of 400 μm, a resistivity of 0.022 Ω · cm, and a (0001) plane off-angle of 8 ° was prepared. Next, an SiC layer having a thickness of 10 μm and a concentration of 5 × 10 ¹⁵ cm ⁻³ was formed on the SiC substrate. The SiC layer was formed using a CVD epitaxial method. Next, a resist having a predetermined shape was patterned, and the SiC layer was dry etched by RIE (Reactive Ion Etching) using this resist as a mask. As a result, trenches having a width of 2 μm, a depth of 0.5 μm, and an interval of 1 μm were formed. Subsequently, a coating film made of Si was formed on the upper surface of the SiC layer, and the SiC layer was heat-treated at a temperature of 1600 ° C. As a result, a facet having a period length of 2 μm was formed. Subsequently, a p-type impurity region having a concentration of 2 × 10 ¹⁷ cm ⁻³ and a depth of 1 μm was formed on the bottom surface of the trench by ion implantation. Thereafter, a cathode electrode made of Al was formed on the lower main surface of the SiC substrate, and an anode electrode made of Ni was formed on the upper main surface of the SiC layer. Further, as a comparative example, a Schottky diode (hereinafter referred to as a comparative example) having a configuration substantially similar to the configuration of FIG. 15 except that facets were not formed was manufactured.

  Next, the electrical characteristics of the manufactured Schottky diode were examined. As a result, in the Schottky diode of the present invention, the current during forward voltage application was increased and the on-resistance was reduced as compared with the comparative example. Regarding the breakdown voltage against the reverse voltage, the breakdown voltage of the comparative example was 1 kV, whereas the breakdown voltage of the Schottky diode of the present invention was 1.2 kV, which greatly improved the breakdown voltage.

  The embodiments and examples disclosed above are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is shown not by the above embodiments and examples but by the scope of claims, and is intended to include all modifications and variations within the meaning and scope equivalent to the scope of claims. .

It is sectional drawing which shows the structure of the semiconductor device in Embodiment 1 of this invention. It is a perspective view which expands and shows the facet formation layer in FIG. It is a figure which shows the crystal structure of (0001) plane of 4H type SiC crystal. It is sectional drawing which shows the 1st process of the manufacturing method of the Schottky diode in Embodiment 1 of this invention. It is sectional drawing which shows the 2nd process of the manufacturing method of the Schottky diode in Embodiment 1 of this invention. FIG. 6 is an enlarged view of part B of FIG. 5 showing a first state in which a facet forming layer is formed. It is the B section enlarged view of Drawing 5 showing the 2nd state where a facet formation layer is formed. FIG. 6 is an enlarged view of part B of FIG. 5 showing a third state in which a facet forming layer is formed. It is sectional drawing which shows the 3rd process of the manufacturing method of the Schottky diode in Embodiment 1 of this invention. It is sectional drawing which shows the 4th process of the manufacturing method of the Schottky diode in Embodiment 1 of this invention. It is sectional drawing which shows the 5th process of the manufacturing method of the Schottky diode in Embodiment 1 of this invention. It is sectional drawing which shows the 6th process of the manufacturing method of the Schottky diode in Embodiment 1 of this invention. It is sectional drawing which shows the 7th process of the manufacturing method of the Schottky diode in Embodiment 1 of this invention. (A) is sectional drawing which shows the 1st process of the modification of the manufacturing method of the Schottky diode in Embodiment 1 of this invention, (b) is manufacture of the Schottky diode in Embodiment 1 of this invention. It is sectional drawing which shows the 2nd process of the modification of a method. It is sectional drawing which shows the structure of the semiconductor device in Embodiment 2 of this invention. It is sectional drawing which shows the 1st process of the manufacturing method of the Schottky diode in Embodiment 2 of this invention. It is sectional drawing which shows the 2nd process of the manufacturing method of the Schottky diode in Embodiment 2 of this invention. It is sectional drawing which shows the 3rd process of the manufacturing method of the Schottky diode in Embodiment 2 of this invention. It is sectional drawing which shows the 4th process of the manufacturing method of the Schottky diode in Embodiment 2 of this invention. It is sectional drawing which shows the structure of the modification of the Schottky diode in Embodiment 2 of this invention.

Explanation of symbols

  1, 1b, 1c facet, 2, 2a-2c, 3, 3a-3c crystal plane, 5a-5c atoms, 6a-6c straight line, 7 bunching step, 10 SiC substrate, 11 SiC layer, 11a facet forming layer, 12 cathode Electrode, 13 Anode electrode, 13a Metal film, 14 Insulating film, 15 P-type impurity region, 16 Anode electrode, 17 Trench, 17a Trench bottom, 17b Trench side, 20 Cover film, 30 Schottky diode, 31a to 31e Resist, 32 opening.

Claims (7)

A semiconductor layer made of silicon carbide;
An anode electrode formed on one main surface of the semiconductor layer;
A cathode electrode formed on the other main surface of the semiconductor layer,
The semiconductor layer has a facet on the one main surface, and the anode electrode is formed so as to be in contact with the facet ,
A semiconductor device further comprising impurity regions of a conductivity type formed at both ends of the facet and different from the semiconductor layer . 2. The semiconductor device according to claim 1, wherein at least one of the facets is constituted by a {0001} plane or a {03-38} plane. The semiconductor layer further includes a plurality of trenches on the one main surface,
The facet is formed between the adjacent trenches,
Wherein the impurity regions on at least one surface of the bottom and side surfaces of each of said trench is formed, the semiconductor device according to claim 1 or 2. Forming a semiconductor layer made of silicon carbide;
A faceting step of forming a facet on one main surface of the semiconductor layer;
Forming an anode electrode in contact with the facet;
Forming a cathode electrode on the other main surface of the semiconductor layer ;
Forming an impurity region of a conductivity type different from that of the semiconductor layer so as to be disposed at both ends of the facet . 5. The method of manufacturing a semiconductor device according to claim 4 , wherein the faceting step includes a heat treatment step of heat-treating the semiconductor layer in a state where silicon is supplied to a surface of the semiconductor layer. The semiconductor device manufacturing method according to claim 5 , wherein the heat treatment step includes a step of forming a coating film containing silicon as a main constituent element on one main surface of the semiconductor layer. The faceting step includes a step of forming a resist having an opening having a width continuously decreasing in the depth direction on the one main surface of the semiconductor layer, and etching the semiconductor layer using the resist as a mask. The method for manufacturing a semiconductor device according to claim 4 , further comprising a step.

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