JP2013172119A - Silicon carbide semiconductor device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor device having a low on resistance which can be manufactured easily.SOLUTION: A mask 60 is formed on the first surface P1 of a silicon carbide substrate SB having first conductivity type. The first surface P1 is etched so that a trench TR, having a sidewall SW inclining for the first surface P1 and holding the silicon carbide substrate SB partially, is formed on the first surface P1. Impurities of a conductivity type for imparting a second conductivity type to silicon carbide are injected on the sidewall SW, so that a gate region 14 of second conductivity type provided on the sidewall SW, and a channel region 10 of a first conductivity type having a part held by the gate region 14 and a part forming a second surface P2 are formed of the silicon carbide substrate SB.

Description

  The present invention relates to a silicon carbide semiconductor device and a manufacturing method thereof, and more particularly to a silicon carbide semiconductor device having a gate electrode and a manufacturing method thereof.

  As a power semiconductor device using a silicon substrate, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a trench gate has been widely used. On the other hand, the use of silicon carbide instead of silicon has been actively studied. It is expected that the on-resistance of the semiconductor device can be further reduced by using silicon carbide. However, so far, a MOSFET having a low on-resistance as theoretically expected has not been obtained. This is presumably because the channel mobility that greatly affects the on-resistance is significantly smaller than the theoretical value predicted from the physical properties of silicon carbide. According to Japanese Patent Laid-Open No. 2011-23675 (Patent Document 1), it is pointed out that the decrease in channel mobility of a trench MOSFET using silicon carbide is caused by the fact that the trench side wall surface is not smooth.

  Unlike a MOSFET, in the case of a junction field effect transistor (JFET), the above-described problem of reduction in channel mobility can be substantially avoided. This is because most of the channels in the JFET are located in the bulk crystal and are not easily affected by the crystal surface.

Non-Patent Document 1 (Yasunori Tanaka et.al, “700-V 1.0-mΩ · cm ² Buried Gate SiC-SIT (SiC-BGSIT)”, IEEE Electron Devices Letters, Vol. 27, No. 11, (6. ), Pp. 908-910), a silicon carbide semiconductor device called an electrostatic induction transistor (SIT: Static Induction Transistor) or a junction field effect transistor (JFET: Junction Field Effect Transistor) is proposed. Has been. This JFET has a buried gate constituted by a p ⁺ gate layer. The manufacturing method of this JFET includes the following steps. In the first step, an n ⁻ drift layer and a p ⁺ gate layer are epitaxially grown on the n ⁺ 4H—SiC substrate. In the second step, the p ⁺ gate layer is dry etched to form a fine trench structure. In the third step, an n ⁻ channel region is formed by epitaxial growth so as to cover the trench structure.

JP 2011-23675 A

Yasunori Tanaka et. al, “700-V 1.0-mΩ · cm 2 Buried Gate SiC-SIT (SiC-BGSIT)”, IEEE Electron Device Letters, Vol. 27, no. 11, (2006), pp. 908-910

In the above JFET, the width of the trench formed in the p ⁺ gate layer corresponds to the channel width. Therefore, in order to be able to control the channel without using an extremely large gate voltage, it is necessary to make the width of the trench fine. If there is a variation in the formation of the n ⁻ channel region filling the trench, variations occur in the pn junction surface formed by the p ⁺ gate layer and the n ⁻ channel region, and the JFET characteristics vary. For this reason, in the above-described JFET manufacturing method, it is necessary to perform fine processing for forming a fine trench and epitaxial growth for accurately filling the fine trench. Thus, the above-described JFET manufacturing method is highly difficult.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a silicon carbide semiconductor device that has a low on-resistance and can be easily manufactured. is there.

  The method for manufacturing a silicon carbide semiconductor device of the present invention includes the following steps. A silicon carbide substrate having a first surface and a second surface facing each other in the thickness direction and having a first conductivity type is prepared. A mask having an opening and a masking portion sandwiched by the opening in the in-plane direction intersecting the thickness direction is formed on the first surface of the silicon carbide substrate. Carbonization is performed using a mask so that a trench having a side wall that is inclined by an angle smaller than 90 ° with respect to the first surface and that partially sandwiches the silicon carbide substrate in the in-plane direction is formed on the first surface. The first surface of the silicon substrate is etched. A gate region provided on the sidewall of the trench and having a second conductivity type different from the first conductivity type; a portion having the first conductivity type and sandwiched between the gate regions in the in-plane direction; and A second conductivity type different from the first conductivity type is imparted to silicon carbide on the sidewall of the silicon carbide substrate so that the channel region having a portion forming the second surface is formed from the silicon carbide substrate. Conductive impurities are implanted. A gate electrode in contact with the gate region and away from the channel region is formed in the trench. A source electrode in contact with the channel region is formed on the first surface. A drain electrode in contact with the channel region is formed on the second surface.

  According to this manufacturing method, since a JFET structure having a pn junction surface formed at the interface between the gate region and the channel region is provided, a decrease in channel mobility can be avoided as compared with the MOSFET structure. As a result, the on-resistance can be lowered. Further, according to this manufacturing method, the pn junction surface for controlling the channel is formed not by burying the trench but by implanting impurities onto the side wall of the silicon carbide substrate. Therefore, since it is not necessary to fill the trench with high accuracy, the silicon carbide semiconductor device can be easily manufactured. As described above, according to this manufacturing method, a silicon carbide semiconductor device having a low on-resistance can be easily manufactured.

  Preferably, the step of implanting the conductivity type impurity is performed using the mask. This eliminates the need to separately form a mask for implanting the conductive impurities. Therefore, the silicon carbide semiconductor device can be manufactured more easily.

  Preferably, the step of etching the first surface of the silicon carbide substrate includes a step of performing thermal etching. Thereby, a trench having a side wall having a predetermined slope can be stably formed. Therefore, variation in characteristics of the silicon carbide semiconductor device can be suppressed.

  Preferably, the first conductivity type is n-type. This provides an n-channel JFET structure. Therefore, the on-resistance can be further reduced.

  The silicon carbide semiconductor device of the present invention has a silicon carbide substrate, a gate electrode, a source electrode, and a drain electrode. The silicon carbide substrate has a first surface and a second surface facing the first surface in the thickness direction. A trench having side walls is provided on the first surface. The side wall is inclined by an angle smaller than 90 ° with respect to the first surface. The sidewall partially sandwiches the silicon carbide substrate in the in-plane direction that intersects the thickness direction. The silicon carbide substrate has a gate region and a channel region. The gate region is provided on the sidewall of the trench and has a second conductivity type different from the first conductivity type. The channel region has a first conductivity type, has a portion sandwiched between gate regions in the in-plane direction, and has a portion forming a second surface. The gate electrode is provided in the trench, is in contact with the gate region, and is separated from the channel region. The source electrode is in contact with the channel region on the first surface. The drain electrode is in contact with the channel region on the second surface.

  According to this silicon carbide semiconductor device, since the JFET structure having the pn junction surface formed at the interface between the gate region and the channel region is provided, a decrease in channel mobility can be avoided as compared with the MOSFET structure. As a result, the on-resistance can be lowered. According to this silicon carbide semiconductor device, the pn junction surface for controlling the channel can be formed not by burying the trench but by implanting impurities onto the sidewall of the silicon carbide substrate. Therefore, since it is not necessary to fill the trench with high accuracy, the silicon carbide semiconductor device can be obtained more easily. As described above, according to this silicon carbide semiconductor device, the on-resistance can be lowered and the silicon carbide silicon carbide semiconductor device can be obtained more easily.

  As described above, according to the present invention, it is possible to provide a silicon carbide semiconductor device that has a low on-resistance and can be easily manufactured.

FIG. 4 schematically shows a configuration of a silicon carbide semiconductor device in one embodiment of the present invention, and is a cross-sectional view taken along a line II in FIG. 2 and FIG. 3. FIG. 2 is a plan view schematically showing a structure of the silicon carbide semiconductor device of FIG. 1. FIG. 2 is a plan view schematically showing a structure of a silicon carbide substrate included in the silicon carbide semiconductor device of FIG. 1. 1 is a cross sectional view schematically showing an on state of a silicon carbide semiconductor device in one embodiment of the present invention. 1 is a cross sectional view schematically showing an off state of a silicon carbide semiconductor device in one embodiment of the present invention. It is sectional drawing which shows schematically the 1st process of the manufacturing method of the silicon carbide semiconductor device in one embodiment of this invention. FIG. 6 is a plan view schematically showing a second step of the method for manufacturing the silicon carbide semiconductor device in one embodiment of the present invention. It is a schematic sectional drawing in alignment with line VIII-VIII of FIG. FIG. 11 is a plan view schematically showing a third step of the method for manufacturing the silicon carbide semiconductor device in one embodiment of the present invention. It is a schematic sectional drawing in alignment with line XX of FIG. FIG. 10 is a cross sectional view schematically showing a fourth step of the method for manufacturing the silicon carbide semiconductor device in one embodiment of the present invention. FIG. 10 is a cross sectional view schematically showing a fifth step of the method for manufacturing the silicon carbide semiconductor device in one embodiment of the present invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

  As shown in FIGS. 1 and 2, JFET 90 (silicon carbide semiconductor device) of the present embodiment has an epitaxial substrate SB (silicon carbide substrate), a gate electrode 40, a source electrode 41, and a drain electrode 42. . Epitaxial substrate SB is made of silicon carbide.

  As shown in FIGS. 1 and 3, the epitaxial substrate SB includes an upper surface P1 (first surface) and a lower surface P2 (second surface) facing the upper surface P1 in the thickness direction (vertical direction in FIG. 1). Have A trench TR having a sidewall SW is provided on the upper surface P1. The side wall SW is inclined by an angle smaller than 90 ° with respect to the upper surface P1. Sidewall SW partially sandwiches epitaxial substrate SB in the in-plane direction (lateral direction in FIG. 1) intersecting the thickness direction. When the epitaxial substrate SB has a hexagonal crystal structure, the upper surface P1 of the epitaxial substrate SB surrounded by the trench TR preferably has a hexagonal shape. Further, the side walls SW connected to each of the six sides of the hexagon are preferably crystallographically equivalent.

Epitaxial substrate SB has gate region 14 and channel region 10.
Gate region 14 is provided on sidewall SW of trench TR. The gate region 14 has a p-type (second conductivity type different from the first conductivity type). Gate region 14 has a bottom surface BT substantially parallel to side wall SW and a side surface SD extending so as to connect between bottom surface BT and side wall SW. The side surface SD extends approximately in the thickness direction (vertical direction in FIG. 1).

  Channel region 10 has n-type (first conductivity type). The channel region 10 has a portion sandwiched between the gate regions 14 in the in-plane direction (lateral direction in FIG. 1). The channel region 10 has a portion that forms the lower surface P2. In the present embodiment, channel region 10 has a single crystal substrate 11 and an epitaxial layer 12. Single crystal substrate 11 has an n-type and has lower surface P2. Epitaxial layer 12 is made of silicon carbide epitaxially grown on single crystal substrate 11, has an n-type, and has upper surface P1.

  Gate electrode 40 is provided in trench TR, is in contact with gate region 14 and is separated from channel region 10. The source electrode 41 is in ohmic contact with the channel region 10 on the upper surface P1. The drain electrode 42 is in ohmic contact with the channel region 10 on the lower surface P2.

Next, the operation of JFET 90 will be described below.
Referring to FIG. 4, JFET 90 is used as a switching element having a carrier (electron in the present embodiment) path EL between source electrode 41 and drain electrode 42. In the on state (the state shown in FIG. 4), carriers pass through the portion sandwiched between the gate regions 14 in the in-plane direction (lateral direction in the drawing) of the channel region 10. Specifically, the carriers injected from the source electrode 41 pass through a portion of the channel region 10 sandwiched between the side surfaces SD of the gate region 14 and are sandwiched by the bottom surface BT of the gate region 14 of the channel region 10. It passes through the portion and is discharged from the drain electrode 42.

  Referring to FIG. 5, when a voltage exceeding a threshold value is applied to gate region 14 through gate electrode 40, a depletion layer is formed from gate region 14 into channel region 10 as indicated by an arrow in the drawing. Extend. Specifically, a portion of the channel region 10 sandwiched between the side surfaces SD of the gate region 14 in the in-plane direction (lateral direction in the figure) is depleted by a depletion layer extending as indicated by an arrow DS in the figure. Is done. Further, a portion of the channel region 10 sandwiched between the bottom surfaces BT of the gate regions 14 in the in-plane direction is depleted by a depletion layer extending as indicated by an arrow DB in the drawing. As a result, the carrier path EL (FIG. 4) is blocked. That is, JFET 90 is turned off.

Next, a method for manufacturing JFET 90 will be described below.
As shown in FIG. 6, an epitaxial substrate SB having an upper surface P1 and a lower surface P2 facing each other in the thickness direction and having an n-type is prepared. Specifically, epitaxial layer 12 is formed on single crystal substrate 11. Epitaxial layer 12 can be formed by, for example, a chemical vapor deposition (CVD) method.

  As shown in FIGS. 7 and 8, on the upper surface P1 of the epitaxial substrate SB, a mask 60 having an opening OP and a masking portion MS sandwiched by the opening OP in the in-plane direction (lateral direction in FIG. 8). Is formed. The position of the opening OP corresponds to the position where the trench TR (FIGS. 1 and 3) is to be formed. The material of the mask 60 is, for example, silicon oxide.

  As shown in FIGS. 9 and 10, upper surface P <b> 1 of epitaxial substrate SB is etched using mask 60. Thereby, trench TR having sidewall SW is formed on upper surface P1. Sidewall SW is formed so as to be inclined with respect to upper surface P1 by an angle smaller than 90 ° and to partially sandwich epitaxial substrate SB in the in-plane direction (lateral direction in FIG. 10). Preferably, this etching is performed by thermal etching (details will be described later).

  As shown in FIG. 11, a conductive impurity for imparting p-type to silicon carbide is implanted onto sidewall SW of epitaxial substrate SB using mask 60. Thereby, the gate region 14 and the channel region 10 are formed from the epitaxial substrate SB. Gate region 14 has a p-type and is provided on sidewall SW of trench TR. The channel region 10 has an n-type, a portion sandwiched between the gate regions 14 in the in-plane direction, and a portion forming the lower surface P2. Next, the mask 60 is removed (FIG. 12).

  Referring again to FIG. 1, gate electrode 40 in contact with gate region 14 and away from channel region 10 is formed in trench TR. A source electrode 41 in contact with the channel region 10 is formed on the upper surface P1. A drain electrode 42 in contact with the channel region 10 is formed on the lower surface P2. Thus, JFET 90 is obtained.

  According to the present embodiment, a JFET structure having a pn junction formed at the interface between the gate region 14 and the channel region 10 is provided (FIG. 1). Unlike the channel formed at the interface between the semiconductor and the oxide in the MOSFET structure, the channel of the JFET structure includes a current path EL (FIG. 4) in the bulk crystal. Accordingly, a decrease in channel mobility can be avoided, so that the on-resistance can be lowered.

  The pn junction surface is formed by implanting impurities onto the sidewall SW of the epitaxial substrate SB (FIG. 11). Therefore, the JFET 90 can be easily manufactured.

  Further, when impurities are implanted, mask 60 (FIG. 10) used in the step of etching upper surface P1 of the silicon carbide substrate is used. This eliminates the need to separately form a mask for implanting impurities. Therefore, the JFET 90 can be manufactured more easily.

  Further, since the first conductivity type is n-type, an n-channel JFET structure is provided. Therefore, the on-resistance can be further reduced as compared with the p-channel type.

  Further, the shape of the channel sandwiched between the gate regions 14 is not defined by one channel width and one channel length as in a normal JFET structure, but is a degree of taper-shaped expansion toward the drain electrode 42. That is, the angle of the bottom surface BT of the gate region 14. Therefore, the threshold characteristic of the JFET structure can be adjusted more finely. The angle of the bottom surface BT can be easily adjusted by the angle of the side wall SW of the trench TR.

  Preferably, the step of etching upper surface P1 of epitaxial substrate SB (FIG. 10) includes a step of performing thermal etching. Thereby, it is possible to stably form the trench TR having the sidewall SW having a predetermined inclination. Therefore, characteristic variation of JFET 90 (FIG. 1) can be suppressed.

Here, “thermal etching” is performed by exposing an object to be etched to an etching gas at a high temperature, and has substantially no physical etching action. By using thermal etching, a crystallographically specific side wall SW can be self-formed. The thermal etching process gas preferably contains a halogen atom, and more preferably the halogen atom is a chlorine atom. Specifically, the process gas may be Cl ₂ gas. Preferably, the process gas further includes a gas containing oxygen atoms in addition to the gas containing a halogen element. Specifically, the gas containing oxygen atoms may be O ₂ gas. The process gas may contain a carrier gas. As the carrier gas, for example, N ₂ gas, Ar gas, or He gas can be used. The heat treatment temperature for thermal etching is preferably 700 ° C. or higher and 1200 ° C. or lower. The lower limit of this temperature is more preferably 800 ° C, and still more preferably 900 ° C. Further, the upper limit of this temperature is more preferably 1100 ° C., still more preferably 1000 ° C. In this case, the etching rate can be set to a sufficiently practical value. When the heat treatment temperature is set to 700 ° C. or higher and 1000 ° C. or lower, the etching rate of silicon carbide is about 70 μm / hr, for example.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above-described embodiment but by the scope of claims, and is intended to include all modifications within the meaning and scope equivalent to the scope of claims.

  For example, the first conductivity type is not necessarily n-type and the second conductivity type is not necessarily p-type. Conversely, the first conductivity type is p-type and the second conductivity type is n-type. There may be. In the step of injecting the conductivity type impurity, the mask used in the step of etching the first surface of the silicon carbide substrate is not necessarily used. In other words, a mask used in the step of implanting the conductivity type impurity may be separately formed. Etching for forming the trench is not limited to thermal etching, and other dry etching methods may be used. For example, dry etching such as reactive ion etching or ion beam etching may be used. Further, wet etching may be used instead of dry etching.

  10 channel region, 11 single crystal substrate, 12 epitaxial layer, 14 gate region, 40 gate electrode, 41 source electrode, 42 drain electrode, 60 mask, 90 JFET (silicon carbide semiconductor device), BT bottom surface, MS masking portion, OP opening Part, P1 upper surface (first surface), P2 lower surface (second surface), SB epitaxial substrate (silicon carbide substrate), SD side surface, SW side wall, TR trench.

Claims (5)

Preparing a silicon carbide substrate having a first conductivity type and a first surface and a second surface facing each other in the thickness direction;
Forming a mask having an opening and a masking portion sandwiched between the openings in an in-plane direction intersecting the thickness direction on the first surface of the silicon carbide substrate;
The trench is formed on the first surface so as to have a side wall that is inclined with respect to the first surface by an angle smaller than 90 ° and partially sandwiches the silicon carbide substrate in the in-plane direction. Etching the first surface of the silicon carbide substrate using a mask;
A gate region provided on the sidewall of the trench and having a second conductivity type different from the first conductivity type; and having the first conductivity type and sandwiched between the gate regions in the in-plane direction A channel region having a portion and having a portion forming the second surface is different from the first conductivity type on the side wall of the silicon carbide substrate so as to be formed from the silicon carbide substrate. Injecting a conductivity type impurity for imparting a second conductivity type to silicon carbide;
Forming a gate electrode in the trench in contact with the gate region and away from the channel region;
Forming a source electrode in contact with the channel region on the first surface;
Forming a drain electrode in contact with the channel region on the second surface.   The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the step of injecting the conductivity type impurity is performed using the mask.   The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the step of etching the first surface of the silicon carbide substrate includes a step of performing thermal etching.   The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the first conductivity type is an n-type. A silicon carbide semiconductor device,
A silicon carbide substrate having a first surface provided with a trench having a side wall and a second surface facing the first surface in the thickness direction; and the side wall with respect to the first surface The sidewall is inclined by an angle smaller than 90 °, and the sidewall partially sandwiches the silicon carbide substrate in an in-plane direction intersecting the thickness direction, and the silicon carbide substrate is disposed on the sidewall of the trench. A gate region having a second conductivity type different from the first conductivity type, a portion having the first conductivity type and sandwiched between the gate regions in the in-plane direction, and A channel region having a portion forming the second surface, wherein the silicon carbide semiconductor device is further provided in the trench, and a gate electrode in contact with the gate region and away from the channel region;
A source electrode in contact with the channel region on the first surface;
A silicon carbide semiconductor device comprising: a drain electrode in contact with the channel region on the second surface.

Images