JP5332216B2 - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can form an impurity region precisely at a desired position, and to provide its fabrication process. <P>SOLUTION: A fabrication process of a Schottky barrier diode comprises a step for forming an n-type SiC layer 10, a step for forming a trench 30 on the surface of the n-type SiC layer 10, and a step for heat treating the n-type SiC layer 10 while supplying silicon and nitrogen to the surface of the n-type SiC layer 10 after the step for forming a trench 30. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a semiconductor film made of silicon carbide (SiC) and a manufacturing method thereof.

  SiC is a material that is expected to be applied to next-generation power semiconductor devices because it has a wide band gap and a maximum insulation electric field that is about an order of magnitude larger than that of silicon (Si). So far, it is being applied to various electronic devices using a single crystal wafer called 4H—SiC or 6H—SiC, and is considered to be particularly suitable for high-temperature, high-power elements. The above crystal is an alpha phase SiC in which zinc blende type and wurtzite type are laminated. In addition, a semiconductor device is also experimentally manufactured using a beta phase SiC crystal called 3C-SiC. Recently, Schottky diodes, MOSFETs (metal oxide semiconductor field-effect transistors), thyristors, etc. have been prototyped as power elements, and their characteristics have been confirmed to be very good compared to conventional Si semiconductor devices. Yes.

  In a semiconductor device using SiC, in particular, in a MOSFET having a structure in which a channel is formed on the surface of a SiC substrate, a surface formed by high-temperature annealing has been conventionally used as a channel. However, there are irregular irregularities on the surface of the SiC substrate obtained by high-temperature annealing. For this reason, when the density of interface states increases, there is a problem that the mobility of carriers decreases and the characteristics of the semiconductor device deteriorate.

A technique that can solve this problem is disclosed in, for example, Japanese Patent Laid-Open No. 2006-344942 (Patent Document 1). In Patent Document 1, two trenches are formed on the surface of the SiC film, and then the SiC film is heat-treated with Si supplied to the surface of the SiC film. Thereby, facets (macrosteps) having a length of one cycle of 100 nm or more are formed at positions between the trenches. Next, an insulating film having a predetermined shape is formed on the macro step, and impurity ions are implanted into the macro step using the insulating film as a mask to remove the insulating film. Thus, the source contact region and the drain contact region are formed so as to sandwich the macro step terrace. As a result, the terrace of the macro step becomes the channel of the MOSFET.
JP 2006-344942 A

  In the technique of Patent Document 1 described above, an insulating film is used as a mask layer when impurity ions are implanted. Thus, conventionally, in order to form an impurity region at a desired position, it is necessary to form a mask layer, and the accuracy of the impurity region depends on the accuracy of the mask layer. For this reason, it has been difficult to accurately form the impurity region in the desired region. This problem is not limited to the formation of a channel on the surface of the SiC substrate, but may occur in general semiconductor devices.

  Accordingly, an object of the present invention is to provide a semiconductor device and a manufacturing method thereof in which an impurity region can be accurately formed at a desired position.

The semiconductor device according to the present invention includes a semiconductor film made of SiC. The semiconductor film has on its surface a macro step provided with a riser surface and a terrace surface adjacent to each other in the periodic direction . The semiconductor device includes a first conductivity type impurity region formed on the entire macrostep riser surface and a second surface formed on the entire macrostep terrace surface in a cross-sectional view taken along the periodic direction . And another impurity region of conductivity type . The impurity region includes at least one of a nitrogen atom and a boron atom.

A method for manufacturing a semiconductor device according to one aspect of the present invention includes a step of forming a semiconductor film made of SiC, a step of forming a groove on a surface of the semiconductor film, and a step of forming the groove, and heat-treating the semiconductor film. In this way, a step of forming a macro step in which a riser surface and a terrace surface adjacent to each other in the periodic direction are provided on the surface of the semiconductor film is provided. And Si in the surface of the semiconductor film by the semiconductor film is Ru is heat treated while supplying at least one of the impurities of the nitrogen and boron, more than the terrace surface in the cross-sectional view according to section along the periodic direction impurity regions of a first conductivity type having a higher concentration of impurities Ru is formed on the riser surface.

  According to the semiconductor device of the present invention and the method of manufacturing a semiconductor device according to one aspect, the semiconductor film is heat-treated in a state where Si is supplied to the surface of the semiconductor film made of SiC. Can be reconfigured. As a result, a macro step having a period of 100 nm or more is obtained at the position where the groove is formed on the surface of the semiconductor film, and the length of the flat portion of the macro step can be made longer than before.

  In addition, nitrogen or boron penetrates into the semiconductor film through Si during the heat treatment, and is replaced with carbon (C) atoms constituting the SiC crystal, thereby forming an impurity region. Here, since the riser of the macrostep is an unstable surface compared to the terrace, more nitrogen or boron enters the riser than the terrace. As a result, an impurity region having a higher concentration than the terrace is formed in the riser. As a result, the impurity region can be accurately formed at the desired position by using the desired position as the riser.

  In the semiconductor device of the present invention, preferably, the macro steps are plural and have the same period. The impurity region is formed on the riser surface of each of the plurality of macro steps. Thereby, a periodic impurity region can be formed with high accuracy.

  Preferably, the semiconductor device of the present invention further includes another impurity region of the second conductivity type formed on the terrace surface of each of the plurality of macro steps and adjacent to the impurity region. Thereby, a pn junction can be formed by the impurity region and other impurity regions.

  Preferably, the semiconductor device of the present invention further includes a Schottky electrode formed on the surface side of the semiconductor film and an ohmic electrode formed on the side opposite to the surface of the semiconductor film. The current flowing from the Schottky electrode to the ohmic electrode is controlled by the potential difference between the Schottky electrode and the ohmic electrode.

  Thereby, the semiconductor device functions as a Schottky diode, and the breakdown voltage of the Schottky diode can be improved by the pn junction formed by the impurity region and the other impurity regions.

  Preferably, the semiconductor device of the present invention further includes a source electrode and a gate electrode formed on the front surface side of the semiconductor film, and a drain electrode formed on the back surface side of the semiconductor film. The current flowing from the drain electrode to the source electrode is controlled by the voltage applied to the gate electrode.

  Thereby, the semiconductor device functions as a vertical MOSFET, and the breakdown voltage of the vertical MOSFET can be improved by the pn junction formed by the impurity region and the other impurity regions.

  The semiconductor device of the present invention preferably further includes a source electrode, a gate electrode, and a drain electrode formed on the surface of the semiconductor film. The current flowing from the drain electrode to the source electrode is controlled by the voltage applied to the gate electrode. The semiconductor device further includes a first conductivity type drain region formed on the surface of the semiconductor film and in contact with the drain electrode. The impurity region is formed adjacent to the drain region, and has an impurity concentration lower than that of the drain region.

  Thereby, the impurity region serves as an LDD (Lightly Doped Drain) region of the lateral MOSFET, and generation of hot carriers can be suppressed.

  The semiconductor device of the present invention preferably further includes a source electrode, a gate electrode, and a drain electrode formed on the surface of the semiconductor film. The current flowing from the drain electrode to the source electrode is controlled by the voltage applied to the gate electrode. The drain electrode and the semiconductor film are electrically connected through the impurity region.

  Thus, minority carriers are supplied from the impurity region to the semiconductor film when a channel is formed in the semiconductor film. As a result, the threshold voltage of the lateral MOSFET can be lowered.

  Preferably, in the manufacturing method, the step of heat-treating the semiconductor film includes the steps of forming a coating film containing silicon as a main constituent element on the surface of the semiconductor film, and forming the coating film with nitrogen and Heat-treating the semiconductor film in an atmosphere containing at least one of boron.

  Thereby, the state which supplied Si to the surface of the semiconductor film which consists of SiC is realizable with the said coating film. Since the growth in the direction perpendicular to the terrace surface is suppressed at the portion of the semiconductor film where the coating film is formed, the reconfiguration of the semiconductor film along the terrace surface can be promoted.

A method of manufacturing a semiconductor device according to another aspect of the present invention includes a step of forming a semiconductor film made of SiC, a step of forming a groove on a surface of the semiconductor film, and a step of forming the groove, and heat-treating the semiconductor film. Thus, after the step of forming the macro step in which the riser surface and the terrace surface adjacent to each other in the periodic direction are provided on the surface of the semiconductor film and the step of heat treating the semiconductor film, Forming at least one of the first conductivity type impurity region on the riser surface having a higher concentration of the impurity than the terrace surface in a cross-sectional view taken along a section along the periodic direction by injecting at least one of them. I have.

  According to the method of manufacturing a semiconductor device according to another aspect of the present invention, the semiconductor film is heat-treated in a state where silicon is supplied to the surface of the semiconductor film made of SiC, thereby reconfiguring the semiconductor film into an energetically stable surface state. Can be made. As a result, a macro step having a period of 100 nm or more is obtained at the position where the groove is formed on the surface of the semiconductor film, and the length of the flat portion of the macro step can be made longer than before.

  In addition, when at least one of nitrogen and boron is implanted, nitrogen or boron penetrates into the semiconductor film through silicon, and is replaced with carbon atoms constituting the SiC crystal, thereby forming an impurity region. Here, since the riser of the macrostep is an unstable surface compared to the terrace, more nitrogen or boron enters the riser than the terrace. As a result, an impurity region having a higher concentration than the terrace is formed in the riser. As a result, the impurity region can be accurately formed at the desired position by using the desired position as the riser.

  Preferably, in the manufacturing method, in the step of forming the grooves, three or more grooves are formed on the surface of the semiconductor film at equal intervals. Thereby, a plurality of macro steps having the same cycle can be obtained.

  In the present invention, the macro step terrace means the {0001} plane, and the macro step riser means a plane other than the {0001} plane.

  According to the semiconductor device and the manufacturing method thereof of the present invention, an impurity region can be easily formed at a desired position.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
FIG. 1 is a cross-sectional view showing a configuration of a Schottky barrier diode (SBD) according to Embodiment 1 of the present invention. Referring to FIG. 1, SBD 110 as a semiconductor device in the present embodiment includes an n-type SiC substrate 9, an n-type SiC layer 10 as a semiconductor film, an n-type epitaxial layer 12, and an n-type as an impurity region. Impurity regions 11a to 11c, p-type impurity regions 21a to 21c as other impurity regions, a Schottky electrode 41, and an ohmic electrode 42 are provided. An n-type SiC layer 10 is formed on the n-type SiC substrate 9, and an n-type epitaxial layer 12 is formed on the n-type SiC layer 10. N-type impurity regions 11 a to 11 c and p-type impurity regions 21 a to 21 c are formed on the boundary surface between n-type SiC layer 10 and n-type epitaxial layer 12, in other words, on surface 10 a of n-type SiC layer 10. A Schottky electrode 41 is formed on the n-type epitaxial layer 12 on the surface 10a side of the n-type SiC layer 10, and on the back surface 46 of the n-type SiC substrate 9 on the back surface 10b side of the n-type SiC layer 10. An ohmic electrode 42 is formed.

  The SiC crystal constituting the n-type SiC substrate 9 is, for example, such that the (0001) plane or (000-1) is inclined in the range of −30 ° to + 30 ° in the [1-100] direction (that is, −30 °). (With an off angle in the range of ~ + 30 °). Alternatively, the plane orientation of the n-type SiC substrate 9 is inclined by 0.5 ° or more and 56 ° or less with respect to the (0001) plane or the (000-1) plane.

  The n-type SiC layer 10 is a layer that is homoepitaxially grown on the n-type SiC substrate 9 and inherits the crystal structure of the n-type SiC substrate 9. The n-type SiC layer 10 has a plurality of macro steps 1 on its surface 10a. FIG. 2 is an enlarged perspective view showing two macro steps in the n-type SiC layer of FIG. Referring to FIG. 2, when viewed from a microscopic viewpoint, surface 10 a of n-type SiC layer 10 is not flat but has irregularities, and a plurality of macro steps 1 are formed at a constant period. Each of the macro steps 1 includes a crystal plane (riser) 2 and a crystal plane 3 (terrace) that is a crystal plane wider than the crystal plane 2. The crystal plane 3 is, for example, a {0001} plane, and the inclination angle of the crystal plane 3 with respect to the lateral direction in FIG. 2 is the off angle α of the SiC layer 10. The crystal plane 2 is composed of an arbitrary plane other than the {0001} plane. Each length (length of one period) L of the macro step 1 is, for example, 100 nm or more, and the length of the crystal plane 3 is, for example, 2 μm.

  Here, the length of one cycle of the macro step is the length of the macro step 1 in a direction (lateral direction in FIG. 2) along the surface of the n-type SiC layer 10 when viewed from a macro viewpoint. Similarly, the length of the crystal plane is the length of the crystal plane in the direction along the surface of the n-type SiC layer 10 when viewed from a macro viewpoint.

  Each of n-type impurity regions 11a to 11c is formed on the surface of crystal surface 2, and each of p-type impurity regions 21a to 21c is formed on the surface of crystal surface 3. Each of n-type impurity regions 11 a-11 c and each of p-type impurity regions 21 a-21 c are adjacent to each other and are alternately formed along the surface of macro step 1. Each of n-type impurity regions 11a-11c contains a nitrogen atom as an impurity. Regarding the relationship between the concentration of n-type impurity atoms (nitrogen atoms) contained in each of n-type impurity regions 11a to 11c and the concentration of p-type impurity atoms contained in each of p-type impurity regions 21a to 21c, one is the other It is preferable that it is 1/10 or more and 10 times or less. Further, the relationship between the widths of the n-type impurity regions 11a to 11c (lateral length in FIG. 2) and the widths of the p-type impurity regions 21a to 21c (lateral length in FIG. 2) is as follows. It is preferable that one is not less than 1/10 and not more than 10 times the other.

  Referring to FIG. 1, n type epitaxial layer 12 is made of SiC, for example, and is formed to cover surface 10 a of n type SiC layer 10. Here, since the SiC layer 10 and the n-type epitaxial layer 12 are formed in different steps, the SiC crystal has a boundary surface between the n-type SiC layer 10 and the n-type epitaxial layer 12 (the surface of the n-type SiC layer 10). 10a) is discontinuous. Based on the discontinuity of the SiC crystal, the surface 10a of the n-type SiC layer 10 can be specified.

  The Schottky electrode 41 is made of a material that is in Schottky contact with the n-type epitaxial layer 12, and is made of, for example, chromium (Cr), iron (Fe), copper (Cu), molybdenum (Mo), tungsten (W), or the like. It has become. The ohmic electrode 42 is made of a material that makes ohmic contact with the SiC substrate 9, and is made of, for example, nickel (Ni).

  FIG. 3 is a diagram for explaining the operation of the SBD in the first embodiment of the present invention. Referring to FIG. 3, in SBD 110, the current flowing from Schottky electrode 41 to ohmic electrode 42 is controlled by the potential difference between Schottky electrode 41 and ohmic electrode 42. Specifically, when the potential of the Schottky electrode 41 is higher than the potential of the ohmic electrode 42 (when a forward voltage is applied), a current I110 flows between the Schottky electrode 41 and the ohmic electrode 42. At this time, current I110 flows through n-type epitaxial layer 12, n-type impurity regions 11a to 11c, n-type SiC layer 10, and n-type SiC substrate 9.

  On the other hand, when the potential of the Schottky electrode 41 is lower than the potential of the ohmic electrode 42 (when a reverse voltage is applied), the n-type epitaxial layer 12 has a boundary from the boundary between the Schottky electrode 41 and the n-type epitaxial layer 12. A depletion layer D41 extends inside. At the same time, depletion layers Da to Dc extend from each of p type impurity regions 21a to 21c to each of n type impurity regions 11a to 11c, and depletion layers Da to Dc are integrated. As a result, the path of the current I110 is blocked by the depletion layers D41 and Da to Dc, and no current flows between the Schottky electrode 41 and the ohmic electrode 42. That is, since the depletion layers Da to Dc function together with the depletion layer D41 to block the reverse current, the breakdown voltage is improved.

  The structure of the SBD 110 shown in FIG. 1 is an example, and a potential difference between a Schottky electrode formed on the surface side of the semiconductor film made of SiC and an ohmic electrode formed on the side opposite to the surface of the semiconductor film is As long as the current flowing from the Schottky electrode to the ohmic electrode is controlled, the SBD may have another structure.

Subsequently, a method of manufacturing the SBD in the present embodiment will be described with reference to FIGS. First, referring to FIG. 4, n-type SiC substrate 9 made of SiC is prepared. Then, n-type SiC layer 10 is epitaxially grown on n-type SiC substrate 9. The n-type SiC layer 10 is grown by, for example, a CVD (Chemical Vapor Deposition) method using SiH ₄ and C ₃ H ₈ as source gases and nitrogen gas as impurity gases. At this time, many irregularities (steps) exist on the surface 10 a of the n-type SiC layer 10.

  Subsequently, a resist R1 having a predetermined shape is formed on the n-type SiC layer 10, and the n-type SiC layer 10 is etched using the resist R1 as a mask. Thereby, each of the trenches 30 (grooves) having the same depth is formed on the surface 10a of the n-type SiC layer 10 with the same period, and a mesa portion 31 is formed between the trenches 30. Three or more trenches 30 are preferably formed. Thereafter, the resist R1 is removed.

  Next, referring to FIG. 5, a coating film 32 made of silicon is formed so as to cover n-type SiC layer 10. The covering film 32 is formed with a thickness of, for example, 0.1 μm so as to fill the trench 30. Next, n-type SiC layer 10 is heat-treated in a nitrogen atmosphere at a temperature of about 1500 ° C., for example. Thereby, n-type SiC layer 10 is heat-treated in a state where silicon and nitrogen are supplied to surface 10 a of n-type SiC layer 10. As a result, the surface 10a of the n-type SiC layer 10 (the boundary surface between the coating film 32 and the n-type SiC layer 10) is reconfigured, and a plurality of surfaces 10a of the n-type SiC layer 10 are formed on the surface 10a as shown in FIG. The same length macro step 1 is formed. At the same time, n-type impurity regions 11 a to 11 c are formed on each crystal plane 2 of the macro step 1.

  In the present embodiment, the case where the coating film 32 made of silicon is formed has been described. However, instead of forming the coating film 32, Si (silicon) -based gas is introduced into the surface of the SiC layer 10. Thus, silicon may be supplied to the surface of the SiC layer 10. Alternatively, silicon may be supplied to the surface of the SiC layer 10 by applying a liquid containing silicon to the surface of the SiC layer 10. In the present embodiment, the n-type SiC layer 10 is heat-treated in a nitrogen atmosphere. However, the n-type SiC layer 10 may be heat-treated in a state where nitrogen is supplied to at least the surface 10a of the n-type SiC layer 10. .

  Here, how macro step 1 and n-type impurity regions 11a to 11c are formed on the surface of SiC layer 10 by heat treatment will be described with reference to FIGS. 6 to 9 are enlarged views of a portion A in FIG. Referring to FIG. 6, a large number of bunching steps 1a exist on the surface of n-type SiC layer 10 before the heat treatment. Each of the bunching steps 1a includes a crystal face 2a and a crystal face 3a. The crystal plane 3a has a flat portion longer than the crystal plane 2a, and is, for example, a {0001} plane. The crystal plane 3a is a terrace of the bunching step 1a. The crystal plane 2a has a plane orientation other than the {0001} plane. The length P1 in the lateral direction of the crystal plane 3a in the bunching step 1a in the drawing is about 10 nm.

  When the n-type SiC layer 10 is heat-treated with silicon supplied to the surface of the n-type SiC layer 10, the n-type SiC layer 10 does not grow in a direction perpendicular to the crystal plane 3a, and is indicated by a solid arrow in FIG. Thus, it grows in the direction along the crystal plane 3a starting from the crystal plane 2a. At the same time, silicon atoms and carbon atoms on the upper surface of the mesa portion 31 diffuse into the bottom surface of the trench 30 as indicated by the dotted arrows in FIG. As a result, each of the bunching steps 1a converges to form a macro step 1b having a crystal face 3b wider than the crystal face 3a of the bunching step 1a, as shown in FIG. 7, and the bottom face of the trench 30 and the top face of the mesa portion 31. And the height difference (depth of the trench 20) becomes smaller.

  The macro step 1b further grows in the direction along the crystal plane 3b starting from the crystal plane 2b. Further, silicon atoms and carbon atoms on the upper surface of the mesa portion 31 diffuse into the bottom surface of the trench 30. As a result, each of the macro steps 1b is focused, and as shown in FIG. 8, the macro step 1c has a crystal face 3c wider than the crystal face 3b of the macro step 1b, and the trench 30 disappears.

  The macro step 1c further grows in the direction along the crystal plane 3c starting from the crystal plane 2c. As a result, each of the macro steps 1c is focused, and finally, the macro step 1 having a crystal plane 3 wider than the crystal plane 3c of the macro step 1c is obtained as shown in FIG. Since each of the trenches 30 is formed at equal intervals, each of the resulting macrosteps 1 has the same length (one cycle length).

  On the other hand, as indicated by the alternate long and short dash line in FIGS. 6 to 9, nitrogen in the nitrogen atmosphere is taken into the n-type SiC layer 10 through the coating film 32 by the heat treatment, and the crystal plane 2 of the n-type SiC layer 10. N-type impurity regions 11a to 11c are formed. That is, since the silicon crystal constituting the coating film 32 has a property of easily taking in nitrogen, nitrogen in the nitrogen atmosphere is first taken into the coating film 32. As a result, nitrogen is supplied to the surface 10 a of the n-type SiC layer 10. And since the atomic size of nitrogen is close to the atomic size of carbon, nitrogen replaces the carbon site in the SiC crystal. In addition, in the SiC crystal, the crystal planes 2a, 2b, and 2c (that is, the crystal plane 2) are unstable as compared with the crystal planes 3a, 3b, and 3c (that is, the crystal plane 3). For this reason, nitrogen in the coating film 32 is further taken into the n-type SiC layer 10 from the crystal faces 2a, 2b, and 2c. As a result, nitrogen is unevenly distributed on crystal plane 2 of n-type SiC layer 10 to form n-type impurity regions 11a to 11c.

In the above description, the case where the n-type SiC layer 10 is heat-treated at 1500 ° C. has been shown, but the heat treatment temperature of the n-type SiC layer 10 is preferably in the following range. In order to prevent SiC from sublimating and completely decomposing, it is preferably 2545 ° C. or lower. Moreover, in order to suppress to some extent that SiC sublimates in the state of SiC ₂ , Si, Si ₂ C or the like, the temperature is preferably 2000 ° C. or lower. Further, in order to sufficiently suppress the sublimation of SiC in a state such as SiC ₂ , Si, or Si ₂ C, and to facilitate control of the surface morphology of the n-type SiC layer 10, the temperature is preferably 1800 ° C. or lower. . Furthermore, in order to improve the surface morphology of the n-type SiC layer 10, the temperature is preferably 1600 ° C. or lower. On the other hand, in order to grow SiC and promote the formation of macro steps, the temperature is preferably 1300 ° C. or higher. Moreover, in order to make the surface morphology of the n-type SiC layer 10 favorable, it is preferable that it is 1400 degreeC or more.

  Further, the heat treatment time of n-type SiC layer 10 may be longer than 0, and is preferably in the following range. In order to form a comparatively large macro step, it is preferable that it is 10 minutes or more. Further, in order to form a macro step having a length of one cycle of 0.5 μm or more, it is preferably 30 minutes or more. On the other hand, considering the productivity of the semiconductor device, it is preferably 4 hours or less. In order to efficiently form a macro step having a length of one cycle of 1.0 μm or more, it is preferably 2 hours or less. The “heat treatment time” means a time for holding the semiconductor film made of SiC at a predetermined temperature, and the “heat treatment time” does not include the temperature raising time and the temperature lowering time.

  Furthermore, in the above description, the case where the n-type impurity region is formed by heat-treating the semiconductor film with silicon and nitrogen supplied to the surface of the semiconductor film made of SiC has been shown. However, in the present invention, the p-type impurity region may be formed by heat-treating the semiconductor film with silicon and boron supplied to the surface of the semiconductor film. Since the atomic size of boron is close to the atomic size of carbon, when the semiconductor film is heat-treated with boron supplied to the surface of the semiconductor film, the boron replaces the carbon site in the SiC crystal. In addition, the riser in the macro step of the semiconductor film is an unstable surface compared to the terrace. For this reason, boron is taken into the semiconductor film like nitrogen, and is unevenly distributed in the macro step riser. As a result, a p-type impurity region is formed in the riser.

  Next, referring to FIG. 11A, impurity ions such as Al (aluminum) are implanted into the entire surface 10 a of n-type SiC layer 10. As a result, p-type impurity regions 21 a to 21 c are formed on the crystal plane 3. At this time, if the concentration of the p-type impurity in the p-type impurity regions 21a to 21c is adjusted to be lower than the concentration of the nitrogen atoms in the n-type impurity regions 11a to 11c, the n-type impurity regions 11a to 11c will be It is maintained as an n-type region. Thereafter, n-type SiC layer 10 is annealed to activate p-type impurity regions 21a to 21c.

  Moreover, you may perform the process shown to FIG.11 (b) instead of the process shown to Fig.11 (a). Referring to FIG. 11B, a resist R2 is formed so as to cover each of n-type impurity regions 11a to 11c, and impurity ions such as Al are implanted using resist R2 as a mask. Thereafter, resist R2 is removed, and n-type SiC layer 10 is annealed to activate p-type impurity regions 21a to 21c. According to this method, p-type impurity ions can be implanted only into the crystal plane 3.

  Next, referring to FIG. 1, n-type epitaxial layer 12 is formed on surface 10 a of n-type SiC layer 10. Thereafter, Schottky electrode 41 is formed on n-type epitaxial layer 12 using, for example, vapor deposition, and ohmic electrode 42 is formed on back surface 46 of n-type SiC substrate 9. The SBD 110 in the present embodiment is completed through the above steps.

  According to SBD 110 and the manufacturing method thereof in the present embodiment, n-type SiC layer 10 is thermally stabilized by heat-treating n-type SiC layer 10 with silicon supplied to surface 10a of n-type SiC layer 10. Can be reconfigured to a simple surface state. As a result, the macro step 1 having a period of 100 nm or more is obtained at the position where the trench 30 is formed on the surface 10a of the n-type SiC layer 10, and the length of the flat portion of the macro step 1 is increased as compared with the conventional case. Can do.

  In addition, during the heat treatment, nitrogen enters the n-type SiC layer 10 through silicon, and is replaced with carbon constituting the SiC crystal to form an impurity region. Here, since the crystal plane 2 which is the riser of the macro step 1 is an unstable plane as compared with the crystal plane 3 which is the terrace, more nitrogen enters the crystal plane 3 than the crystal plane 2. As a result, n-type impurity regions 11 a to 11 c having a higher concentration than crystal plane 3 are formed on crystal plane 2. As a result, by setting the desired position as the riser, the n-type impurity region can be accurately formed at the desired position.

  In addition, by forming the plurality of macro steps 1 with the same period, and forming each of the n-type impurity regions 11a to 11c on the crystal plane 2 of each of the plurality of macro steps 1, the periodic n-type impurity regions are formed. Can be formed with high accuracy.

  Further, the SBD 110 further includes p-type impurity regions 21a to 21c formed on the crystal planes 3 of each of the plurality of macro steps 1 and adjacent to the n-type impurity regions 11a to 11c, whereby the n-type impurity region 11a. To 11c and p-type impurity regions 21a to 21c can form a pn junction.

  Further, the SBD 110 includes a Schottky electrode 41 formed on the front surface 10a side of the n-type SiC layer 10 and an ohmic electrode 42 formed on the rear surface 10b side of the n-type SiC layer 10, and the ohmic electrode is formed from the Schottky electrode 41. The current I110 that flows to 42 is controlled by the potential difference between the Schottky electrode 41 and the ohmic electrode 42. Thereby, the breakdown voltage of SBD 110 can be improved by the pn junction constituted by each of n type impurity regions 11a to 11c and each of p type impurity regions 21a to 21c.

  In the manufacturing method of the present embodiment, the step of heat-treating n-type SiC layer 10 includes the step of forming coating film 32 made of silicon on surface 10a of n-type SiC layer 10 and the formation of coating film 32. And a step of heat-treating the n-type SiC layer in an atmosphere containing nitrogen. Thereby, the state in which silicon is supplied to the surface 10 a of the n-type SiC layer 10 can be realized by the coating film 32. Since the growth in the direction perpendicular to the terrace surface is suppressed at the location where the coating film 32 in the n-type SiC layer 10 is formed, the reconfiguration of the semiconductor film along the terrace surface can be promoted.

  Furthermore, in the manufacturing method of the present embodiment, three or more trenches 30 are formed in the surface 10a of n-type SiC layer 10 at equal intervals. Thereby, a plurality of macro steps 1 having the same cycle can be obtained.

(Embodiment 2)
FIG. 12 is a cross-sectional view showing the configuration of the vertical MOSFET in the second embodiment of the present invention. Referring to FIG. 12, vertical MOSFET 120 as a semiconductor device in the present embodiment differs from SBD in the first embodiment in the following points. On the surface of n-type epitaxial layer 12, p-type impurity regions 24a and 24b, n-type impurity regions 16a and 16b, and p ⁻ impurity regions 23a and 23b are formed. Each of p ⁻ impurity regions 23 a and 23 b is formed at both ends of n type epitaxial layer 12. Inside each of p ⁻ impurity regions 23 a and 23 b, p type impurity regions 24 a and 24 b and n type impurity regions are formed. Regions 16a and 16b are formed. Each of p-type impurity regions 24a and 24b is formed on the outer side in the figure than each of n-type impurity regions 16a and 16b. On the n-type epitaxial layer 12, source electrodes S1 and S2 and a gate insulating layer 44 are formed. The source electrode S1 is formed on the left side in the drawing and is in contact with the p-type impurity region 24a and the n-type impurity region 16a. The source electrode S2 is formed on the right side in the drawing and is in contact with the p-type impurity region 24b and the n-type impurity region 16b. The gate insulating layer 44 is formed between the source electrode S 1 and the source electrode S 2, and the gate electrode G is formed on the gate insulating layer 44. Gate electrode G faces p ⁻ impurity regions 23 a and 23 b and n-type epitaxial layer 12 with gate insulating layer 44 interposed therebetween. A drain electrode D is formed on the back surface 46 of the n-type SiC substrate 9.

  Since the configuration of the vertical MOSFET other than this is the same as the configuration of the SBD in the first embodiment, the same members are denoted by the same reference numerals, and description thereof will not be repeated.

FIG. 13 is a diagram for explaining the operation of the vertical MOSFET according to the second embodiment of the present invention. Referring to FIG. 13, in vertical MOSFET 120, the current flowing from drain electrode D to source electrodes S <b> 1 and S <b> 2 is controlled by the voltage applied to gate electrode G. Specifically, when a voltage equal to or higher than the threshold voltage is applied to the gate electrode G, channels by minority carriers are formed on the surfaces of the p ⁻ impurity regions 23a and 23b. A current I120 flows to the Current I120 flows through n-type SiC substrate 9, n-type SiC layer 10, n-type impurity regions 11a to 11c, n-type epitaxial layer 12, p ⁻ impurity regions 23a and 23b, and n-type impurity regions 16a and 16b. On the other hand, when the voltage applied to the gate electrode G falls below the threshold voltage, no channel is formed in the p ⁻ impurity regions 23a and 23b, and the current I120 is cut off. At the same time, depletion layers Da to Dc extend from each of p type impurity regions 21a to 21c to each of n type impurity regions 11a to 11c, and depletion layers Da to Dc are integrated. As a result, the path of the current I120 is blocked by the depletion layers Da to Dc. That is, since the depletion layers Da to Dc function to block the reverse current, the breakdown voltage is improved.

  Note that the structure of the vertical MOSFET shown in FIG. 12 is an example, and the current flowing from the drain electrode formed on the back surface side of the semiconductor film made of SiC to the source electrode formed on the front surface side of the semiconductor film is As long as the structure is controlled by the voltage applied to the gate electrode formed on the surface side, the vertical MOSFET may have another structure.

Next, a method for manufacturing the vertical MOSFET in the present embodiment will be described. First, the same manufacturing process as that of the first embodiment shown in FIGS. 4 to 11 is performed. Subsequently, n type epitaxial layer 12 is formed on surface 10 a of n type SiC layer 10. Next, p ⁻ impurity regions 23a and 23b, p-type impurity regions 24a and 24b, and n-type impurity regions 16a and 16b are formed by ion implantation or the like. Thereafter, the source electrodes S1, S2, the gate insulating layer 44, the gate electrode G, and the drain electrode D are formed, and the vertical MOSFET 120 in this embodiment is completed.

  According to the vertical MOSFET 120 and the manufacturing method thereof in the present embodiment, the same effect as in the first embodiment can be obtained. In addition, the MOSFET 120 includes source electrodes S1, S2 and a gate electrode G formed on the surface 10a side of the n-type SiC layer 10, and a drain electrode formed on the back surface side of the n-type SiC layer 10, and the drain electrode D The current I120 flowing from the source electrode S1 to the source electrode S2 is controlled by the voltage applied to the gate electrode G. Thereby, the breakdown voltage of the vertical MOSFET 120 can be improved by the pn junction formed by each of the n-type impurity regions 11a to 11c and each of the p-type impurity regions 21a to 21c.

(Embodiment 3)
14-16 is a figure which shows the structure of horizontal type | mold MOSFET in Embodiment 3 of this invention. 14 is a top perspective view, FIG. 15 is a cross-sectional view taken along line XV-XV in FIG. 14, and FIG. 16 is a cross-sectional view taken along line XVI-XVI in FIG. 14 to 16, a lateral MOSFET 130 as a semiconductor device in the present embodiment includes a p-type SiC substrate 9, a p-type SiC layer 10 as a semiconductor film, and an n ⁺ impurity region 13 as a drain region. An n-type impurity region 14 as an impurity region, an n-type impurity region 15, a gate insulating layer 44, a gate electrode G, a source electrode S, and a drain electrode D.

  A p-type SiC layer 10 is formed on the p-type SiC substrate 9, and a source electrode S, a gate insulating layer 44, and a drain electrode D are formed on the surface 10 a of the p-type SiC layer 10. Referring particularly to FIG. 14, each of source electrode S, gate insulating layer 44, and drain electrode D extends in the horizontal direction in this order from the front side to the back side in FIG. A gate electrode G is formed on the gate insulating layer 44. The gate electrode G extends in the horizontal direction in FIG. 14 so as to cover a part of the gate insulating layer 44.

  P-type SiC layer 10 has the same configuration as n-type SiC layer 10 except that it has a conductivity type opposite to that of n-type SiC layer in the first embodiment. A plurality of macro steps 1 are formed on the surface 10 a of the p-type SiC layer 10 at a constant period, and each of the macro steps 1 is composed of a crystal plane 2 and a crystal plane 3. The n-type impurity region 14 is periodically formed on the crystal plane 2 between the gate electrode G and the source electrode S.

N ⁺ impurity region 13, n type impurity region 14, and n type impurity region 15 are formed on surface 10 a of p type SiC layer 10. The n ⁺ impurity region 13 extends in the horizontal direction in FIG. 14 immediately below the source electrode S and is in contact with the source electrode S. The n-type impurity region 15 extends in the horizontal direction in FIG. 14 immediately below the drain electrode D and is in contact with the drain electrode D. the n-type impurity region 14 has an impurity concentration lower than the impurity concentration of the n ⁺ impurity region 13 is adjacent, and the n ⁺ impurity region 13.

  Since the configuration of the other lateral MOSFET is the same as that of the SBD in the first embodiment, the same reference numerals are given to the same members, and description thereof will not be repeated.

  Referring to FIG. 15, in MOSFET 130, when a voltage equal to or higher than the threshold voltage is applied to gate electrode G, a minority carrier channel (inversion layer) is formed on surface 10 a of p-type SiC layer 10. A current I130 flows from the drain electrode D to the source electrode S. Since the channel thickness increases in proportion to the voltage applied to the gate electrode G, the current flowing from the drain electrode D to the source electrode S increases as the voltage applied to the gate electrode G increases. On the other hand, when the voltage applied to the gate electrode G falls below the threshold voltage, no channel is formed in the p-type SiC layer 10 and the current I130 is cut off. Thus, the current I130 is controlled by the voltage applied to the gate electrode G.

  Here, when a current flows from the drain electrode D to the source electrode S, electrons and holes (hot electrons) with large energy are easily generated in the p-type SiC layer 10. The insulating layer 44 enters the insulating layer 44 and becomes a factor of unstable characteristics such as changing a threshold voltage. Therefore, the n-type impurity region 14 which is a low-concentration impurity region is formed on the crystal plane 2, so that the n-type impurity region 14 serves as an LDD region of the lateral MOSFET 130.

  Note that the structure of the lateral MOSFET 130 shown in FIG. 13 is an example, and other structures may be used.

  Next, a method for manufacturing the MOSFET in the present embodiment will be described. First, p-type SiC layer 10 is formed on p-type SiC substrate 9 using a manufacturing method substantially similar to that of the first embodiment shown in FIGS. 4 and 5, and trenches are formed on surface 10 a of p-type SiC layer 10. 30 and mesa portion 31 are formed. As an impurity gas for growing the p-type SiC layer 10, boron gas or the like is used instead of nitrogen gas. Then, coating film 32 is formed so as to cover p-type SiC layer 10. Next, the p-type SiC layer 10 is heat-treated at a temperature of about 1500 ° C., for example. Thereby, n-type SiC layer 10 is heat-treated in a state where silicon is supplied to surface 10 a of p-type SiC layer 10. As a result, as shown in FIG. 10, a plurality of macro steps 1 having the same length are formed on the surface 10 a of the p-type SiC layer 10. In this embodiment, since heat treatment is not performed in a nitrogen atmosphere, n-type impurity regions 11a to 11c are not formed.

  Next, referring to FIGS. 17 and 18, a resist R <b> 3 is formed on p-type SiC layer 10. As shown in FIG. 17, the resist R3 covers a region other than the region where the n-type impurity region 14 is formed when viewed in a cross section along the crystal plane 2 (a cross section along the XV-XV line in FIG. 14). ing. As shown in FIG. 18, a region corresponding to the n-type impurity region 14 (n-type impurity in FIG. 14) when viewed in a cross-section along the crystal plane 3 (cross-section along the XVI-XVI line in FIG. 14). An area other than the area 14 extending in the horizontal direction) is covered. Then, nitrogen ions are implanted into the p-type SiC layer 10 using the resist R3 as a mask. As a result, nitrogen is unevenly distributed on the crystal plane 2 of the p-type SiC layer 10 and the n-type impurity region 14 is formed based on the same principle as described in the first embodiment. Thereafter, the resist R3 is removed.

Next, referring to FIG. 15, n-type impurity ions are implanted at a predetermined position. Thereby, n ⁺ impurity region 13 and n-type impurity region 15 are formed. Thereafter, the source electrode S, the drain electrode D, the gate insulating layer 44, and the gate electrode G are formed, and the lateral MOSFET 130 in this embodiment is completed.

  According to the lateral MOSFET 130 and the manufacturing method thereof in the present embodiment, the same effect as in the first embodiment can be obtained. In addition, the p-type SiC layer 10 can be reconfigured into an energetically stable surface state by heat-treating the p-type SiC layer 10 with silicon supplied to the surface 10a of the p-type SiC layer 10. As a result, the macro step 1 having a period of 100 nm or more is obtained at the position where the trench 30 is formed on the surface 10a of the p-type SiC layer 10, and the length of the flat portion of the macro step 1 is increased as compared with the conventional case. Can do.

  In addition, when nitrogen is implanted, nitrogen enters the p-type SiC layer 10 through silicon and replaces carbon atoms constituting the SiC crystal, thereby forming an n-type impurity region 14. Here, since the crystal plane 2 which is the riser of the macro step 1 is an unstable plane compared to the crystal plane 3 which is the terrace, more nitrogen or boron enters the crystal plane 2 than the crystal plane 3. To do. As a result, an n-type impurity region 14 having a higher concentration than the crystal plane 3 is formed on the crystal plane 2. As a result, the impurity region can be accurately formed at the desired position by using the desired position as the riser.

The lateral MOSFET 130 includes a source electrode S, a gate electrode G, and a drain electrode D that are formed on the surface 10 a of the p-type SiC layer 10. A current I130 flowing from the drain electrode D to the source electrode S is controlled by a voltage applied to the gate electrode G. The lateral MOSFET 130 further includes an n ⁺ impurity region 13 formed on the surface 10a of the p-type SiC layer 10 and in contact with the drain electrode D. N-type impurity region 14 is formed adjacent to drain electrode D and has an impurity concentration lower than that of n ⁺ impurity region 13. As a result, the n-type impurity region 14 serves as the LDD region of the lateral MOSFET 130, and generation of hot carriers can be suppressed.

(Embodiment 4)
FIGS. 19-21 is a figure which shows the structure of the horizontal MOSFET in Embodiment 4 of this invention. 19 is a top perspective view, FIG. 20 is a cross-sectional view taken along line XX-XX in FIG. 19, and FIG. 21 is a cross-sectional view taken along line XXI-XXI in FIG. Referring to FIGS. 19 to 21, lateral MOSFET 140 in the present embodiment includes a p-type SiC substrate 9, a p-type SiC layer 10 as a semiconductor film, an n-type impurity region 17, and an n-type impurity region 18. A p-type impurity region 25 as an impurity region, a gate insulating layer 44, a gate electrode G, a source electrode S, and a drain electrode D.

  A p-type SiC layer 10 is formed on the p-type SiC substrate 9, and a source electrode S, a gate insulating layer 44, and a drain electrode D are formed on the surface 10 a of the p-type SiC layer 10. Referring particularly to FIG. 19, each of source electrode S, gate insulating layer 44, and drain electrode D extends in the horizontal direction in this order from the front side to the back side in FIG. A gate electrode G is formed on the gate insulating layer 44 and extends in the horizontal direction in FIG.

  A plurality of macro steps 1 are formed on the surface 10 a of the p-type SiC layer 10 at a constant period, and each of the macro steps 1 is composed of a crystal plane 2 and a crystal plane 3. As shown in FIG. 20, the p-type impurity region 25 is formed in a region from just below the source electrode S to just below the gate electrode G in each crystal plane 2. In addition, as shown in FIG. 21, the p-type impurity region 25 is also formed in a part of the region immediately below the source electrode S in the crystal plane 3, whereby the p-type impurity region 25 in each crystal plane 2 is They are electrically connected and integrated. N-type impurity region 17 is formed on surface 10 a of p-type SiC layer 10 on crystal plane 3 and is in contact with source electrode S. N-type impurity region 18 is formed on surface 10a of p-type SiC layer 10 directly below the drain region, and is in contact with drain electrode D. The type impurity region 18 extends in the horizontal direction in FIG. 14 together with the drain electrode D.

  Since the configuration of the other lateral MOSFET is the same as that of the SBD in the first embodiment, the same reference numerals are given to the same members, and description thereof will not be repeated.

  The lateral MOSFET 140 in the present embodiment operates in the same manner as the lateral MOSFET in the third embodiment, and the current I140 flowing from the drain electrode D to the source electrode S is controlled by the voltage applied to the gate electrode G. Here, in the lateral MOSFET 140, the drain electrode D and the p-type SiC layer 10 are electrically connected through the p-type impurity region 25. For this reason, when a voltage equal to or higher than the threshold voltage is applied to the gate electrode G, minority carriers are supplied from the drain electrode D to the surface 10 a of the p-type SiC layer 10. Thereby, a channel is easily formed, and the threshold voltage can be lowered.

  The structure of the lateral MOSFET 140 shown in FIGS. 10 to 21 is an example, and other structures may be used.

  Next, a method for manufacturing the MOSFET in the present embodiment will be described. First, p-type SiC layer 10 is formed on p-type SiC substrate 9 using a manufacturing method substantially similar to that of the first embodiment shown in FIGS. 4 and 5, and trenches are formed on surface 10 a of p-type SiC layer 10. 30 and mesa portion 31 are formed. Then, coating film 32 is formed so as to cover p-type SiC layer 10. Next, the p-type SiC layer 10 is heat-treated at a temperature of about 1500 ° C., for example. Thereby, n-type SiC layer 10 is heat-treated in a state where silicon is supplied to surface 10 a of p-type SiC layer 10. As a result, a plurality of macro steps 1 having the same length are formed on the surface 10 a of the p-type SiC layer 10. On the other hand, in this embodiment, since the heat treatment is not performed in a nitrogen atmosphere, the n-type impurity region is not formed.

  Next, referring to FIGS. 22 and 23, a resist R4 is formed on p-type SiC layer 10. As shown in FIG. 22, the resist R4 covers a region other than the region where the p-type impurity region 25 is formed when viewed in a section along the crystal plane 2 (a section along the line XX-XX in FIG. 19). ing. Further, as shown in FIG. 23, the region other than the region corresponding to the p-type impurity region 25 is covered when viewed in a section along the crystal plane 3 (a section along the XXI-XXI line in FIG. 19). . Then, boron ions are implanted into the p-type SiC layer 10 using the resist R3 as a mask. As a result, boron is unevenly distributed on the crystal plane 2 of p-type SiC layer 10 according to the same principle as described in the first embodiment, and p-type impurity region 25a is formed. Thereafter, the resist R4 is removed.

  Next, referring to FIG. 20, boron ions are implanted into a predetermined position of crystal plane 3. As a result, the p-type impurity regions formed in each of the crystal planes 2 are integrated to form a p-type impurity region 25. Thereafter, the n-type impurity region 17, the n-type impurity region 18, the source electrode S, the drain electrode D, the gate insulating layer 44, and the gate electrode G are formed, and the lateral MOSFET 140 in this embodiment is completed.

  According to the lateral MOSFET 140 and the manufacturing method thereof in the present embodiment, the same effect as in the first embodiment can be obtained. In addition, the lateral MOSFET 140 further includes a source electrode S, a gate electrode G, and a drain electrode D formed on the surface 10 a of the p-type SiC layer 10. A current I140 flowing from the drain electrode D to the source electrode S is controlled by a voltage applied to the gate electrode G. Drain electrode D and p-type SiC layer 10 are electrically connected through p-type impurity region 25. Thus, minority carriers are supplied from the p-type impurity region 25 to the p-type SiC layer 10 when a channel is formed in the p-type SiC layer 10. As a result, the threshold voltage of the lateral MOSFET 140 can be lowered.

  The embodiment disclosed above should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above embodiments but by the scope of claims, and is intended to include all modifications and variations within the scope and meaning equivalent to the scope of claims.

  The present invention is suitable for a semiconductor device including a semiconductor film made of SiC and a manufacturing method thereof.

It is sectional drawing which shows the structure of SBD in Embodiment 1 of this invention. It is a perspective view which expands and shows two macro steps in the n-type SiC layer of FIG. It is a figure for demonstrating operation | movement of SBD in Embodiment 1 of this invention. It is a figure which shows the 1st process of the manufacturing method of SBD in Embodiment 1 of this invention. It is a figure which shows the 2nd process of the manufacturing method of SBD in Embodiment 1 of this invention. FIG. 6 is an enlarged view of a part A in FIG. 5, which is a cross-sectional view showing a first state in which a macro step is formed on the surface of the SiC film. FIG. 6 is an enlarged view of a part A in FIG. 5, and is a cross-sectional view showing a second state in which macro steps are formed on the surface of the SiC film. FIG. 6 is an enlarged view of a part A in FIG. 5, and is a cross-sectional view showing a third state in which macro steps are formed on the surface of the SiC film. FIG. 6 is an enlarged view of a portion A in FIG. 5, and is a cross-sectional view showing a fourth state in which macro steps are formed on the surface of the SiC film. It is a figure which shows the 3rd process of the manufacturing method of SBD in Embodiment 1 of this invention. (A) It is a figure which shows the 4th process of the manufacturing method of SBD in Embodiment 1 of this invention. (B) It is a figure which shows the modification of the 4th process of the manufacturing method of SBD in Embodiment 1 of this invention. It is sectional drawing which shows the structure of the vertical MOSFET in Embodiment 2 of this invention. It is a figure for demonstrating operation | movement of the vertical MOSFET in Embodiment 2 of this invention. It is a top perspective view which shows the structure of the horizontal MOSFET in Embodiment 3 of this invention. It is sectional drawing along the XV-XV line | wire of FIG. It is sectional drawing along the XVI-XVI line of FIG. FIG. 15 is a cross-sectional view taken along line XV-XV in FIG. 14 for describing the method for manufacturing the lateral MOSFET in the third embodiment of the present invention. FIG. 15 is a cross-sectional view taken along line XVI-XVI in FIG. 14 for describing the method for manufacturing the lateral MOSFET in the third embodiment of the present invention. It is a top perspective view which shows the structure of the horizontal MOSFET in Embodiment 4 of this invention. It is sectional drawing along the XX-XX line of FIG. It is sectional drawing along the XXI-XXI line | wire of FIG. FIG. 20 is a cross-sectional view taken along the line XX-XX in FIG. 19 for describing the method for manufacturing the lateral MOSFET in the fourth embodiment of the present invention. FIG. 20 is a cross-sectional view taken along the line XXI-XXI in FIG. 19 for describing the method for manufacturing the lateral MOSFET in the fourth embodiment of the present invention.

Explanation of symbols

1, 1b, 1c macro step, 1a bunching step, 2, 2a-2c, 3, 3a-3c crystal plane, 9 SiC substrate, 10 SiC layer, 10a SiC layer surface, 10b SiC layer back surface, 11a-11c, 14, 15, 16a, 16b, 17, 18 n-type impurity region, 12 n-type epitaxial layer, 13 n ⁺ impurity region, 20 trench, 21 mesa portion, 21a-21c, 24a, 24b, 25, 25a p-type impurity region, 23a , 23b p ^- impurity region 30 trench 31 mesa portion, 32 coating film, 41 Schottky electrode, 42 ohmic electrode, 44 a gate insulating layer, 46 SiC substrate backside, 110 SBD, 120 vertical MOSFET, 130, 140 horizontal MOSFET, D drain electrode, D41 depletion layer, Da to Dc depletion layer, G gate electrode, I 10, I120, I130, I140 current, R1 to R4 resist, S, S1, S2 source electrode, alpha-off angle.

Claims (11)

Comprising a semiconductor film made of silicon carbide,
The semiconductor film has a macro step provided on the surface thereof with a riser surface and a terrace surface adjacent to each other in the periodic direction ,
In a cross-sectional view by a cross section along the periodic direction, the first conductivity type impurity region formed on the entire riser surface of the macro step and the second conductivity type formed on the entire terrace surface of the macro step. And other impurity regions ,
The semiconductor device, wherein the impurity region includes at least one of a nitrogen atom and a boron atom.   2. The semiconductor device according to claim 1, wherein the macro steps are plural and have the same period, and the impurity region is formed on a riser surface of each of the macro steps.   The semiconductor device according to claim 2, further comprising another impurity region of a second conductivity type formed on a terrace surface of each of the plurality of macro steps and adjacent to the impurity region. A Schottky electrode formed on the surface side of the semiconductor film;
An ohmic electrode formed on the opposite side of the semiconductor film from the surface;
The semiconductor device according to claim 3, wherein a current flowing from the Schottky electrode to the ohmic electrode is controlled by a potential difference between the Schottky electrode and the ohmic electrode. A source electrode and a gate electrode formed on the surface side of the semiconductor film;
A drain electrode formed on the back side of the semiconductor film;
The semiconductor device according to claim 3, wherein a current flowing from the drain electrode to the source electrode is controlled by a voltage applied to the gate electrode. Further comprising a source electrode, a gate electrode, and a drain electrode formed on the semiconductor film surface;
A current flowing from the drain electrode to the source electrode is controlled by a voltage applied to the gate electrode;
A drain region of a first conductivity type formed on the surface of the semiconductor film and in contact with the drain electrode;
The semiconductor device according to claim 1, wherein the impurity region is formed adjacent to the drain region and has an impurity concentration lower than that of the drain region. A source electrode, a gate electrode, and a drain electrode formed on the semiconductor film surface;
A current flowing from the drain electrode to the source electrode is controlled by a voltage applied to the gate electrode;
The semiconductor device according to claim 1, wherein the drain electrode and the semiconductor film are electrically connected through the impurity region. Forming a semiconductor film made of silicon carbide;
Forming a groove in the semiconductor film surface;
After the step of forming the groove, a step of forming a macro step in which a surface of the semiconductor film is provided with a riser surface and a terrace surface adjacent to each other in a periodic direction by heat-treating the semiconductor film,
And silicon in the surface of the semiconductor film, by which the semiconductor film is Ru is heat treated while supplying at least one of the impurities of the nitrogen and boron, the terrace surface in the cross-sectional view according to a section along the periodic direction A method of manufacturing a semiconductor device, wherein a first conductivity type impurity region having a higher impurity concentration is formed on the riser surface .   The step of heat-treating the semiconductor film includes a step of forming a coating film containing silicon as a main component on the surface of the semiconductor film and a step of forming the coating film, and at least one of nitrogen and boron. The method for manufacturing a semiconductor device according to claim 8, further comprising a step of heat-treating the semiconductor film in an atmosphere including any one of them. Forming a semiconductor film made of silicon carbide;
Forming a groove in the semiconductor film surface;
After the step of forming the groove, a step of forming a macro step in which a surface of the semiconductor film is provided with a riser surface and a terrace surface adjacent to each other in a periodic direction by heat-treating the semiconductor film ;
After the step of heat-treating the semiconductor film, by injecting at least one of nitrogen and boron into the surface of the semiconductor film , compared to the terrace surface in a cross-sectional view by a section along the periodic direction Forming a first conductivity type impurity region having a high concentration of the impurity on the surface of the riser .   11. The method of manufacturing a semiconductor device according to claim 8, wherein, in the step of forming the groove, three or more grooves are formed on the surface of the semiconductor film at equal intervals.

Images