JP4927146B2 - 電子部品実装構造の製造方法 - Google Patents
電子部品実装構造の製造方法 Download PDFInfo
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- JP4927146B2 JP4927146B2 JP2009241253A JP2009241253A JP4927146B2 JP 4927146 B2 JP4927146 B2 JP 4927146B2 JP 2009241253 A JP2009241253 A JP 2009241253A JP 2009241253 A JP2009241253 A JP 2009241253A JP 4927146 B2 JP4927146 B2 JP 4927146B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Production Of Multi-Layered Print Wiring Board (AREA)
Description
次に、本発明の第1実施形態の電子部品実装構造の製造方法を説明する。図2〜図4は本発明の第1実施形態の電子部品実装構造の製造方法を示す断面図である。第1実施形態の電子部品実装構造の製造方法は、図2(a)に示すように、まず、ビルドアップ配線基板を製造するためのベース基板24を用意する。このベース基板24は樹脂などの絶縁性材料から構成されている。またベース基板24にはスルーホール24aが設けられていて、このスルーホール24aにはその内面にベース基板24上の第1配線パターン28に繋がるスルーホールめっき層24bが形成され、その孔は樹脂24cで埋め込まれている。
図5及び図6は本発明の第2実施形態の電子部品実装構造の製造方法を示す断面図である。第2実施形態が第1実施形態と異なる点は、半導体チップを第1樹脂膜に埋め込んで実装した後に第2樹脂膜を形成せずに半導体チップ20上に直接第3配線パターンを形成することにある。第2実施形態では、第1実施形態と同様な工程についてはその詳しい説明を省略する。
図7及び図8は本発明の第3実施形態の電子部品実装構造の製造方法を示す断面図である。第3実施形態が第1実施形態と異なる点は、半導体チップをフェイスダウンで樹脂膜の中に埋め込んでフリップチップ実装することにある。第3実施形態において、第1実施形態と同一工程についてはその詳しい説明を省略する。
図9及び図10は本発明の第4実施形態の電子部品実装構造の製造方法を示す断面図である。第4実施形態が第3実施形態と異なる点は、第3実施形態と同様な方法により半導体チップを実装した後に、半導体チップ上に絶縁膜を形成することにある。これにより、配線パターンを半導体チップ上の領域にも引き回しできるようになる。第4実施形態では、第1及び第3実施形態と同一工程についての詳しい説明を省略する。
図11〜図13は本発明の第5実施形態の電子部品実装構造の製造方法を順に示す断面図である。前述した第3及び第4実施形態では、樹脂膜を排斥して半導体チップのバンプを配線パターンに接合するので、半導体チップのバンプと配線パターンとの間に僅かな樹脂が介在するおそれがあり、電気接続の十分な信頼性が得られない場合が想定される。第5実施形態では、そのような不具合を解消することができる。なお、第5実施形態では、第1及び第3実施形態と同一工程についてはその詳しい説明を省略する。
このため、本実施形態では、半導体チップ20bのバンプ23がはんだバンプである場合は、バンプ23をリフロー・硬化させて変形させることによりその隙間が埋め込まれるようにする。その後に、130〜200℃の温度雰囲気で熱処理を行うことにより、第1樹脂膜32aを硬化させる。
Claims (3)
- 配線パターンを備えた配線基板の上に該配線基板の一面側を覆うように未硬化の樹脂膜を形成する工程と、
素子形成面に接続端子と該接続端子を露出させる開口部をもつパシベーション膜とを備えた電子部品を、該接続端子を上側にして前記電子部品の背面と前記配線基板との間に前記樹脂膜が介在するように、前記未硬化の樹脂膜の中に埋め込む工程と、
前記樹脂膜を熱処理して硬化させることにより絶縁膜を得る工程と、
前記配線パターン上の前記絶縁膜の所定部にビアホールを形成する工程と、
前記ビアホールを介して前記配線パターンに接続されると共に、前記開口部を介して前記接続端子に接続される上側配線パターンを、前記パシベーション膜と前記絶縁膜とに跨った状態で前記絶縁膜及び前記電子部品上に接触させて形成する工程とを有することを特徴とする電子部品実装構造の製造方法。 - 前記電子部品を前記未硬化の樹脂膜に埋め込む工程において、
前記電子部品の素子形成面と前記未硬化の樹脂膜の上面とが同一の高さになるように、前記電子部品を埋め込むことを特徴とする請求項1に記載の電子部品実装構造の製造方法。 - 配線パターンを備えた配線基板の上に該配線基板の一面側を覆うように未硬化の樹脂膜を形成する工程と、
素子形成面に接続端子を備え、前記素子形成面と反対面の背面に絶縁膜が形成された電子部品を、該接続端子を下側にして前記電子部品の側面が埋め込まれるように、前記未硬化の樹脂膜の中に埋め込むと共に、前記接続端子を前記配線パターンに接合する工程と、
前記樹脂膜を熱処理して硬化させることにより層間絶縁膜を得る工程と、
前記層間絶縁膜を得る工程の後に、前記層間絶縁膜の所定部に前記配線パターンが露出するようにビアホールを形成する工程と、
前記ビアホールを介して前記配線パターンに接続された上側配線パターンを前記層間絶縁膜上及び前記電子部品の背面の前記絶縁層上に形成する工程とを有し、
前記電子部品の背面に形成された前記絶縁膜と前記層間絶縁層の上面とは、略同一の高さになって平坦化されることを特徴とする電子部品実装構造の製造方法。
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JP2002176267A (ja) * | 2000-09-26 | 2002-06-21 | Toshiba Corp | 電子部品、回路装置とその製造方法並びに半導体装置 |
JP3881193B2 (ja) * | 2001-06-13 | 2007-02-14 | 松下電器産業株式会社 | 電子部品実装済部品の製造方法、電子部品実装済部品、電子部品実装済完成品の製造方法及び電子部品実装済完成品 |
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