JP4921080B2 - メモリ制御回路及びメモリ制御方法 - Google Patents

メモリ制御回路及びメモリ制御方法 Download PDF

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Publication number
JP4921080B2
JP4921080B2 JP2006237727A JP2006237727A JP4921080B2 JP 4921080 B2 JP4921080 B2 JP 4921080B2 JP 2006237727 A JP2006237727 A JP 2006237727A JP 2006237727 A JP2006237727 A JP 2006237727A JP 4921080 B2 JP4921080 B2 JP 4921080B2
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write data
data
memory
burst
read
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JP2006237727A
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Japanese (ja)
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JP2008059449A (ja
JP2008059449A5 (enExample
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武史 鈴木
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Canon Inc
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Canon Inc
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Priority to JP2006237727A priority Critical patent/JP4921080B2/ja
Priority to US11/840,912 priority patent/US7755951B2/en
Priority to CN2007101476782A priority patent/CN101135951B/zh
Publication of JP2008059449A publication Critical patent/JP2008059449A/ja
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JP2006237727A 2006-09-01 2006-09-01 メモリ制御回路及びメモリ制御方法 Expired - Fee Related JP4921080B2 (ja)

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Application Number Priority Date Filing Date Title
JP2006237727A JP4921080B2 (ja) 2006-09-01 2006-09-01 メモリ制御回路及びメモリ制御方法
US11/840,912 US7755951B2 (en) 2006-09-01 2007-08-17 Data output apparatus, memory system, data output method, and data processing method
CN2007101476782A CN101135951B (zh) 2006-09-01 2007-08-31 数据输出设备和方法、存储器系统、数据处理方法

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JP2006237727A JP4921080B2 (ja) 2006-09-01 2006-09-01 メモリ制御回路及びメモリ制御方法

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JP2008059449A JP2008059449A (ja) 2008-03-13
JP2008059449A5 JP2008059449A5 (enExample) 2009-10-08
JP4921080B2 true JP4921080B2 (ja) 2012-04-18

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CN (1) CN101135951B (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012014493A (ja) * 2010-07-01 2012-01-19 Sony Corp メモリ管理装置、メモリ管理方法及びプログラム
JP5629392B2 (ja) * 2011-12-22 2014-11-19 インターナショナル・ビジネス・マシーンズ・コーポレーションＩｎｔｅｒｎａｔｉｏｎａｌ Ｂｕｓｉｎｅｓｓ Ｍａｃｈｉｎｅｓ Ｃｏｒｐｏｒａｔｉｏｎ 記憶装置アクセス・システム
JP5962258B2 (ja) 2012-06-29 2016-08-03 富士通株式会社 データ変換方法、データ変換装置およびデータ変換プログラム
JP5778640B2 (ja) * 2012-08-10 2015-09-16 日本電信電話株式会社 フレーム検索処理装置および方法
CN102937935A (zh) * 2012-09-04 2013-02-20 邹粤林 一种固态存储系统及控制器、提高闪存芯片寿命的方法
JP6234247B2 (ja) * 2014-01-28 2017-11-22 キヤノン株式会社 画像処理装置、画像処理方法
JP6414497B2 (ja) * 2015-03-25 2018-10-31 アイシン・エィ・ダブリュ株式会社 メモリコントローラ
KR102491579B1 (ko) * 2016-01-22 2023-01-25 삼성전자주식회사 메모리 장치, 메모리 모듈 및 메모리 시스템
CN107402714B (zh) * 2016-05-20 2020-06-02 中芯国际集成电路制造(上海)有限公司 用于串行闪存的写操作的方法和串行闪存
CN109346116B (zh) * 2018-09-12 2020-10-09 上海华力集成电路制造有限公司 Sram防sso的输出自调节电路

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08115254A (ja) * 1994-10-14 1996-05-07 Sony Corp メモリのアクセス方法及びメモリコントロール装置
US6813700B2 (en) * 2001-06-11 2004-11-02 Fujitsu Limited Reduction of bus switching activity using an encoder and decoder
US7133324B2 (en) * 2003-12-24 2006-11-07 Samsung Electronics Co., Ltd. Synchronous dynamic random access memory devices having dual data rate 1 (DDR1) and DDR2 modes of operation and methods of operating same

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CN101135951B (zh) 2012-10-17
JP2008059449A (ja) 2008-03-13
CN101135951A (zh) 2008-03-05

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