JP4902917B2 - 隣接するボンディングパッドのコード化による配置を備えた半導体デバイス構成 - Google Patents

隣接するボンディングパッドのコード化による配置を備えた半導体デバイス構成 Download PDF

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Publication number
JP4902917B2
JP4902917B2 JP2001509083A JP2001509083A JP4902917B2 JP 4902917 B2 JP4902917 B2 JP 4902917B2 JP 2001509083 A JP2001509083 A JP 2001509083A JP 2001509083 A JP2001509083 A JP 2001509083A JP 4902917 B2 JP4902917 B2 JP 4902917B2
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Japan
Prior art keywords
die
pad
lead
placement
target
Prior art date
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Expired - Lifetime
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JP2001509083A
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English (en)
Japanese (ja)
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JP2003504874A5 (enExample
JP2003504874A (ja
Inventor
フィリップ、シルベストル
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of JP2003504874A5 publication Critical patent/JP2003504874A5/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6605—High-frequency electrical connections
    • H01L2223/6611—Wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP2001509083A 1999-07-07 2000-07-05 隣接するボンディングパッドのコード化による配置を備えた半導体デバイス構成 Expired - Lifetime JP4902917B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/348,793 US6246107B1 (en) 1999-07-07 1999-07-07 Semiconductor device arrangement having configuration via adjacent bond pad coding
US09/348,793 1999-07-07
PCT/US2000/018435 WO2001004952A1 (en) 1999-07-07 2000-07-05 Semiconductor device arrangement having configuration via adjacent bond pad coding

Publications (3)

Publication Number Publication Date
JP2003504874A JP2003504874A (ja) 2003-02-04
JP2003504874A5 JP2003504874A5 (enExample) 2010-04-22
JP4902917B2 true JP4902917B2 (ja) 2012-03-21

Family

ID=23369559

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001509083A Expired - Lifetime JP4902917B2 (ja) 1999-07-07 2000-07-05 隣接するボンディングパッドのコード化による配置を備えた半導体デバイス構成

Country Status (6)

Country Link
US (1) US6246107B1 (enExample)
EP (1) EP1118121B1 (enExample)
JP (1) JP4902917B2 (enExample)
AU (1) AU5786900A (enExample)
DE (1) DE60043922D1 (enExample)
WO (1) WO2001004952A1 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6798076B2 (en) * 1999-12-21 2004-09-28 Intel Corporation Method and apparatus for encoding information in an IC package
US7088002B2 (en) * 2000-12-18 2006-08-08 Intel Corporation Interconnect
US6903448B1 (en) 2002-11-12 2005-06-07 Marvell International Ltd. High performance leadframe in electronic package
US7119448B1 (en) * 2004-10-18 2006-10-10 National Semiconductor Corporation Main power inductance based on bond wires for a switching power converter
DE102006044016A1 (de) * 2006-09-15 2008-04-03 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Stapelbare Funktionsschicht für ein modulares mikroelektronisches System
DE102007040871A1 (de) * 2007-08-29 2009-03-12 Osram Gesellschaft mit beschränkter Haftung Verbindungselement
US7825527B2 (en) * 2008-06-13 2010-11-02 Altera Corporation Return loss techniques in wirebond packages for high-speed data communications
US8829685B2 (en) * 2009-03-31 2014-09-09 Semiconductor Components Industries, Llc Circuit device having funnel shaped lead and method for manufacturing the same
TWI607548B (zh) * 2016-02-05 2017-12-01 Au Optronics Corp 自發光型顯示器

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3478229A (en) 1968-04-29 1969-11-11 American Micro Syst Multifunction circuit device
US3648116A (en) 1970-09-17 1972-03-07 Rca Corp Multicircuit hybrid module and method for making
JPS59165439A (ja) * 1983-03-09 1984-09-18 Fujitsu Ltd 半導体装置
US4558345A (en) 1983-10-27 1985-12-10 Rca Corporation Multiple connection bond pad for an integrated circuit device and method of making same
KR960013630B1 (ko) * 1986-06-30 1996-10-10 페어차일드 세미콘덕터 코퍼레이션 집적회로에서의 접지 변동 감소 장치
US5066831A (en) 1987-10-23 1991-11-19 Honeywell Inc. Universal semiconductor chip package
US5161124A (en) 1988-10-27 1992-11-03 Texas Instruments Incorporated Bond programmable integrated circuit
NL9100321A (nl) 1991-02-22 1992-09-16 Tulip Computers International Inrichting voor het op n verschillende manieren met bedradingssporen op een printplaat verbinden van de aansluitpennen van een in een dual-in-line (dil)-behuizing ondergebrachte geintegreerde schakeling.
JPH04307943A (ja) 1991-04-05 1992-10-30 Mitsubishi Electric Corp 半導体装置
JP2681427B2 (ja) 1992-01-06 1997-11-26 三菱電機株式会社 半導体装置
JPH05215504A (ja) 1992-02-05 1993-08-24 Mitsubishi Electric Corp 位置検出装置
US5264664A (en) 1992-04-20 1993-11-23 International Business Machines Corporation Programmable chip to circuit board connection
JPH06310558A (ja) 1993-04-20 1994-11-04 Sanyo Electric Co Ltd Ｉｃチップ
JPH07202111A (ja) * 1993-12-28 1995-08-04 Toshiba Corp 樹脂封止型半導体装置用リ−ドフレ−ム及び樹脂封止型半導体装置
US5698903A (en) 1995-05-09 1997-12-16 United Memories, Inc. Bond pad option for integrated circuits
US5646451A (en) 1995-06-07 1997-07-08 Lucent Technologies Inc. Multifunctional chip wire bonds
US5675178A (en) 1995-11-22 1997-10-07 Cypress Semiconductor Corp. No-bond integrated circuit inputs
US5701234A (en) 1995-12-06 1997-12-23 Pacesetter, Inc. Surface mount component for selectively configuring a printed circuit board and method for using the same
US5703759A (en) 1995-12-07 1997-12-30 Xilinx, Inc. Multi-chip electrically reconfigurable module with predominantly extra-package inter-chip connections
US5754879A (en) 1996-09-23 1998-05-19 Motorola, Inc. Integrated circuit for external bus interface having programmable mode select by selectively bonding one of the bond pads to a reset terminal via a conductive wire
US5805428A (en) 1996-12-20 1998-09-08 Compaq Computer Corporation Transistor/resistor printed circuit board layout
US6097098A (en) * 1997-02-14 2000-08-01 Micron Technology, Inc. Die interconnections using intermediate connection elements secured to the die face
CA2232843C (en) * 1997-03-25 2002-03-12 Koichi Haruta Plastic package, semiconductor device, and method of manufacturing plastic package
JP3545200B2 (ja) * 1997-04-17 2004-07-21 シャープ株式会社 半導体装置
JPH1131777A (ja) * 1997-07-11 1999-02-02 Mitsubishi Electric Corp リードフレームおよび半導体装置とその製造方法
US6008533A (en) * 1997-12-08 1999-12-28 Micron Technology, Inc. Controlling impedances of an integrated circuit
US5914529A (en) * 1998-02-20 1999-06-22 Micron Technology, Inc. Bus bar structure on lead frame of semiconductor device package

Also Published As

Publication number Publication date
DE60043922D1 (de) 2010-04-15
WO2001004952A1 (en) 2001-01-18
AU5786900A (en) 2001-01-30
EP1118121A1 (en) 2001-07-25
JP2003504874A (ja) 2003-02-04
EP1118121B1 (en) 2010-03-03
US6246107B1 (en) 2001-06-12

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