JP4884199B2 - ネットワークの時間同期化方法 - Google Patents
ネットワークの時間同期化方法 Download PDFInfo
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- JP4884199B2 JP4884199B2 JP2006345240A JP2006345240A JP4884199B2 JP 4884199 B2 JP4884199 B2 JP 4884199B2 JP 2006345240 A JP2006345240 A JP 2006345240A JP 2006345240 A JP2006345240 A JP 2006345240A JP 4884199 B2 JP4884199 B2 JP 4884199B2
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- 238000000034 method Methods 0.000 claims description 16
- 230000001934 delay Effects 0.000 claims description 7
- 238000004891 communication Methods 0.000 description 23
- 238000005259 measurement Methods 0.000 description 11
- 238000009826 distribution Methods 0.000 description 7
- 230000009471 action Effects 0.000 description 5
- 230000004044 response Effects 0.000 description 4
- 238000012546 transfer Methods 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000002441 reversible effect Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 238000012937 correction Methods 0.000 description 2
- 230000007613 environmental effect Effects 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 230000002123 temporal effect Effects 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/14—Time supervision arrangements, e.g. real time clock
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
- H04J3/0667—Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
- H04L43/0852—Delays
- H04L43/0858—One way delays
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/16—Threshold monitoring
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/10—Active monitoring, e.g. heartbeat, ping or trace-route
- H04L43/106—Active monitoring, e.g. heartbeat, ping or trace-route using time related information in packets, e.g. by adding timestamps
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Environmental & Geological Engineering (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Description
る不要な調節が生じないように、ネットワークの時間同期化から遅延変動を除去する技法
が開示される。この技法によるネットワーク時間同期化を有するシステムは、通信ネットワークを介してタイミングパケットを送信する第1の装置と、通信ネットワークを介してタイミングパケットを受信すると共に、タイミングパケットに応答してネットワーク遅延を判定し、ネットワーク遅延が調節可能な閾値を超える場合に、タイミングパケットを破棄する第2の装置と、を備える。調節可能な閾値により、時間的な同期を維持するために十分な遅延計測の回数に対して、遅延変動の観点において遅延計測の品質をバランスさせることができる。
SMD=T4−(T3−OFFSET)
42 時間同期化回路
Claims (2)
- 最小ネットワーク遅延δと、調節可能な閾値εを用いたネットワークの時間同期化方法において、
タイミングパケットと関連したネットワーク遅延を計測する段階と、
前記ネットワーク遅延が前記最小ネットワーク遅延δと前記調節可能な閾値εとの和を上回っている場合には、前記タイミングパケットを破棄する段階と、
前記ネットワーク遅延が前記最小ネットワーク遅延δを中心として前記調節可能な閾値の±εの範囲内にある場合には、前記最小ネットワーク遅延δを、前記最小ネットワーク遅延δの値と前記ネットワーク遅延との平均値に設定する段階と、
前記ネットワーク遅延が前記最小ネットワーク遅延δから前記調節可能な閾値εを差し引いた値より下回っている場合には、前記最小ネットワーク遅延δを前記ネットワーク遅延に設定する段階と、
キューイング遅延を伴わない予想ネットワーク遅延ジッタに、前記タイミングパケットが辿る経路中のキューによる一連の遅延要素のうちの一部の遅延要素の遅延を導入して前記調節可能な閾値εを調節し、前記調節可能な閾値εを使用してタイミングパケットの破棄を制御する段階と
を有することを特徴とする方法。 - 前記タイミングパケットの破棄を制御する段階は、
前記ネットワーク遅延の複数の推定値を判定する段階と、
それぞれの推定値に対して重みを割り当てる段階と、
を有することを特徴とする請求項1に記載の方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/317,711 | 2005-12-23 | ||
US11/317,711 US20070147435A1 (en) | 2005-12-23 | 2005-12-23 | Removing delay fluctuation in network time synchronization |
Publications (3)
Publication Number | Publication Date |
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JP2007174676A JP2007174676A (ja) | 2007-07-05 |
JP2007174676A5 JP2007174676A5 (ja) | 2010-01-21 |
JP4884199B2 true JP4884199B2 (ja) | 2012-02-29 |
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JP2006345240A Active JP4884199B2 (ja) | 2005-12-23 | 2006-12-22 | ネットワークの時間同期化方法 |
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US (1) | US20070147435A1 (ja) |
EP (1) | EP1802015A1 (ja) |
JP (1) | JP4884199B2 (ja) |
CN (1) | CN1997027A (ja) |
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2005
- 2005-12-23 US US11/317,711 patent/US20070147435A1/en not_active Abandoned
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2006
- 2006-11-15 EP EP06255844A patent/EP1802015A1/en not_active Withdrawn
- 2006-12-22 CN CNA200610170653XA patent/CN1997027A/zh active Pending
- 2006-12-22 JP JP2006345240A patent/JP4884199B2/ja active Active
Also Published As
Publication number | Publication date |
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JP2007174676A (ja) | 2007-07-05 |
US20070147435A1 (en) | 2007-06-28 |
CN1997027A (zh) | 2007-07-11 |
EP1802015A1 (en) | 2007-06-27 |
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