JP4882983B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device in which a trench is formed on the surface of a semiconductor substrate and a current path is provided in the trench or in the vicinity of a sidewall or bottom of the trench.

  As a semiconductor device having a current path inside a trench formed in a semiconductor substrate or near the side wall or bottom of the trench, a trench structure MOSFET (hereinafter referred to as a trench MOSFET), IGBT (hereinafter referred to as a trench IGBT) or There is a lateral trench power MISFET (hereinafter referred to as TLPM). FIG. 38 shows a plan shape of a conventional trench pattern in these semiconductor devices. In FIG. 38, reference numeral 11 denotes a semiconductor substrate, and reference numeral 12 denotes a trench. As shown in FIG. 38, the width of the conventional trench pattern is uniform up to the trench end 13. A cross-sectional structure of a conventional trench MOSFET having such a trench pattern is shown in FIGS.

  FIG. 39 is a diagram showing a cross-sectional structure of the trench MOSFET taken along a cutting line M-M ′ in FIG. 38. As shown in FIG. 39, p-type channel region 103 is formed in the surface layer of n-type drift layer 102 on n + -type drain layer 101. An n-type source region 104 is formed in the surface layer of the p-type channel region 103. Then, a trench 100 that reaches the drift layer 102 from the surface of the source region 104 through the channel region 103 is formed. A gate oxide film 105 is formed along the inner surface of the trench 100, and further, the inside thereof is filled with a gate electrode 106 made of polycrystalline silicon. A source electrode 108 is stacked on the surface of the source region 104. The source electrode 108 and the gate electrode 106 are insulated by an interlayer insulating film 107. A drain electrode 109 is provided on the back surface of the drain layer 101.

  FIG. 40 is a diagram showing a cross-sectional structure of the trench MOSFET taken along a cutting line L-L ′ in FIG. 38. As shown in FIG. 40, the terminal portion 110 of the trench 100 is a lead portion for the gate electrode 106. That is, the gate electrode 106 is pulled out to the substrate surface at the terminal portion 110 and is extended onto the field oxide film 121 along the substrate surface. On the field oxide film 121, the gate electrode 106 is connected to the gate metal electrode 123 through a contact hole 122 opened in the interlayer insulating film 107.

  However, if the trench 100 is formed by dry etching as usual, the terminal corner portion 111 (see FIG. 40) of the trench 100 is pointed, so that the thickness of the gate oxide film 105 here becomes thinner than other portions. For this reason, the electric field concentrates on the terminal corner 111, and there has been a problem that the breakdown voltage of the device may be lowered.

  The present invention has been made to solve the above-described problem, and a semiconductor device capable of preventing electric field concentration at the terminal corner portion of the trench and thereby preventing a decrease in breakdown voltage of the device, and such a configuration. An object of the present invention is to provide a method for manufacturing the semiconductor device without increasing the number of steps.

  In order to achieve the above object, according to the present invention, a current path is provided in a trench formed in a semiconductor substrate, in the vicinity of a sidewall or bottom, and a part or all of the bottom surface of the trench, or a sidewall of the trench. In a semiconductor device in which a gate electrode is provided through a gate insulating film along part or all of the trench, the width of the outermost trench among the intersecting trenches is narrower than the width of the inner trench It is characterized by. The outermost trench is shallower than the inner trench.

  In addition, in a semiconductor device having a trench such as a trench MOSFET trench IGBT or TLPM, the vicinity of the end of the trench has a tapered planar shape that narrows toward the end portion, and a shape that becomes shallow toward the end portion. To do. According to the present invention, the vicinity of the trench termination becomes shallow toward the termination and the trench termination corner is rounded, so that the generation of singular points in the gate termination film and the gate electrode at the trench termination corner is suppressed.

  In addition, the present invention is characterized in that the tapered portion of the semiconductor device in which the portion near the trench termination is tapered as described above is filled with a gate insulating film. According to the present invention, the occurrence of singular points in the gate insulating film and the gate electrode at the trench terminal corner is suppressed, and the vicinity of the trench terminal is covered with the thick gate insulating film.

  In addition, the semiconductor device manufacturing method according to the present invention includes forming a tapered trench in the vicinity of the end of the trench, depositing a gate insulating film in the trench, performing isotropic etching, and then forming the tapered portion. The gate insulating film covering the other part in the trench is made to have a desired thickness while being filled with the gate insulating film. According to the present invention, the portion near the end of the trench is covered with the thick gate insulating film without adding the number of steps.

  According to the present invention, since the generation of singular points in the gate insulating film and the gate electrode is suppressed at the trench termination corner portion, electric field concentration at the trench termination corner portion can be prevented, and the breakdown voltage of the device can be prevented from being lowered. Can do. Further, this semiconductor device can be obtained without increasing the number of steps.

  In addition, according to another invention, the occurrence of singular points in the gate insulating film and the gate electrode is suppressed in the trench terminal corner, and the trench terminal corner is covered with the thick gate insulating film, so that the trench terminal corner As a result, it is possible to more effectively prevent the concentration of the electric field on the device, so that it is possible to further prevent the breakdown voltage of the device from decreasing. In addition, the semiconductor device having such a configuration can be manufactured without increasing the number of steps.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
Embodiment 1 FIG.
FIG. 1 is a schematic schematic view showing a first example of a planar shape of a portion near a trench termination of a semiconductor device according to the present invention, and FIG. 2 is a cross-sectional shape of a trench along a cutting line AA ′ in FIG. FIG. 1 and 2, reference numeral 21 is a semiconductor substrate, and the shaded portion indicated by reference numeral 22 is a trench. As shown in FIG. 1, in the first example, the planar shape of the trench 22 is a bottleneck type in which the width of the end vicinity portion 23 of the trench 22 is one step narrower than the width of the trunk portion 24 closer to the center. It has become. Such a planar trench 22 is formed by forming a mask oxide film having a pattern corresponding to this shape on a semiconductor substrate and performing well-known dry etching. In the formed trench 22, the end vicinity portion 23 is shallower than the body portion 24 as shown in FIG. 2.

  FIG. 37 is a schematic diagram showing a cross section of a trench formed by dry etching while changing the trench width. In the figure, reference numeral 1 is a semiconductor substrate, reference numerals 2a, 2b and 2c are trenches, and reference numeral 3 is a mask oxide film. As shown in FIG. 37, in dry etching, a trench having a wide trench width (for example, trench 2a) is etched deeply on the pattern, and a trench having a narrow trench width (for example, trench 2c) is etched shallowly on the pattern. Therefore, as shown in FIGS. 1 and 2, the end vicinity portion 23 having a narrow trench width becomes shallow by dry etching.

  The trench etching conditions are, for example, an ICP (Inductive Coupled Plasma) type trench etcher, the flow rates of HBr gas, SF6 gas and O2 gas are 40 sccm, 42 sccm and 45 sccm, respectively, the source power is 800 W, the bias power is 120 W, The pressure was 25 mTorr.

  FIG. 3 is a schematic schematic view showing a second example of the planar shape of the vicinity of the trench termination of the semiconductor device according to the present invention, and FIG. 4 is a cross-sectional shape of the trench along the cutting line DD ′ of FIG. FIG. 3 and 4, reference numeral 31 is a semiconductor substrate, and the shaded portion indicated by reference numeral 32 is a trench. As shown in FIG. 3, in the second example, the planar shape of the trench 32 has a boat shape in which a portion 33 near the end of the trench 32 is smoothly narrowed from the trunk portion 34. Such a planar trench 32 is formed by forming a mask oxide film having a pattern corresponding to this shape on a semiconductor substrate and performing well-known dry etching. In the formed trench 32, as shown in FIG. 4, the end vicinity portion 33 is gradually shallower than the body portion 34.

  FIG. 5 is a schematic schematic view showing a third example of the planar shape of the vicinity of the trench termination of the semiconductor device according to the present invention, and FIG. 6 is a cross-sectional shape of the trench along the cutting line FF ′ of FIG. FIG. 5 and 6, reference numeral 41 is a semiconductor substrate, and the shaded portion indicated by reference numeral 42 is a trench. As shown in FIG. 5, in the third example, the planar shape of the trench 42 is a combination of the bottleneck type of the first example and the boat type of the second example, that is, the end vicinity portion 43 is The shape extends from the body portion 44 through the intermediate portion 45 that smoothly narrows to a portion 46 that is narrower by one step than the width of the body portion 44. This one-step narrow portion 46 is also shaped like a boat. Such a planar trench 42 is formed by forming a mask oxide film having a pattern corresponding to this shape on a semiconductor substrate and performing well-known dry etching. In the formed trench 42, as shown in FIG. 6, the end vicinity portion 43 is gradually shallower than the body portion 44.

  FIG. 7 is a schematic schematic view showing a fourth example of the planar shape of the vicinity of the trench termination of the semiconductor device according to the present invention, and FIG. 8 is a cross-sectional shape of the trench along the cutting line HH ′ of FIG. FIG. 7 and 8, reference numeral 51 is a semiconductor substrate, and the shaded portion indicated by reference numeral 52 is a trench. As shown in FIG. 7, in the fourth example, the planar shape of the trench 52 has a one-step narrower intermediate portion 55 than the intermediate portion 55 in the vicinity of the end portion 53 of the trench 52. The shape reaches a narrow portion 56 in a stepped manner. That is, the end vicinity portion 53 has a shape that is two steps narrower than the body portion 54. Such a planar trench 52 is formed by forming a mask oxide film having a pattern corresponding to this shape on a semiconductor substrate and performing well-known dry etching. In the formed trench 52, as shown in FIG. 8, the end vicinity portion 53 becomes shallower than the body portion 54 stepwise. Note that the end vicinity portion 53 may be narrowed by three or more steps.

  FIG. 9 is a schematic schematic view showing a fifth example of the planar shape of the vicinity of the trench termination of the semiconductor device according to the present invention, and FIG. 10 is a cross-sectional shape of the trench along the cutting line JJ ′ of FIG. FIG. 9 and 10, reference numeral 61 is a semiconductor substrate, and the shaded portions indicated by reference numerals 62, 63, and 64 are trenches. As shown in FIG. 9, in the fifth example, in a structure in which a plurality of trenches 62 and 63 are arranged in a lattice shape, for example, the width of the outermost trench 64 is narrower than the other trenches 62 and 63. . Such planar trenches 62, 63 and 64 are formed by forming a mask oxide film having a pattern corresponding to this shape on a semiconductor substrate and performing well-known dry etching. In the formed trenches 62, 63, 64, as shown in FIG. 10, the outermost peripheral trench 64 is shallower than the inner trenches 62, 63. The trench 64) is shallower than the body portion closer to the center.

  In the fifth example, if the width of the outermost trench is the narrowest, the widths of the other trenches need not be the same. That is, for example, as shown in FIG. 11, even if the width of the trench 65 extending in the lateral direction and the width of the trench 66 extending in the vertical direction are different inside the outermost trench 64, the width of the outermost trench 64 is the largest. If it is narrow, the outermost trench 64 becomes the shallowest by dry etching. Therefore, the vicinity of the ends of the trenches 65 and 66 extending vertically and horizontally (that is, the outermost trench 64) is shallower than the body portion closer to the center. For example, as shown in FIG. 12, if the width of the outermost periphery trench 64 is the narrowest, the pattern of the trenches 67, 68, 69 on the inner side is not limited to the lattice shape, but other than the lattice such as an amid shape. The intersection pattern may be used.

  Next, a finished structure of the semiconductor device to which the trench of the first example shown in FIGS. 1 and 2 is applied will be described. First, an example of the structure of the trench MOSFET will be described. FIG. 13 is a partial cross-sectional view showing a cross-sectional structure of the trench MOSFET along the cutting line B-B ′ of FIG. 1. The device cross-sectional structure along the cutting line B-B ′ is the same as the conventional structure shown in FIG. However, in the trench MOSFET shown in FIG. 13, reference numeral 200 denotes a trench, reference numeral 201 denotes an n + -type drain layer, reference numeral 202 denotes an n-type drift layer, reference numeral 203 denotes a p-type channel region, reference numeral 204 denotes an n-type source region, reference numeral 205 Is a gate oxide film which is a gate insulating film, numeral 206 is a gate electrode, numeral 207 is an interlayer insulating film, numeral 208 is a source electrode, and numeral 209 is a drain electrode.

  FIG. 14 is a partial cross-sectional view showing a cross-sectional structure of the trench MOSFET taken along section line A-A ′ of FIG. 1. As shown in FIG. 14, the gate electrode 206 is drawn to the substrate surface at the end portion 210 of the trench 200, extends to the field oxide film 221 along the substrate surface, and is a contact hole opened in the interlayer insulating film 207 there. It is connected to the gate metal electrode 223 through 222. Here, since the vicinity of the end of the trench 200 is tapered (see FIG. 1), the trench 200 becomes shallow in the vicinity of the end. Further, since the retention of the etching gas is reduced in the narrow trench portion, the terminal corner portion 211 of the trench 200 is rounded, and the electric field concentration on the terminal corner portion 211 is alleviated or the electric field concentration is eliminated. As a result, a decrease in breakdown voltage at the terminal corner portion 211 is prevented.

  Further, since the end corner portion 211 of the trench 200 is in a shallow position, the end corner portion 211 is buried in the p-type region (p-type channel region 203), and the breakdown voltage can be further maintained. Although illustration is omitted, even if the end corner portion of the trench is not buried in the p-type region, the end corner portion is not sharp, and thus the breakdown voltage can be sufficiently prevented from decreasing. Although not shown and described, the same applies when the trenches of the second to fifth examples are applied.

  Next, an example of the structure of a trench IGBT to which the trench of the first example shown in FIGS. 1 and 2 is applied will be described. FIG. 15 is a partial cross-sectional view showing a cross-sectional structure of the trench IGBT along the cutting line B-B ′ of FIG. 1. As shown in FIG. 15, a p-type channel region 303 is formed in the surface layer of the n-type drift layer 302 on the p + -type collector layer 301. An n-type emitter region 304 is selectively formed on the surface layer of the p-type channel region 303. Then, a trench 300 that reaches the drift layer 302 from the surface of the emitter region 304 through the channel region 303 is formed. A gate oxide film 305, which is a gate insulating film, is formed along the inner surface of the trench 300, and the inside thereof is filled with a gate electrode 306 made of polycrystalline silicon. An emitter electrode 308 is stacked on the surface of the emitter region 304. The emitter electrode 308 and the gate electrode 306 are insulated by an interlayer insulating film 307. A collector electrode 309 is provided on the back surface of the collector layer 301.

  FIG. 16 is a partial cross-sectional view showing a cross-sectional structure of trench IGBT taken along section line A-A ′ of FIG. 1. As shown in FIG. 16, the gate electrode 306 is drawn to the substrate surface at the end portion 310 of the trench 300, extends along the substrate surface to the field oxide film 321, and is a contact hole opened in the interlayer insulating film 307 there. It is connected to the gate metal electrode 323 through 322. Here, since the trench 300 has a tapered portion in the vicinity of the end (see FIG. 1), the trench 300 is shallow in the vicinity of the end, and the end corner 311 is rounded due to a decrease in the retention of the etching gas. As a result, the electric field concentration at the terminal corner portion 311 is alleviated or the electric field concentration is eliminated, and the breakdown voltage drop at the terminal corner portion 311 is prevented.

  Further, since the terminal corner portion 311 of the trench 300 is buried in the p-type region (p-type channel region 303), the breakdown voltage can be further maintained. Although illustration is omitted, even if the end corner portion of the trench is not buried in the p-type region, the end corner portion is not sharp, and thus the breakdown voltage can be sufficiently prevented from decreasing. Although not shown and described, the same applies when the trenches of the second to fifth examples are applied.

  Next, an example of the structure of the TLPM to which the trench of the first example shown in FIGS. 1 and 2 is applied will be described. FIG. 17 is a partial cross-sectional view showing a cross-sectional structure of the TLPM along the cutting line B-B ′ in FIG. 1. As shown in FIG. 17, trench 400 is formed from the surface of p − type semiconductor substrate 401. An n-type extended drain 402 and a p-type base region 403 are formed on the side and below the trench 400, respectively. A gate oxide film 405 that is a gate insulating film is formed along the sidewall of the trench 400. A gate electrode 406 made of polycrystalline silicon is formed along the gate oxide film 405 inside. A source electrode 408 is provided inside the gate electrode 406 with a first insulating film 407 interposed therebetween. The source electrode 408 is connected to the n + -type source region 404 formed in the base region 403 at the bottom of the trench 400. The drain electrode 409 is connected to the extended drain 402 through the second insulating film 431 covering the surface of the extended drain 402 and the first insulating film 407 extending to the upper side.

  18 is a partial cross-sectional view showing a cross-sectional structure of the TLPM along the cutting line A-A ′ in FIG. 1. As shown in FIG. 18, the gate electrode 406 is drawn to the substrate surface at the terminal portion 410 of the trench 400 and is connected to the gate metal electrode 423 on the second insulating film 431. Here, since the trench 400 has a tapered portion in the vicinity of the end (see FIG. 1), the trench 400 becomes shallow in the vicinity of the end, and the end corner 411 is rounded due to a decrease in retention of the etching gas. As a result, the electric field concentration at the terminal corner portion 411 is alleviated or the electric field concentration is eliminated, and the breakdown voltage at the terminal corner portion 411 is prevented from being lowered. Although illustration and description are omitted, the same applies when the trenches of the second to fifth examples are applied.

  Next, an example of the structure of the two-stage TLPM to which the trench of the first example shown in FIGS. 1 and 2 is applied will be described. FIG. 19 is a partial cross-sectional view showing a cross-sectional structure of the two-stage TLPM along the cutting line B-B ′ of FIG. 1. As shown in FIG. 19, a first-stage trench 500 is formed from the surface of p − type semiconductor substrate 501. An n-type extended drain 502 is formed around the first-stage trench 500. In addition, an insulating film 531 is provided inside the first-stage trench 500. A second-stage trench 530 is formed through the insulating film 531 and the extended drain 502. A p-type base region 503 is formed below the second-stage trench 530.

  A gate oxide film 505 that is a gate insulating film is formed along the side wall of the second-stage trench 530. A gate electrode 506 made of polycrystalline silicon is formed along the gate oxide film 505 inside. A source electrode 508 is provided inside the gate electrode 506 with an insulating film 507 interposed therebetween. The source electrode 508 is connected to an n + -type source region 504 formed in the base region 503 at the bottom of the second-stage trench 530. The drain electrode 509 is connected to the extended drain 502 through an insulating film 507 extending from between the gate electrode 506 and the source electrode 508 to the surface of the extended drain 502.

  20 is a partial cross-sectional view showing a cross-sectional structure of the two-stage TLPM along the cutting line A-A ′ of FIG. 1. As shown in FIG. 20, the gate electrode 506 is drawn to the substrate surface at the end portion 510 of the trenches 500 and 530 and is connected to the gate metal electrode 523 on the insulating film 531. Here, since the trenches 500 and 530 are tapered in the vicinity of the terminal ends (see FIG. 1), the trenches 500 and 530 are shallow in the vicinity of the terminal end portion, and the terminal corner portion 511 is rounded due to the decrease in the retention of the etching gas. As a result, the electric field concentration at the terminal corner portion 511 is alleviated or the electric field concentration is eliminated, and a decrease in breakdown voltage at the terminal corner portion 511 is prevented. Although illustration and description are omitted, the same applies when the trenches of the second to fifth examples are applied.

  According to the first embodiment described above, the vicinity of the trench termination becomes shallow toward the termination, and the trench termination corner is rounded without being sharpened. Therefore, there is a singular point in the gate insulation film or the gate electrode at the trench termination corner. It is suppressed from occurring. Therefore, it is possible to prevent electric field concentration at the trench terminal corner, and to prevent a breakdown voltage of the device from decreasing. Further, when manufacturing this semiconductor device, it is only necessary to perform trench etching using a mask having a pattern that makes the trench narrow in the vicinity of the end of the trench. Therefore, without increasing the number of steps, gate insulation is performed at the trench end corner. A semiconductor device without a singular point of a film or a gate electrode is obtained.

Embodiment 2. FIG.
In the first embodiment, the thickness of the gate insulating film in the trench is uniform. In the second embodiment, however, the gate insulating film is thinner in the tapered portion near the end of the trench than in the other portions in the trench. Is thickened. For example, after forming the trench 22 having the shape shown in FIGS. 1 and 2 as described in the first embodiment, as shown in FIG. 21, the tapered portion near the trench end portion 23 is filled with the insulating film. Thus, the insulating film 27 is formed. Then, as shown in FIG. 22, isotropic etching is performed, and the insulating film 27 in the trunk portion 24 other than the vicinity of the trench termination portion 23, that is, the trunk portion 24, is formed into a gate insulating film 28 having a desired thickness. . At that time, the insulating film 27 filled in the vicinity 23 of the trench termination is not removed and remains as the gate insulating film 29. That is, the trench end vicinity portion 23 is covered with the gate insulating film 29 thicker than the gate insulating film 28 of the trunk portion 24.

  23 to 26 show sectional views and dimensions of specific trench termination structures. FIG. 23 shows a state where the insulating film 27 is formed along the trench shape along the cutting line B-B ′ of FIG. 1, and shows a cross-sectional structure of the trench body portion of FIG. 21. FIG. 24 shows a state where the formed insulating film 27 is formed into a gate insulating film 28 having a desired thickness by isotropic etching, and shows a cross-sectional structure in the trench body portion of FIG. . 25 shows a state in which the insulating film 27 is formed along the trench shape along the cutting line CC ′ in FIG. 1, and shows a cross-sectional structure in the vicinity of the end of the trench in FIG. Yes. FIG. 26 shows a state in which the gate insulating film 29 remains in the trench after isotropic etching, and shows a cross-sectional structure in the vicinity of the end of the trench in FIG.

  The same applies to the second example shown in FIGS. In the case of the second example, after the trench 32 having the shape shown in FIGS. 3 and 4 is formed as described in the first embodiment, the tapered shape of the trench end vicinity portion 33 is formed as shown in FIG. The insulating film 37 is formed so that this portion is filled with the insulating film. Then, as shown in FIG. 28, isotropic etching is performed to leave the insulating film 37 filled in the vicinity of the trench termination portion 33 as a thick gate insulating film 39, and the insulating film 37 of the body portion 34 is formed to a desired thickness. The gate insulating film 38 is used. Accordingly, the trench termination vicinity portion 33 is covered with a gate insulating film 39 thicker than the gate insulating film 38 of the trunk portion 34.

  The same applies to the third example shown in FIGS. 5 and 6. In the case of the third example, after the trench 42 having the shape shown in FIGS. 5 and 6 is formed as described in the first embodiment, the tapered shape of the trench end vicinity portion 43 is formed as shown in FIG. An insulating film 47 is formed so that this portion is filled with the insulating film. Then, as shown in FIG. 30, isotropic etching is performed so that the insulating film 47 of the body portion 44 of the trench 42 becomes a gate insulating film 48 having a desired thickness. The insulating film 47 filled in the trench end vicinity portion 43 remains as a thick gate insulating film 49. That is, the trench termination vicinity portion 43 is covered with the gate insulating film 49 thicker than the gate insulating film 48 of the trunk portion 44.

  The same applies to the fourth example shown in FIGS. In the case of the fourth example, after the trench 52 having the shape shown in FIGS. 7 and 8 is formed as described in the first embodiment, the tapered shape of the trench end vicinity portion 53 is formed as shown in FIG. The insulating film 57 is formed so that most of the portion is filled with the insulating film. Then, as shown in FIG. 32, isotropic etching is performed to make the insulating film 57 of the barrel portion 54 a gate insulating film 58 having a desired thickness, leaving the insulating film 57 filled in the vicinity of the trench termination portion 53. A thick gate insulating film 59 is used. Thereby, the trench end vicinity portion 53 is covered with a gate insulating film 59 thicker than the gate insulating film 58 of the trunk portion 54.

  Next, the finished structure of the semiconductor device in which the gate insulating film near the end of the trench is thick as described above will be described. First, an example of the structure of the trench MOSFET will be described. FIG. 33 is a partial cross-sectional view showing a cross-sectional structure of the trench MOSFET taken along section line A-A ′ of FIG. 1. As shown in FIG. 33, the gate oxide film 205 which is a gate insulating film is thick in the vicinity of the trench termination. Reference numeral 241 denotes a thick portion of the gate oxide film 205. As described above, since the portion near the trench termination is covered with the thick gate oxide film 241, the electric field concentration at the trench termination corner portion 211 can be more effectively prevented, and thus the breakdown voltage of the device can be further prevented. . Since other configurations are the same as those of the trench MOSFET shown in FIG. 14, the same components as those shown in FIG.

  As described above, in order to cover the vicinity of the trench end with the thick gate oxide film 241, the following process is performed. First, after the trench 200 is formed, the trench polymer and damage are removed. Then, after performing sacrificial oxidation, the oxide film is removed with an HF solution. Next, an oxide film is formed and isotropic etching is performed. Due to the effect of isotropic etching, a thin gate oxide film 205 is formed on the trunk portion of the trench 200, while a thick gate oxide film 241 is formed on the trench termination portion. Next, a gate electrode 206 is formed, an interlayer insulating film 207 is formed so as to cover it, and a source electrode 208 is formed. In addition, the drain electrode 209 is formed. In addition, the process demonstrated here is a part of manufacturing process of trench MOSFET. Although not shown and described, the same applies when a trench having the structure shown in FIG. 3, FIG. 5 or FIG. 7 is applied.

  Next, an example of the structure of the trench IGBT will be described. 34 is a partial cross-sectional view showing a cross-sectional structure of trench IGBT taken along section line A-A ′ of FIG. 1. As shown in FIG. 34, the gate oxide film 305 which is a gate insulating film is thick in the vicinity of the trench termination. Reference numeral 341 denotes a thick portion of the gate oxide film 305. As described above, since the portion near the trench termination is covered with the thick gate oxide film 341, electric field concentration at the trench termination corner 311 can be more effectively prevented, and thus the breakdown voltage of the device can be further prevented. . Since other configurations are the same as those of the trench IGBT shown in FIG. 16, the same configurations as those shown in FIG. Although illustration and description are omitted, the same applies when a trench having the structure shown in FIG. 3, FIG. 5, or FIG. 7 is applied.

  Next, an example of the structure of TLPM will be described. FIG. 35 is a partial cross-sectional view showing a cross-sectional structure of the TLPM along the cutting line A-A ′ in FIG. 1. As shown in FIG. 35, the gate oxide film 405 which is a gate insulating film is thick in the vicinity of the trench termination. Reference numeral 441 denotes a thick portion of the gate oxide film 405. As described above, since the portion near the trench termination is covered with the thick gate oxide film 441, electric field concentration on the trench termination corner 411 can be more effectively prevented, and thus the breakdown voltage of the device can be further prevented. . Since other configurations are the same as those of the TLPM shown in FIG. 18, the same components as those shown in FIG. Although illustration and description are omitted, the same applies when a trench having the structure shown in FIG. 3, FIG. 5, or FIG. 7 is applied.

  Next, an example of the structure of the two-stage TLPM will be described. FIG. 36 is a partial cross-sectional view showing a cross-sectional structure of the two-stage TLPM along the cutting line A-A ′ of FIG. 1. As shown in FIG. 36, the gate oxide film 505 which is a gate insulating film is thick in the vicinity of the trench termination. Reference numeral 541 denotes a thick portion of the gate oxide film 505. As described above, since the portion near the trench termination is covered with the thick gate oxide film 541, the electric field concentration on the trench termination corner 511 can be more effectively prevented, and thus the breakdown voltage of the device can be further prevented. . Since other configurations are the same as those of the two-stage TLPM shown in FIG. 20, the same components as those shown in FIG. Although illustration and description are omitted, the same applies when a trench having the structure shown in FIG. 3, FIG. 5, or FIG. 7 is applied.

  According to the second embodiment described above, in addition to the suppression of the occurrence of singular points in the gate insulating film and the gate electrode at the trench termination corner as in the first embodiment, the portion near the trench termination is thicker. Since it is covered with the gate insulating film, it is possible to more effectively prevent electric field concentration at the trench terminal corner. Therefore, it is possible to further prevent the breakdown voltage of the device from decreasing. In addition, the semiconductor device having such a configuration can be manufactured without increasing the number of steps.

  In the above, the present invention can be variously changed. For example, the gate insulating film is not limited to an oxide film, but may be an electrical insulating film or a film that functions as a high resistance film. Further, the present invention is not limited to a device made of a silicon semiconductor, but can be applied to a device made of a compound semiconductor such as SiC. Further, the present invention can also be applied to other trench type MOS semiconductor devices such as IEGT (Injection Enhanced Insulated Gate Bipolar Transistor), insulated gate thyristor, and IPM (Intelligent Power Module).

It is a typical schematic diagram showing the 1st example of the plane shape of the trench termination neighborhood part of the semiconductor device concerning the present invention. FIG. 2 is a schematic diagram illustrating a cross-sectional shape of a trench along a cutting line A-A ′ in FIG. 1. It is a typical schematic diagram showing the 2nd example of the plane shape of the trench termination neighborhood part of the semiconductor device concerning the present invention. FIG. 4 is a schematic schematic diagram illustrating a cross-sectional shape of a trench along a cutting line D-D ′ in FIG. 3. It is a schematic diagram which shows the 3rd example of the planar shape of the trench termination | terminus vicinity of the semiconductor device concerning this invention. FIG. 6 is a schematic diagram illustrating a cross-sectional shape of a trench along a cutting line F-F ′ in FIG. 5. It is a typical schematic diagram showing the 4th example of the plane shape of the trench termination neighborhood part of the semiconductor device concerning the present invention. FIG. 8 is a schematic diagram illustrating a cross-sectional shape of a trench along a cutting line H-H ′ in FIG. 7. It is a typical schematic diagram showing the 5th example of the plane shape of the trench termination neighborhood part of the semiconductor device concerning the present invention. FIG. 10 is a schematic schematic diagram illustrating a cross-sectional shape of a trench along a cutting line J-J ′ in FIG. 9. It is a typical schematic diagram showing the modification of the 5th example of the plane shape of the trench end neighborhood part of the semiconductor device concerning the present invention. It is a typical schematic diagram showing another modification of the 5th example of the shape of a plane of the portion near the trench termination of the semiconductor device concerning the present invention. FIG. 3 is a partial cross-sectional view showing a cross-sectional structure of the trench MOSFET according to the first embodiment taken along section line B-B ′ of FIG. 1. FIG. 2 is a partial cross-sectional view showing a cross-sectional structure of the trench MOSFET according to the first embodiment taken along a cutting line A-A ′ of FIG. 1. FIG. 3 is a partial cross-sectional view showing a cross-sectional structure of trench IGBT of the first embodiment taken along section line B-B ′ of FIG. 1. FIG. 3 is a partial cross-sectional view showing a cross-sectional structure of trench IGBT of the first embodiment taken along section line A-A ′ of FIG. 1. FIG. 2 is a partial cross-sectional view illustrating a cross-sectional structure of the TLPM according to the first embodiment taken along a cutting line B-B ′ in FIG. 1. FIG. 2 is a partial cross-sectional view illustrating a cross-sectional structure of the TLPM according to the first embodiment taken along a cutting line A-A ′ in FIG. 1. FIG. 2 is a partial cross-sectional view showing a cross-sectional structure of a two-stage TLPM of Embodiment 1 taken along a cutting line B-B ′ of FIG. 1. FIG. 2 is a partial cross-sectional view showing a cross-sectional structure of a two-stage TLPM of Embodiment 1 taken along a cutting line A-A ′ of FIG. 1. FIG. 3 is a schematic diagram for explaining a configuration in which a trench end vicinity portion is filled with a gate insulating film in the first example of the trench end vicinity portion shown in FIGS. 1 and 2. FIG. 3 is a schematic diagram for explaining a configuration in which a trench end vicinity portion is filled with a gate insulating film in the first example of the trench end vicinity portion shown in FIGS. 1 and 2. It is a figure which shows the cross-section in the trench trunk | drum part of FIG. It is a figure which shows the cross-section in the trench trunk | drum part of FIG. It is a figure which shows the cross-section in the trench termination | terminus vicinity part of FIG. It is a figure which shows the cross-sectional structure in the trench termination | terminus vicinity part of FIG. FIG. 5 is a schematic diagram for explaining a configuration in which a trench termination vicinity portion is filled with a gate insulating film in the second example of the trench termination vicinity portion shown in FIGS. 3 and 4. FIG. 5 is a schematic diagram for explaining a configuration in which a trench termination vicinity portion is filled with a gate insulating film in the second example of the trench termination vicinity portion shown in FIGS. 3 and 4. FIG. 7 is a schematic diagram for explaining a configuration in which a trench end vicinity portion is filled with a gate insulating film in the third example of the trench end vicinity portion shown in FIGS. 5 and 6. FIG. 7 is a schematic diagram for explaining a configuration in which a trench end vicinity portion is filled with a gate insulating film in the third example of the trench end vicinity portion shown in FIGS. 5 and 6. FIG. 10 is a schematic diagram for explaining a configuration in which a trench end vicinity portion is filled with a gate insulating film in a fourth example of the trench end vicinity portion shown in FIGS. 7 and 8. FIG. 10 is a schematic diagram for explaining a configuration in which a trench end vicinity portion is filled with a gate insulating film in a fourth example of the trench end vicinity portion shown in FIGS. 7 and 8. FIG. 4 is a partial cross-sectional view showing a cross-sectional structure of a trench MOSFET according to a second embodiment taken along section line A-A ′ of FIG. 1. FIG. 6 is a partial cross-sectional view showing a cross-sectional structure of a trench IGBT according to a second embodiment taken along section line A-A ′ of FIG. 1. It is a fragmentary sectional view which shows the cross-section of TLPM of Embodiment 2 in the cutting line A-A 'of FIG. It is a fragmentary sectional view which shows the cross-section of 2 step | paragraph TLPM of Embodiment 2 in the cutting line A-A 'of FIG. It is a schematic diagram which shows the cross section of the trench formed by changing the trench width by dry etching. It is a top view which shows the shape of the trench pattern in the conventional semiconductor device. FIG. 39 is a partial cross-sectional view showing a cross-sectional structure of the trench MOSFET taken along a cutting line M-M ′ in FIG. 38. FIG. 39 is a partial cross-sectional view showing a cross-sectional structure of the trench MOSFET taken along a cutting line L-L ′ in FIG. 38.

Explanation of symbols

21, 31, 41, 51, 61 Semiconductor substrate 22, 32, 42, 52, 62, 63, 65-69, 100, 200, 300, 400, 500 Trench 23, 33, 43, 53 Near end portion of trench 28 , 29, 38, 39, 48, 49, 58, 59, 205, 305, 405, 505 Gate insulating film (gate oxide film)
64 Outermost trench 206, 306, 406, 506 Gate electrode

Claims (1)

A current path is provided in the trench formed in the semiconductor substrate or in the vicinity of the side wall or bottom, and gate insulation is provided along part or all of the bottom surface of the trench or part or all of the side wall of the trench. In a semiconductor device provided with a gate electrode through a film,
A trench provided to connect ends of a plurality of intersecting trenches (hereinafter referred to as “outermost trench”) is shallower than an inner trench, and the width of the outermost trench is equal to that of the inner trench. A semiconductor device characterized by being narrower than the width.

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