JP4882161B2 - Signal output circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a signal output circuit, and more particularly to a signal output circuit that inverts and amplifies a supplied signal and outputs the inverted signal.
[0002]
[Prior art]
FIG. 2 shows a circuit diagram of an example of a conventional signal output circuit. In the figure, an input signal supplied to the terminal 10 is supplied to the base of an npn transistor Q3 via a resistor R1. The transistor Q3 has an npn transistor Q4 and an emitter connected in common to form a differential circuit, and the emitters of the transistors Q3 and Q4 are grounded via a current source 12. A reference voltage Vref is applied to the base of the transistor Q4 via a resistor R3, the collector of the transistor Q3 is connected to the collector of the pnp transistor Q1, and the collector of the transistor Q4 is an npn transistor Q5 having a constant voltage E1 applied to the base. Are connected to the collector of the pnp transistor Q2 through the emitter and collector of the transistor. Transistors Q1 and Q2 have a current mirror configuration, and their emitters are connected to a power supply Vcc. The transistors Q1 to Q5 constitute an inverting amplifier, and an inverted and amplified signal is output from the point A which is the collector of the transistor Q3.
[0003]
The base of the pnp transistor Q6 is connected to the point A, and the point B which is the emitter of the transistor Q6 is connected to the power supply Vcc via the constant current source 14, and is also connected to the base of the npn transistor Q7. The collector is grounded. The collector of the transistor Q7 is connected to the power supply Vcc, the emitter is grounded via the constant current source 16, and is connected to the base of the transistor Q3 via the resistor R2, and is connected to the terminal 18 via the resistor R4. Yes. As a result, the signal at point A is output from the terminal 18 after impedance conversion by the transistors Q6 and Q7 of the emitter follower configuration of the output section.
[0004]
[Problems to be solved by the invention]
In the conventional signal output circuit, an pnp transistor Q6 having an emitter follower configuration is used in the output section. For this reason, in the high frequency region where the input signal exceeds 10 MHz, there is a problem that the characteristics of the pnp transistor Q6 are deteriorated as compared with other npn transistors.
[0005]
The present invention has been made in view of the above points, and an object of the present invention is to provide a signal output circuit that can prevent deterioration of characteristics in a high frequency region by eliminating a pnp transistor in an output section.
[0006]
[Means for Solving the Problems]
The invention according to claim 1 is a differential circuit (Q11 to Q15, 22) for non-inverting amplification of an input signal;
An npn transistor (Q17) for inverting and amplifying the output signal of the differential circuit;
Level shift circuits (Q18, Q20) for level-shifting the signal output from the npn transistor (Q17);
Possess a buffer comprised of said level shift circuit (Q18, Q20) at the level shifted npn transistor emitter follower configuration for outputting a signal (Q21),
The level shift circuit is configured by vertically connecting two diode-connected npn transistors (Q18, Q20), and the npn transistor (Q21) constituting the buffer is diode-connected npn transistor (Q19). ) And the collector of the npn transistor (Q17) for inverting and amplifying the output signal of the differential circuit together with the emitter of the diode-connected npn transistor (Q18) of the level shift circuit, thereby reducing the number of circuit elements. Thus, the pnp transistor in the output part can be eliminated to prevent the deterioration of the characteristics in the high frequency region.
[0008]
Note that the reference numerals in the parentheses are given for ease of understanding, are merely examples, and are not limited to the illustrated modes.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows a circuit diagram of an embodiment of a signal output circuit of the present invention.
[0010]
In FIG. 1, an input signal supplied to the terminal 20 is supplied to the base of an npn transistor Q14 via a resistor R11. The transistor Q14 and the npn transistor Q15 are connected in common to form a differential circuit. The emitters of the transistors Q14 and Q15 are grounded via the current source 22. A reference voltage Vref is applied to the base of the transistor Q15 via the resistor R3, the collector of the transistor Q14 is connected to the collector of the pnp transistor Q12 and the bases of the pnp transistors Q12 and Q13, and the collector of the transistor Q15 is connected to the resistor R15. The transistor Q13 is connected to the collector.
[0011]
Transistors Q12 and Q13 have a current mirror configuration, and their emitters are connected to the emitter of npn transistor Q11. The transistor Q11 has a constant voltage E2 applied to the base, the collector is connected to the power supply Vcc, and the transistor Q11 is used as an emitter follower. The transistors Q11 to Q15 constitute a non-inverting amplifier, and a non-inverted amplified signal is output from the point C which is the collector of the transistor Q15.
[0012]
The base of the npn transistor Q16 constituting the emitter follower is connected to the point C, the collector of the transistor Q16 is connected to the power supply Vcc, and the emitter is connected to one end of the resistor R16. The other end of the resistor R16 is grounded via the constant current source 24 and is connected to the base of the npn transistor Q17.
[0013]
The collector of transistor Q17 is connected to the emitters of npn transistors Q18 and Q19, and the emitter of transistor Q17 is grounded. Transistor Q18 has a diode configuration in which a base and a collector are connected, and the base and collector are connected to the emitter of npn transistor Q20. Transistor Q20 has a diode configuration in which a base and a collector are connected, and the base and collector are connected to the base of npn transistor Q21.
[0014]
The transistor Q19 has a diode configuration in which a base and a collector are connected. The base and collector are connected to the emitter of the npn transistor Q21, connected to the base of the transistor Q14 through the resistor R14, and connected to the terminal through the resistor R14. 26. The transistor Q18 and the transistor Q19 have an emitter area ratio of, for example, 1: 2.
[0015]
Transistor Q21 has a collector connected to power supply Vcc, a base connected to power supply Vcc via resistor R17, and biased, and an emitter connected to the collector of transistor Q19 to form an emitter-follower buffer. The transistor Q20 and the transistor Q21 have an emitter area ratio of, for example, 1: 2.
[0016]
As a result, the signal at the point C is subjected to impedance conversion by the transistor Q16 having the emitter follower configuration of the output section, inverted by the transistor Q17, and further output from the terminal 26 through the transistor Q21 having the emitter follower configuration.
[0017]
In this embodiment, since the transistors Q11 to Q15 are non-inverting amplifiers, it is possible to invert and amplify them using the npn transistor Q17, so that it is not necessary to use the pnp transistor Q6 as in the prior art, and the input signal is 10 MHz. It is possible to prevent deterioration of characteristics in a high frequency region that exceeds the above.
[0018]
The collector potential of the transistor Q17 is level-shifted by the base-emitter drop voltage (approximately 0.7V) in the transistors Q18 and Q20 and supplied to the base of the transistor Q21. Since the level is shifted by the drop voltage and supplied to the emitter of the transistor Q21, a signal can be output from the terminal 26 through the transistor Q21 having an emitter follower configuration.
[0019]
Further, the signal amplitude at the point C which is the collector of the transistor Q15 becomes the base current ib17 × R16 of the transistor Q17, and since the signal is amplified by the transistor Q17, the value of the base current ib17 may be small. The signal amplitude at can be small, and the deterioration of crosstalk can be prevented. In the conventional circuit of FIG. 2, the output of the terminal 18 and the signal amplitude at the point A are the same, and there is a possibility that the signal jumps into another circuit and the crosstalk deteriorates.
[0020]
【Effect of the invention】
As described above, the invention described in claim 1 is a differential circuit that non-inverts and amplifies an input signal, an npn transistor that inverts and amplifies the output signal of the differential circuit, and a level that shifts the level of the signal output from the npn transistor. By having a shift circuit and a buffer composed of an npn transistor having an emitter follower configuration that outputs a signal shifted in level by the level shift circuit, the pnp transistor in the output section is eliminated to prevent deterioration of characteristics in the high frequency region. it can.
[0021]
In the invention described in claim 2, the level shift circuit is configured by vertically connecting two diode-connected npn transistors, and in the invention described in claim 3, the npn transistors constituting the buffer are connected. The number of circuit elements can be reduced by connecting the emitter to the collector of an npn transistor that inverts and amplifies the output signal of the differential circuit together with the diode-connected npn transistor of the level shift circuit via the diode-connected npn transistor. 1 can be realized.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of an embodiment of a signal output circuit of the present invention.
FIG. 2 is a circuit diagram of an example of a conventional signal output circuit.
[Explanation of symbols]
20, 26 Terminals 22, 24 Constant current sources Q11, Q14 to Q21 npn transistor Q12, Q13 pnp transistors R11 to R17 Resistance

Claims (1)

A differential circuit for non-inverting amplification of the input signal;
An npn transistor for inverting and amplifying the output signal of the differential circuit;
A level shift circuit for level shifting a signal output from the npn transistor;
A buffer composed of an npn transistor having an emitter follower configuration for outputting a signal level-shifted by the level shift circuit ;
The level shift circuit is configured by vertically connecting two diode-connected npn transistors,
The emitter of the npn transistor constituting the buffer is the collector of the npn transistor that inverts and amplifies the output signal of the differential circuit together with the emitter of the diode-connected npn transistor of the level shift circuit via the diode-connected npn transistor. A signal output circuit connected to the circuit.

Images