JP2002330036A - Signal output circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal output circuit wherein deterioration of characteristic in a high frequency region can be prevented by eliminating a PNP transistor in an output part. SOLUTION: This signal output circuit is provided with differential circuits Q11-Q15, 22 wherein input signals are subjected to not-inverting amplification, an NPN transistor Q17 wherein output signals of the differential circuits are subjected to inverting amplification, level shift circuits Q18, Q20 wherein an output signal of the NPN transistor Q17 is subjected to level shift, and a buffer constituted of an NPN transistor Q21 of an emitter follower constitution which outputs a signal subjected to level shift by the level shift circuits Q18, Q20. Thereby the PNP transistor in the output part is eliminated, and deterioration of characteristic in the high frequency region can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal output circuit, and more particularly, to a signal output circuit for inverting and amplifying a supplied signal and outputting the inverted signal.

[0002]

2. Description of the Related Art FIG. 2 is a circuit diagram showing an example of a conventional signal output circuit. In the figure, an input signal supplied to a terminal 10 is supplied to the base of an npn transistor Q3 via a resistor R1. The transistor Q3 is an npn transistor Q4
And the emitter are connected in common to form a differential circuit,
The emitters of the transistors Q3 and Q4 are grounded via the current source 12. A reference voltage Vref is applied to the base of the transistor Q4 via a resistor R3, the collector of the transistor Q3 is connected to the collector of a pnp transistor Q1, and the collector of the transistor Q4 is connected to an npn transistor Q5 having a base to which a constant voltage E1 is applied. Is connected to the collector of the pnp transistor Q2 via the emitter and the collector of the transistor Q2. The transistors Q1 and Q2 have a current mirror configuration, and their emitters are connected to the power supply Vcc. The transistors Q1 to Q5 constitute an inverting amplifier, and an inverted and amplified signal is output from a point A which is a collector of the transistor Q3.

The point A is connected to the base of a pnp transistor Q6, and the point B, which is the emitter of the transistor Q6, is connected to a power supply Vcc via a constant current source 14.
It is connected to the base of npn transistor Q7, and the collector of transistor Q6 is grounded. The collector of transistor Q7 is connected to power supply Vcc, the emitter is grounded via constant current source 16, connected to the base of transistor Q3 via resistor R2, and connected to terminal 18 via resistor R4. I have. This allows
The signal at the point A is output from the terminal 18 after being subjected to impedance conversion by the transistors Q6 and Q7 having an emitter follower configuration in the output section.

[0004]

In the above-mentioned conventional signal output circuit, a pnp transistor Q6 having an emitter follower configuration is used for an output portion. Therefore, if the input signal is 10M
In a high frequency region exceeding Hz, there is a problem that the characteristics of the pnp transistor Q6 are deteriorated as compared with other npn transistors.

The present invention has been made in view of the above points, and has as its object to provide a signal output circuit capable of preventing the deterioration of characteristics in a high frequency region by eliminating a pnp transistor in an output section.

[0006]

According to a first aspect of the present invention, there is provided a differential circuit (Q11 to Q1) for non-inverting amplifying an input signal.
5, 22), an npn transistor (Q17) for inverting and amplifying an output signal of the differential circuit, a level shift circuit (Q18, Q20) for level shifting a signal output from the npn transistor (Q17), An npn transistor (Q) having an emitter follower configuration that outputs a signal level-shifted by the shift circuits (Q18, Q20)
By having the buffer configured in 21), it is possible to eliminate the pnp transistor in the output unit and prevent deterioration of characteristics in a high frequency region.

According to the second aspect of the present invention, the level shift circuit is configured by vertically connecting two diode-connected npn transistors (Q18, Q20).
According to the third aspect of the present invention, n
An npn transistor (Q21) that inverts and amplifies the output signal of the differential circuit together with the diode-connected npn transistor (Q18) of the level shift circuit via the diode-connected npn transistor (Q19) with the emitter of the pn transistor (Q21). By connecting to the collector of Q17), the invention according to claim 1 can be realized with a small number of circuit elements.

The reference numerals in the parentheses are provided for easy understanding, are merely examples, and are not limited to the illustrated embodiment.

[0009]

FIG. 1 is a circuit diagram showing an embodiment of a signal output circuit according to the present invention.

In FIG. 1, an input signal supplied to a terminal 20 is supplied to the base of an npn transistor Q14 via a resistor R11. The transistor Q14 has an emitter connected in common with the npn transistor Q15 to form a differential circuit. The emitters of the transistors Q14 and Q15 are grounded via the current source 22. Transistor Q
A reference voltage Vref is applied to the base of the transistor 15 via a resistor R3. The collector of the transistor Q14 is connected to the collector of the pnp transistor Q12 and the pnp transistor Q1.
2, connected to the base of Q13, and the collector of transistor Q15 is connected to the collector of transistor Q13 via resistor R15.

The transistors Q12 and Q13 have a current mirror configuration, and their emitters are npn transistors Q
11 emitters. Transistor Q11
A constant voltage E2 is applied to the base, and the collector is the power supply Vc
The transistor Q11 is used as an emitter follower. The above transistors Q11 to Q11
Q15 constitutes a non-inverting amplifier, and the transistor Q15
A non-inverted amplified signal is output from a point C, which is a collector of the reference numeral 15.

At point C, np constituting an emitter follower
The base of n-transistor Q16 is connected, the collector of transistor Q16 is connected to power supply Vcc, and the emitter is connected to one end of resistor R16. The other end of the resistor R16 is grounded via a constant current source 24 and is connected to the base of an npn transistor Q17.

The collector of transistor Q17 is connected to the emitters of npn transistors Q18 and Q19, and the emitter of transistor Q17 is grounded. The transistor Q18 has a diode configuration in which a base and a collector are connected, and the base and the collector are connected to the emitter of the npn transistor Q20. Transistor Q2
Reference numeral 0 denotes a diode configuration in which a base and a collector are connected, and the base and the collector are connected to an npn transistor Q21.
Connected to the base.

Transistor Q19 has a diode configuration in which a base and a collector are connected. The base and the collector are connected to the emitter of npn transistor Q21, connected to the base of transistor Q14 via a resistor R14, and connected to a resistor R14. The terminal 26 is connected to the terminal 26. The transistor Q18 and the transistor Q1
9 indicates that the emitter area ratio is, for example, 1: 2.

The transistor Q21 has a collector connected to the power supply Vc.
c, and the base is connected to the power supply Vcc via a resistor R17.
, And the emitter is connected to the collector of the transistor Q19 to form an emitter-follower buffer. The transistor Q2
The emitter area ratio between 0 and the transistor Q21 is, for example, 1: 2.

As a result, the signal at the point C is converted in impedance by the transistor Q16 having an emitter follower configuration at the output portion, is inverted by the transistor Q17, and is output from the terminal 26 through the transistor Q21 having the emitter follower configuration.

In this embodiment, the transistor Q11
Since Q15 to N15 are non-inverting amplifiers, it is possible to invert and amplify using the npn transistor Q17, and it is not necessary to use the pnp transistor Q6 as in the conventional case. Deterioration of characteristics can be prevented.

The collector potential of the transistor Q17 is level-shifted by the respective base-emitter drop voltages (approximately 0.7 V) by the transistors Q18 and Q20 and supplied to the base of the transistor Q21. The signal is level-shifted by the emitter-to-emitter drop voltage and is supplied to the emitter of the transistor Q21.
1 can be output from the terminal 26.

The signal amplitude at the point C, which is the collector of the transistor Q15, is the base current ib17 × R16 of the transistor Q17. Since the signal is amplified by the transistor Q17, the value of the base current ib17 may be small. , C, the signal amplitude may be small, and deterioration of crosstalk can be prevented. In the conventional circuit of FIG. 2, the output of the terminal 18 and the signal amplitude at the point A are the same, and a signal may jump into another circuit to deteriorate crosstalk.

[0020]

As described above, the first aspect of the present invention provides
A differential circuit that non-inverts and amplifies an input signal, an npn transistor that inverts and amplifies an output signal of the differential circuit, a level shift circuit that level shifts a signal output from the npn transistor, and a signal that is level-shifted by the level shift circuit , A buffer composed of an npn transistor having an emitter follower configuration that outputs an output signal can eliminate the pnp transistor in the output section, thereby preventing deterioration in characteristics in a high frequency region.

According to the second aspect of the present invention, the level shift circuit is formed by vertically connecting two diode-connected npn transistors. In the third aspect of the present invention, a buffer is formed. By connecting the emitter of the npn transistor together with the diode-connected npn transistor of the level shift circuit via the diode-connected npn transistor to the collector of the npn transistor for inverting and amplifying the output signal of the differential circuit,
The invention described in claim 1 can be realized with a small number of circuit elements.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of one embodiment of a signal output circuit of the present invention.

FIG. 2 is a circuit diagram of an example of a conventional signal output circuit.

[Explanation of symbols]

 20, 26 terminal 22, 24 constant current source Q11, Q14 to Q21 npn transistor Q12, Q13 pnp transistor R11 to R17 resistance

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Taku Furuya 1601 Sakai, Atsugi-shi, Kanagawa Prefecture F-term in Atsugi Works, Mitsumi Electric Co., Ltd. 5J066 AA01 AA12 CA61 FA00 HA08 HA19 HA25 KA03 KA04 KA05 KA09 KA18 MA01 MA04 MA11 ND01 ND14 ND22 ND23 PD01

Claims (3)

[Claims] A differential circuit that non-inverts and amplifies an input signal; an npn transistor that inverts and amplifies an output signal of the differential circuit; a level shift circuit that level-shifts a signal output from the npn transistor; A buffer formed of an npn transistor having an emitter follower configuration for outputting a signal level-shifted by the shift circuit. 2. The signal output circuit according to claim 1, wherein said level shift circuit is formed by vertically connecting two diode-connected npn transistors. 3. The signal output circuit according to claim 2, wherein an emitter of an npn transistor forming the buffer is connected to a diode-connected npn transistor of the level shift circuit via a diode-connected npn transistor. A signal output circuit connected to a collector of an npn transistor for inverting and amplifying an output signal of a driving circuit.