JP4875284B2 - Semiconductor memory device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor memory device injecting carriers into a floating gate using a direct tunnel phenomenon and a manufacturing method thereof.
[Prior art]
A flash memory is known as a semiconductor memory device. The flash memory is suitable for increasing the capacity because one MISFET constitutes one memory cell. In a flash memory, electrons are injected by applying a voltage to the control gate and drain to pass a current from the source to the drain, and injecting channel hot electrons into the floating gate. Alternatively, a high voltage is applied to the control gate, and electrons are injected into the floating gate by an FN (Fowler-Nordheim) tunnel current. In order to hold the carriers injected into the floating gate, the thickness of the insulating film between the floating gate electrode and the channel region is required to be about 8 to 10 nm. In order to tunnel carriers to the floating gate through the insulating film having this thickness, it is necessary to apply a high voltage of 10V to 20V. In addition, when the FN tunnel current is used, the injection efficiency is good, but there is a problem that the operation speed cannot be increased. On the other hand, when channel hot electrons are used, the applied voltage can be made relatively low, but the power consumption increases because the injection efficiency is poor.
[0002]
For this reason, in order to increase the voltage and speed, a method has been proposed in which the tunnel insulating film is thinned and carriers are injected and extracted from the floating gate by the direct tunnel phenomenon (see, for example, Patent Document 1). However, if the tunnel insulating film (oxide film) is simply made thin in the conventional flash memory, the leakage current between the source / drain and the floating gate increases, and data cannot be retained. Therefore, in order to prevent leakage between the source / drain region and the gate, the floating gate and the source / drain diffusion region are arranged so as not to overlap.
[0003]
FIG. 1A shows a configuration example of a conventional DTM element. The DTM element is formed on the tunnel insulating film 103 and the tunnel insulating film 103 having a thickness of about 2 to 3 nm formed on the silicon substrate 101 in an active region partitioned by an element isolation region 102 such as a LOCOS oxide film. A floating gate 105, a dielectric film 106 located on the floating gate 105, and an upper control gate electrode 107 on the dielectric film 106. A side control gate electrode 108 is formed to cover the floating gate 105, the dielectric film 106, and the side wall of the upper control electrode 107, and the floating gate 106 is surrounded by the control gate. The side wall of the side control gate is covered with a sidewall 109. In this configuration, the floating gate 105 and the source / drain diffusion region 110 do not overlap.
[0004]
[Patent Document 1]
JP 2002-16155 A
[0005]
[Problems to be solved by the invention]
The cell size of the conventional DTM element is 8F²It is about (2F × 4F). F is a design dimension that serves as a reference in the corresponding design rule. In order to further reduce the cell area of the DTM device and improve the degree of integration, the present invention² A direct tunnel (DT) type memory having a (2F × 2F) cell structure is provided.
[0006]
[Means for Solving the Problems]
In order to achieve the above object, according to the present invention, a trench type element isolation region is disposed adjacent to the gate structure of the memory element, and a source / drain diffusion region is disposed along the upper sidewall of the trench type element isolation region. On the semiconductor substrate partitioned by the trench type element isolation region, the floating gate electrode is located via the tunnel insulating film, and the second insulating film is located so as to cover the floating gate electrode. The control gate electrode is located on the second insulating film, and the source / drain diffusion region along the trench upper side wall does not overlap the floating gate on the semiconductor substrate.
[0007]
More specifically, in the first aspect of the present invention, 4F² Provided is a direct tunnel (DT) type memory as a semiconductor memory device realizing a cell size. Such a semiconductor memory device has volatile properties or characteristics between volatile and non-volatile, and is regarded as a semi-non-volatile memory.
[0008]
  A semiconductor memory device includes a semiconductor substrate, a trench type element isolation region formed in the semiconductor substrate, a tunnel insulating film positioned on the semiconductor substrate in a region partitioned by the element isolation region, and the tunnel insulating film A second insulating film that covers the floating gate electrode and the floating gate electrode and the trench type element isolation region, and the upper surface of the second insulating film in the trench type element isolation region is located below the upper surface of the semiconductor substrate. A second insulating film; a control gate electrode formed on the second insulating film; and a source / drain diffusion region extending along the upper sidewall of the trench type element isolation region so as not to overlap the floating gate electrode.The second insulating film is in contact with the semiconductor substrate for a predetermined distance from the end of the floating gate electrode to the end of the source / drain diffusion region.
[0009]
With this configuration, while preventing leakage between the floating gate electrode and the source / drain diffusion region, 4F² A DT memory cell of a size can be realized.
[0010]
  In the second aspect of the present invention, 4F²A method of manufacturing a semiconductor memory device having a DT memory cell of a size is provided. A method for manufacturing a semiconductor memory device includes the following steps.
  (A) forming a tunnel insulating film on the semiconductor substrate;
  (B) forming a floating gate electrode on the tunnel insulating film;
  (C) forming a dummy insulating film located on a side wall of the floating gate electrode;
  (D) forming a first trench having a depth necessary for the source / drain diffusion region using the dummy insulating film as a mask;
  (E) forming a source / drain diffusion region along the sidewall of the first trench;
  (F) forming a second trench having a depth necessary for element isolation from the bottom surface of the first trench, and burying an insulating film from the bottom surface to a portion located below the top surface of the semiconductor substrate; Forming an isolation region;
  (G) removing the dummy insulating film to form a second insulating film covering the floating gate electrode; and
  (H) forming a control gate electrode on the second insulating filmIncluding,
  The first trench is formed at a depth of 0 nm to 200 nm from the surface of the semiconductor substrate.
[0011]
According to this method, the element isolation region is formed adjacent to the gate structure, and the source / drain diffusion region is run along the side wall of the element isolation region.² Can be reduced. Since the shallow first trench is formed to form the source / drain diffusion region, and then the deep second trench is formed to form the element isolation region, etching of the insulating film for forming the element isolation region is performed. Without difficult control. Further, since the depth of the trench directly formed on the substrate can be strictly controlled, the source / drain diffusion regions can be formed with good controllability.
[0012]
That is, in order to form a desired source / drain according to the design, the shape and depth of the first trench can be accurately controlled within an arbitrary range. At the same time, the element isolation region can be formed with good controllability.
[0013]
The source / drain diffusion step into the first trench sidewall includes an ion implantation step into the first trench. The ion implantation at this time may be oblique implantation or vertical ion implantation, but in the case of vertical implantation, it is not necessary to control the angle in the oblique direction. Further, the power of ion implantation can be increased in the vertical implantation. By using silicon as the substrate material, the diffusion of impurities in the horizontal direction can be utilized by any implantation method.
[0014]
As described above, since the trench formation in the silicon substrate can be accurately controlled, the first trench and the second trench can be formed in a desired range. For example, the depth of the first trench can be appropriately set in the range of 0 to 200 nm from the substrate surface, and the second trench can be set in the range of 200 to 400 nm from the substrate surface.
[0015]
  The manufacturing method of the semiconductor memory device is as follows:
  (A) forming a tunnel insulating film on the semiconductor substrate;
  (B) forming a floating gate electrode on the tunnel insulating film;
  (C) forming a dummy insulating film located on the sidewall of the floating gate electrode;
  (D) forming a trench having a depth necessary for element isolation using the dummy insulating film as a mask;
  (E) a step of forming an impurity diffusion region extending to the lower side of the dummy insulating film by implanting ions obliquely into the sidewall of the trench using the dummy insulating film as a mask, and the impurity diffusion region remaining along the upper side wall of the trench as a source A step of forming a drain diffusion region;
  (F) forming a device isolation region by filling a trench;
  (G) The dummy insulating film is completely removed to cover the floating gate electrode.And so as to be in direct contact with the floating gate electrodeForming a second insulating film;
  (H) forming a control gate electrode on the second insulating film;
including.
[0016]
Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the accompanying drawings.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 2 is a plan configuration diagram of a DT (Direct Tunneling) memory 10 according to the embodiment of the present invention. Floating gates 15 are arranged in a matrix in an active region partitioned by a buried oxide film 12 as an element isolation region. A source / drain diffusion region 18 extends along the buried oxide film 12 so as not to overlap the floating gate 15. The source / drain diffusion region 18 functions as the bit line 18 as it is. A control gate electrode 17 covering the floating gate electrode extends in a direction orthogonal to the bit line 18. The control gate electrode 17 functions as the word line 17 as it is.
[0018]
In such a planar configuration, one memory cell 20 includes a floating gate 15 sandwiched between two adjacent bit lines 18 and a word line 17 covering the floating gate 15 and orthogonal to the bit line. Size is 4F² It has become. 4F² In order to realize this cell size, the element isolation region 12 is a trench type element isolation, and the bit line (source / drain diffusion region) runs along the upper side wall of the trench.
[0019]
FIG. 3 is a cross-sectional view taken along the line A-A ′ of FIG. 2. The DT memory cell 20 has a trench-type element isolation region 12 in which the trench 25 is filled with an oxide film in the silicon substrate 11 and a film thickness located on the silicon substrate 11 in an active region partitioned by the trench-type element isolation region 12. It has a tunnel insulating film 13 of about 2 nm and a floating gate electrode 15 located on the tunnel insulating film 13. Further, the second insulating film 16 having a thickness of about 8 to 10 nm covering the upper surface and the side surface of the floating gate electrode 15, the control gate electrode 17 located on the second insulating film 16, and the trench 25 constituting the element isolation region 12. Source / drain diffusion regions 18 extending along the upper side walls of the semiconductor device. The source / drain diffusion region 18 is formed at a position that does not overlap the floating gate 13 in order to prevent charge leakage from the thin tunnel insulating film 13.
[0020]
With this configuration, a 2F × 2F size DT memory cell is realized while preventing leakage between the source / drain 18 and the floating gate 15 and maintaining the reliability of data retention.
[0021]
A write operation to the DT memory cell 20 is performed by applying a voltage of about 5 V to the selected word line (control gate electrode) and a voltage of about 1 V to the selected bit line (drain) 18 to form a channel. Electrons are injected into the floating gate 15 by direct tunneling through the tunnel insulating film 13. In the erasing operation, the control electrode is set to −5 V, an erasing voltage of 0 V is applied to the bit line 18 connected to the source, and the charge is extracted from the floating gate 15 to the substrate. Since the tunnel insulating film 13 is thin, the applied voltage is lower and the operation speed is faster than the conventional floating gate type flash memory.
[0022]
Next, a method for manufacturing such a DT memory will be described.
<First Embodiment>
4 to 7 show a manufacturing process of the DT memory according to the first embodiment of the present invention. The manufacturing process is illustrated as a cross-sectional configuration along the line A-A ′ in FIG. 2.
[0023]
First, as shown in FIG. 4A, a tunnel insulating film 13 having a thickness of about 2 nm is formed on a silicon substrate 11 by thermal oxidation. A polysilicon film having a thickness of 150 nm is deposited on the tunnel insulating film (thermal oxide film) 13 by a CVD method, an oxide film is further deposited by a CVD method to a thickness of 120 nm, and then a floating gate pattern is formed by lithography and etching by an RIE method. Form. By this patterning, the floating gate 15 and the oxide film hard mask 21 covering the floating gate 15 remain on the tunnel insulating film 13. After forming the floating gate pattern, a thin thermal oxide film 24 is formed on the entire surface, and then a nitride film is deposited on the entire surface by CVD. The dummy nitride film 23 remains on the sidewalls of the floating gate 15 and the oxide film hard mask 21 by etching back the nitride film by the entire surface RIE method.
[0024]
Next, as shown in FIG. 4B, using the oxide film hard mask 21 and the dummy nitride film 23 as a mask, the silicon substrate 11 is etched by RIE by self-alignment to have a depth of 200 nm to 400 nm, preferably A trench 25 having a thickness of about 300 nm to 400 nm is formed.
[0025]
Next, as shown in FIG. 5C, an insulating film (for example, an oxide film) 27 is deposited by the CVD method so as to cover the entire surface of the trench 25, the oxide film hard mask 21, and the dummy nitride film.
[0026]
Next, as shown in FIG. 5D, the entire surface of the insulating film 27 is etched by the RIE method so that the insulating film remains only in the trench 25 and the trench type (or buried type) element isolation region 12 is formed. Form. At this time, the etching is controlled so that the upper side wall of the trench 25 is exposed to about 50 nm to 80 nm to provide the side wall exposed surface 26. In the first embodiment, since an oxide film is used as the insulating film 27, the oxide film hard mask 21 is also removed at the time of etching by RIE.
[0027]
Next, as shown in FIG. 6E, oblique ion implantation is performed on the sidewall exposed surface 26 of the trench 25. The implanted impurity ions are diffused by a subsequent heat treatment to form source / drain diffusion regions 28 along the upper side wall of the trench 25. Inclined ion implantation uses an acceleration energy of 20 KeV and a dose of 4 × 10.¹⁵Perform at cm-2.
[0028]
Next, as shown in FIG. 6F, the dummy nitride film 23 is removed by wet etching with hot phosphoric acid. Further, the thin oxide film 24 remaining on the side wall of the floating gate electrode 15 and the silicon substrate is once removed with a hydrofluoric acid-based etchant.
[0029]
  Next, figure7As shown in (g), a gate thermal oxide film 16 is formed on the entire surface with a thickness of about 8 nm by thermal oxidation. This gateheatOxide film16Is a film for insulating the floating gate 15 and the control gate electrode formed in the next process as the second insulating film.
[0030]
  Next, figure7As shown in (h), polysilicon is deposited to a thickness of 50 nm on the entire surface by CVD, and the polysilicon is patterned into the shape of a word line by lithography and etching to form a control gate electrode (or word line) 17. Form.
[0031]
According to such a method of manufacturing a DT memory, a trench type element isolation region is formed by self-alignment using a hard mask covering a floating gate and a dummy sidewall nitride film as a mask, and a source / source region is formed along the upper sidewall of the trench. A drain region is formed. The source / drain regions along the trench sidewall do not overlap with the floating gate electrode. Therefore, while preventing leakage from the tunnel insulating film and holding the charge in the floating gate, 4F² A memory cell of a size is realized.
<Second Embodiment>
Next, a manufacturing process of the DT memory according to the second embodiment of the present invention will be described.
[0032]
In the first embodiment, 4F² In order to realize the cell, as a method of forming the source / drain diffusion region along the upper side wall of the trench type element isolation region, the thick insulating film once filled with the trench was etched back and oblique ion implantation was performed. However, it may be difficult on the control surface to control the etching of the oxide film to partially expose the sidewall of the trench by a predetermined depth after the trench is filled with the oxide film.
[0033]
Therefore, in the second embodiment, 4F² Provided is a process for forming a source / drain diffusion region with better controllability while maintaining the cell size.
[0034]
In order to achieve this object, first, a first trench having a depth necessary for forming a source / drain is formed in a substrate, and an impurity diffusion region is formed by ion implantation and thermal diffusion. Thereafter, the trench is further deeply etched to form a second trench, and the impurity diffusion regions are separated from the left and right upper sidewalls of the second trench to form source / drain diffusion regions. Thereafter, an oxide film is buried in the second trench to form an element isolation region.
[0035]
8 to 11 are views showing a manufacturing process of the DT memory according to the second embodiment. Also in the second embodiment, a manufacturing process is shown as a cross-sectional configuration along the line A-A ′ of FIG. 2. The same components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
[0036]
First, as shown in FIG. 8A, a polysilicon floating gate 15 and an oxide film hard mask covering the upper surface of the floating gate 15 are formed on the silicon substrate 11 via a tunnel insulating film 13 having a thickness of about 2 nm. 21 and a dummy nitride film 23 covering the sidewalls of floating gate 15 and oxide film hard mask 21 through thermal oxide film 24. Up to this point, the process is the same as that shown in FIG. 4A of the first embodiment, and a detailed method of forming each component is omitted. The thickness of the dummy nitride film 23 is 4F² The position of a trench type element isolation region for realizing a memory cell of a size is determined. This dummy nitride film is anisotropically etched to form a dummy nitride film having a predetermined thickness on the side wall of the floating gate 15 Remains.
[0037]
Next, as shown in FIG. 8B, the first trench 45 is formed by etching to the depth of 0 to 200 nm from the surface of the silicon substrate 11, for example, by an amount necessary for forming the source / drain by RIE. To do. In FIG. 8B, the depth is set to 80 nm as an example, but the depth of the first trench is also related to the characteristics of the transistor and is not necessarily limited to this value. Since the trench formation on the silicon substrate can be strictly controlled, it can be set to a desired depth in the range of 0 to 200 nm according to the design. The first trench 45 is formed by self-alignment by the RIE method using the oxide hard mask 21 and the dummy nitride film 23 covering the floating gate 15 as a mask.
[0038]
Next, as shown in FIG. 9C, ion implantation is performed on the first trench 45. In the second embodiment, for example, ion implantation is performed vertically. In the case of vertical implantation, power can be applied to ion implantation. However, oblique ion implantation may be performed in the first trench 45. This is because the depth of the first trench formed in the substrate is accurately controlled, so that the region to be ion-implanted by the tanning can be accurately determined. Impurities implanted by the subsequent thermal process diffuse in the horizontal direction, and an impurity diffusion region 38 extending from the side wall of the first trench 45 is formed. Also, ions diffuse from the bottom surface of the first trench 45 to form an impurity diffusion region 38 ′. In the case of vertical ion implantation, the acceleration energy is 60 KeV and the dose amount is 4 × 10.¹⁵cm^-2It is.
[0039]
Next, as shown in FIG. 9D, the first trench 45 is etched deeper by the RIE method using the oxide film hard mask 21 and the dummy nitride film 23 as a mask to form the second trench 55. The second trench 55 is further dug down in the depth direction from the bottom surface of the first trench 45 and finally has a depth of about 200 nm to 400 nm, more preferably a depth of 300 nm to 400 nm in a state where the first trench is absorbed. It is formed. By forming the second trench 55, the impurity diffusion region 38 ′ that has spread from the bottom surface of the first trench 45 in the previous step is removed, and the impurity diffusion region 38 that diffuses from the upper side wall of the second trench 55 is separated to the left and right. The The impurity diffusion region 38 remaining along the side wall of the second trench becomes the source / drain diffusion region 38 of the DT memory and becomes a bit line. Since the impurity diffusion region formed on the bottom surface of the first trench in the previous step is removed together with the formation of the second trench, power control at the time of ion implantation is not necessarily strictly performed.
[0040]
Next, as shown in FIG. 10E, an insulating film 49 covering the inside of the second trench 55 and the entire surface of the substrate is formed by the CVD method. The insulating film 49 is formed of an oxide film, for example.
[0041]
Next, as shown in FIG. 10F, the insulating film 49 is etched back by the RIE method to leave the insulating film only inside the second trench 55. Thereby, the element isolation region 12 is formed.
[0042]
Next, as shown in FIG. 11G, the dummy nitride film 23 is removed by wet etching using hot phosphoric acid. After the thin oxide film 24 remaining on the side wall of the floating gate 15 is once removed with a hydrofluoric acid-based etchant, a gate insulating film (second insulating film) 16 having a thickness of about 8 nm is formed again on the entire surface by thermal oxidation.
[0043]
Next, as shown in FIG. 11 (h), polysilicon is deposited to a thickness of 50 nm on the entire surface by CVD, and the polysilicon is patterned into the shape of a word line by lithography and etching to control gate electrodes (or Word line) 17 is formed.
[0044]
According to the method of the second embodiment, after embedding a trench for element isolation, it is not necessary to etch back the thick insulating film to partially expose the trench sidewall. In addition, it is not always necessary to employ oblique ion implantation for forming the source / drain diffusion regions, and both the control of etch back and the control of ion implantation for forming the source / drain are facilitated.
[0045]
Furthermore, since the formation of the first trench and the second trench in the silicon substrate can be accurately controlled, the source / drain regions along the upper side wall of the trench can be formed with good controllability by a simple process. As a result, 4F² A memory cell of a size can be realized by a simple process.
[0046]
In addition, since the source / drain diffusion regions are formed by utilizing the thermal diffusion in the lateral direction from the first trench, the diffusion region extending from the bottom surface of the first trench is completely removed simultaneously with the formation of the second trench. Matching memory cells can be reliably separated.
[0047]
As described above, the DT memory using the direct tunnel phenomenon has been described based on the embodiments, but the present invention is not limited to these examples. The depth of the first trench is not limited to 80 nm, and can be appropriately set in the range of 0 nm to 200 nm. When the depth of the first trench is set to 0 nm, ion implantation is performed on the substrate surface without forming the first trench. An impurity diffusion region extending to below the dummy nitride film is formed by spreading the impurities in the horizontal direction and subsequent thermal diffusion. Thereafter, an element isolation trench having a desired depth is formed by a single etching, and the impurity diffusion region remaining along the upper sidewall of the trench can be used as a source / drain diffusion region.
[0048]
The depth of the second trench is preferably in the range of 200 nm to 400 nm, but can be set to an arbitrary depth necessary for element isolation in other ranges. Increasing the depth of the trench type element isolation region increases the effective inter-element distance. However, there is a balance with miniaturization in manufacturing, and the thickness is set to 200 nm to 400 nm, and more preferably 300 nm to 400 nm.
[0049]
The thickness of the second insulating film is not limited to the thickness described in the embodiment as long as the leakage current between the floating gate electrode and the control gate electrode can be prevented. When an oxide film is used as the second insulating film, it is excellent in denseness, so that the film thickness can be appropriately set in the range of 6 to 10 nm.
[0050]
Alternatively, the impurity concentration distribution of the floating gate electrode may be changed. That is, by reducing the impurity concentration in the vicinity of the tunnel insulating film in the floating gate, the amount of charges held in the floating gate tunneling in the substrate direction may be reduced, and the leakage prevention effect may be enhanced.
[0051]
In the embodiment, the dummy sidewall is a silicon nitride film and the trench insulating film is a silicon oxide film. Conversely, the dummy sidewall may be formed of a silicon oxide film, and the trench may be embedded with a silicon nitride film. Good.
[0052]
Finally, the following notes are disclosed regarding the above description.
(Appendix 1) a semiconductor substrate;
A trench type element isolation region formed in a semiconductor substrate;
A tunnel insulating film located on a semiconductor substrate in a region partitioned by the element isolation region;
A floating gate electrode located on the tunnel insulating film;
A second insulating film covering the floating gate electrode;
A control gate electrode located on the second insulating film;
A source / drain diffusion region extending along the upper side wall of the trench type element isolation region so as not to overlap the floating gate electrode;
A semiconductor memory device comprising:
(Appendix 2) A step of forming a tunnel insulating film on a semiconductor substrate;
Forming a floating gate electrode on the tunnel insulating film;
Forming a dummy insulating film located on a sidewall of the floating gate electrode;
Ion implantation using a dummy insulating film as a mask, and forming an impurity diffusion region extending below the dummy insulating film;
Forming a trench having a depth necessary for element isolation using a dummy insulating film as a mask, and making the impurity diffusion region remaining along the upper sidewall of the trench a source / drain diffusion region;
Forming a device isolation region by filling the trench;
Removing the dummy insulating film to form a second insulating film covering the floating gate electrode;
Forming a control gate electrode on the second insulating film;
A method for manufacturing a semiconductor memory device.
(Appendix 3) A step of forming a tunnel insulating film on a semiconductor substrate;
Forming a floating gate electrode on the tunnel insulating film;
Forming a dummy insulating film located on a sidewall of the floating gate electrode;
Forming a first trench having a required depth in the source / drain diffusion region using the dummy insulating film as a mask;
Forming a source / drain diffusion region along the sidewall of the first trench;
Forming a second trench having a depth necessary for element isolation from the bottom surface of the first trench, embedding an insulating film in the second trench, and forming a trench type element isolation region;
Removing the dummy insulating film and forming a second insulating film covering the floating gate electrode;
Forming a control gate electrode on the second insulating film;
A method for manufacturing a semiconductor memory device.
(Additional remark 4) The said 1st trench is formed in the depth of 0 nm-200 nm from the surface of a semiconductor substrate, The manufacturing method of the semiconductor memory device of Additional remark 3 characterized by the above-mentioned.
(Supplementary note 5) The method of manufacturing a semiconductor memory device according to supplementary note 3, wherein the source / drain diffusion step into the first trench sidewall includes an ion implantation step into the first trench.
(Additional remark 6) The manufacturing method of the semiconductor memory device of Additional remark 4 characterized by using the diffusion to the horizontal direction of the said ion to implant the source / drain diffusion process to the 1st trench side wall.
(Additional remark 7) The manufacturing method of the semiconductor memory device according to Additional remark 5 or 6, wherein the ion implantation into the first trench is vertical implantation.
(Supplementary note 8) The supplementary note 2 or 3, wherein the thickness of the dummy insulating film located on the side wall of the floating gate electrode is set to a thickness that does not overlap the source / drain diffusion region and the floating gate electrode. A manufacturing method of the semiconductor memory device described.
[0053]
【The invention's effect】
As described above, according to the present invention, 4F² A cell-sized DT memory device is realized.
[0054]
Further, according to the manufacturing method of the second embodiment, it is not necessary to control the etching of the oxide film in order to partially expose the sidewall of the trench. Since the first trench may be formed by etching the substrate by an amount necessary for forming the source / drain diffusion regions, the controllability for forming the source / drain regions is improved.
[0055]
Further, it is not necessary to control the angle of ion implantation into the first trench, and since the element isolation region is formed by further digging the first trench after the ion implantation, the source / drain region can be reliably separated.
[0056]
Overall, 4F efficiently without difficult control² A cell-sized DT memory can be realized.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration example of a conventional direct tunneling memory (DTM) element.
FIG. 2 shows 4F according to the present invention.² It is a plane block diagram of DT memory of a cell.
3 is a diagram showing a configuration of a DT memory device of the present invention, and is a cross-sectional view taken along the line A-A ′ of FIG. 2;
FIG. 4 is a manufacturing process diagram (No. 1) of the DT memory according to the first embodiment of the invention;
FIG. 5 is a manufacturing process diagram (No. 2) of the DT memory according to the first embodiment of the invention;
FIG. 6 is a manufacturing process diagram (No. 3) of the DT memory according to the first embodiment of the invention;
FIG. 7 is a manufacturing process diagram (No. 4) of the DT memory according to the first embodiment of the invention;
FIG. 8 is a manufacturing process diagram (No. 1) of a DT memory according to a second embodiment of the invention;
FIG. 9 is a manufacturing process diagram (No. 2) of the DT memory according to the second embodiment of the invention;
FIG. 10 is a manufacturing process diagram (No. 3) of the DT memory according to the second embodiment of the invention;
FIG. 11 is a manufacturing process diagram (No. 4) of the DT memory according to the second embodiment of the invention;
[Explanation of symbols]
10 Direct tunnel (DT) memory (semiconductor memory device)
11 Silicon substrate (semiconductor substrate)
12 Trench type element isolation region
13 Tunnel insulating film
15 Floating gate electrode
16 Second insulating film
17 Control gate electrode
18, 28, 38 Source / drain diffusion regions
21 Oxide hard mask (dummy insulating film)
23 Dummy nitride film (dummy insulating film)
24 Thermal oxide film
25 trench
26 Side wall exposed surface
45 First trench
55 Second trench

Claims (4)

A semiconductor substrate;
A trench-type element isolation region formed in the semiconductor substrate and a tunnel insulating film located on the semiconductor substrate in a region partitioned by the element isolation region;
A floating gate electrode located on the tunnel insulating film;
A second insulating film covering the floating gate electrode and the trench type element isolation region, wherein an upper surface of the second insulating film of the trench type element isolation region is located below an upper surface of the semiconductor substrate; A second insulating film;
A control gate electrode located on the second insulating film;
A source / drain diffusion region extending along the upper side wall of the trench type element isolation region so as not to overlap the floating gate electrode ,
The semiconductor memory device, wherein the second insulating film is in contact with the semiconductor substrate for a predetermined distance from an end of the floating gate electrode to an end of the source / drain diffusion region . Forming a tunnel insulating film on the semiconductor substrate;
Forming a floating gate electrode on the tunnel insulating film;
Forming a dummy insulating film located on a sidewall of the floating gate electrode;
Forming a trench having a depth necessary for element isolation using the dummy insulating film as a mask;
Using the dummy insulating film as a mask, implanting ions obliquely into the sidewall of the trench to form an impurity diffusion region extending to the lower side of the dummy insulating film;
Forming the impurity diffusion region remaining along the upper sidewall of the trench as a source / drain diffusion region;
Forming a device isolation region by filling the trench;
Removing all the dummy insulating film, covering the floating gate electrode and forming a second insulating film so as to be in direct contact with the floating gate electrode ;
Forming a control gate electrode on the second insulating film;
A method for manufacturing a semiconductor memory device. Forming a tunnel insulating film on the semiconductor substrate;
Forming a floating gate electrode on the tunnel insulating film;
Forming a dummy insulating film located on a sidewall of the floating gate electrode;
Forming a first trench having a required depth in the source / drain diffusion region using the dummy insulating film as a mask;
Forming a source / drain diffusion region along the sidewall of the first trench;
A trench-type element isolation region is formed by forming a second trench having a depth necessary for element isolation from the bottom surface of the first trench and filling the second trench with an insulating film up to a portion located below the upper surface of the semiconductor substrate. Forming a step;
Removing the dummy insulating film to form a second insulating film covering the floating gate electrode;
Look including a step of forming a control gate electrode on the second insulating film,
The method of manufacturing a semiconductor memory device, wherein the first trench is formed at a depth of 0 nm to 200 nm from the surface of the semiconductor substrate .   4. The method of manufacturing a semiconductor memory device according to claim 3, wherein the source / drain diffusion step into the first trench side wall includes an ion implantation step into the first trench.

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