KR100456256B1 - Semiconductor device and its manufacturing method - Google Patents

Abstract

Provided are a semiconductor device having a small device separation width while ensuring reverse breakdown voltage and punch through breakdown voltage, and a method of manufacturing a semiconductor device which can easily and reliably manufacture such a semiconductor device without using a complicated process.

Source and drain regions of adjacent elements requiring device isolation are formed as impurity diffusion layer lines having a common width under the isolation grooves. Then, patterning is performed for separation of the first conductive film covering the gate insulating film and the separation insulating film. At the same time, through the isolation insulating film in the same pattern using the internal etching film used here, etching is performed to the substrate, and an element isolation groove (trenches) is formed in the substrate, and the impurity diffusion layer formed in the substrate through the element isolation groove. The line is divided to form a source line and a drain line.

Description

Semiconductor device and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices such as EEPROM (Electrically Erasable Programmable ROM) and a manufacturing method thereof.

Recently, the development of nonvolatile memory capable of electrically writing and erasing such as EEPROM is in full swing. In addition, a flash memory that can achieve high density at a low cost is attracting attention. Among the flash memories, a flash EEPROM having a memory array configuration as shown in Fig. 16 is known. In the flash EEPROM, the memory transistors MTr are arranged in a matrix form, the bit lines (drain lines) BL and the source lines SL are arranged in the longitudinal direction of the drawing, and the memory transistors MTr in the longitudinal direction of the drawing are arranged. ) Share these bit lines BL and source lines SL. The word line (control gate) WL is arranged orthogonal to the bit line BL, and constitutes a control gate of each memory transistor MTr. The memory transistors MTr in the word line WL direction are separated from each other.

Such writing and erasing of the memory is performed by injecting electrons into the floating gate FG to write data by using a Fowler Nordheim tunneling using the front surface of the channel with the control gate WL as a positive bias, while the control gate WL is written. ) Is erased by extracting electrons from the floating gate FG as a negative bias. This approach has several advantages over other approaches.

For example, compared with the CHE (Channel Hot Electron) injection method, since the power consumption at the time of writing is small, writing by the internal boost circuit can be speeded up.

In terms of the number of writes, it is known that it is advantageous to perform F-N tunneling injection on the entire channel for both writing and erasing.

Even in a system in which electrons are extracted from the floating gate by F-N tunneling and data is erased, the inter-band tunnel current flows at the time of data writing, thereby causing a problem in the writing speed due to internal boosting.

Moreover, it is advantageous in that random access is faster as compared with the NAND type using F-N tunneling injection on the same channel front.

An example of a conventional method for manufacturing a memory cell having the features described above will be briefly described with reference to the drawings. 14 is a cross-sectional view of the process, and FIG. 15 is a plan view thereof.

First, as shown in FIG. 14A, the device isolation region 200 is formed in the semiconductor substrate 100 using the LOCOS method.

Next, as shown in Figs. 14B and 15A, the pad oxide film 202 and the silicon nitride film 203 are formed to form a portion of the channel region using photolithography and dry etching. Pattern to cover. At this time, polycrystalline silicon may be formed between the pad oxide film 202 and the silicon nitride film 203 to relieve stress of the silicon nitride film 203. Subsequently, the impurity diffusion layer 101 is formed by ion implantation of phosphorus or arsenic using the silicon nitride film 203 as a mask.

Next, when thermal oxidation is performed, since the silicon nitride film 203 becomes an oxidation mask, a relatively thick oxide film 204 is formed as shown in Figs. 14 (b) and 15 (b). At this time, a drain line (bit line) 102 and a source line 103 are formed under the oxide film 204.

Next, as shown in Figs. 14 (d) and 15 (c), the silicon nitride film and the pad oxide film are peeled off to expose the channel region.

Subsequently, as shown in FIG. 14E, thermal oxidation is performed to form a tunnel oxide film 205.

Next, as shown in Fig. 14F, polycrystalline silicon 301 serving as a floating gate is formed and patterned. At this time, as shown in Fig. 15D, the polycrystalline silicon is not cut in the extending direction of the bit line (BB 'direction in the drawing). Subsequently, ion implantation is performed to form the channel stopper. In order to ensure reverse breakdown voltage, the injection amount needs to be a high concentration of about 10 ¹⁷ / cm 3. In addition, the channel stopper 104 needs to make a gap with the bit line 103 or the source line 102 in order to secure the junction breakdown voltage. This ion implantation can be shared with the mask at the time of forming the floating gate 301, but is diffused by heat during formation of the ONO film (three-layer film of silicon oxide, silicon nitride, and silicon oxide film) formed on the floating gate 301. In order to prevent this, after the ONO film is formed, ion implantation may be performed again through a photolithography step.

Next, after the ONO film 206 is formed, the polycrystalline silicon 302 serving as the control gate is deposited, a resist film is formed and patterned, and then the control gate 302, the ONO film 206 and the floating gate ( 301 is etched at a time. Again, using the resist at the time of control gate formation as a mask, memory cells adjacent to each other in the bit line direction B-B 'are separated by boron ion implantation. As a result, a memory cell having a structure as shown in Figs. 14 (g) and 15 (e) can be obtained.

However, in the above-described method, since a high voltage of about 20 V is required at the time of writing, it is possible to secure the breakdown withstand voltage and the punch through withstand voltage in element isolation between memory cells adjacent to the bit line. There is a problem that it becomes difficult.

In the separation by the LOCOS method or the like, when the LOCOS film thickness is made thick in order to secure the reverse breakdown voltage, the separation width is increased by the width of the birds beak due to the dimensional conversion difference, and the degree of integration decreases.

It is conceivable to employ trench isolation with a large punch-through pressure instead of LOCOS.However, in order to simultaneously form a large separation region and a small separation region, a special process technique such as chemical mechanical polishing (CMP) may be used. There is a problem that a complicated landfill planarization process is required, resulting in an increase in cost.

In addition, it is also possible to increase the concentration of the channel stopper. However, in order to secure the junction breakdown voltage, it is necessary to provide a gap between the source and drain regions and the channel stopper ion implantation region. It throws away and causes the fall of density.

Disclosure of Invention The present invention has been made to solve the above-described problems, and the semiconductor device having a small element separation width and a semiconductor device which can be manufactured easily and reliably without using complicated processes while ensuring reverse breakdown voltage and punch through breakdown voltage. An object of the present invention is to provide a method for producing the same.

The present invention provides a semiconductor substrate, a gate insulating film formed on the surface of the semiconductor substrate, a separation insulating film formed on both sides of the gate insulating film, an impurity diffusion layer formed on a substrate under the separation insulating film, A semiconductor device having a first conductive film formed over the isolation insulating film, and a device isolation groove which is formed through the isolation insulating film and the impurity diffusion layer, respectively, and is filled with an insulating material.

Also, in order to achieve the above object, the present invention provides a process for forming a plurality of impurity diffusion layer lines extending along each other in a semiconductor substrate, forming a separation insulating film over a region of the impurity diffusion layer lines, and the impurity diffusion lines. Forming a gate insulating film in the region between the layers, forming a mask layer covering the gate insulating film and the isolation insulating film, forming a etched layer on the mask layer, and patterning the etched layer. And etching the mask layer, the isolation insulating film, and the substrate using the patterned etched layer as a mask, thereby forming an element isolation groove for dividing the impurity diffusion layer line to form a source line and a drain line on the substrate; Provided is a method for manufacturing a semiconductor device, comprising the step of filling the device isolation groove with an insulating material. . The mask layer is for protecting the underlying gate insulating film and the insulating insulating film when etching the insulating material formed on the inside and the upper portion of the device isolation groove, and the insulating material and the etching selectivity are taken, for example, a second conductive film (polycrystal Silicon) or the like.

In the semiconductor device of the present invention, device isolation between devices having a structure in which a substrate and a first conductive film face each other via a gate insulating film, and a diffusion layer is formed under the isolation insulating films on both sides of the gate insulating film is separated from the first conductive film. The insulating film and the diffusion layer are formed in a device isolation groove (trench) that penetrates and is dug into the substrate.

Therefore, since the isolation | separation required element is isolate | separated by the trench isolation | separation which has high reverse breakdown voltage and punch through breakdown voltage, and small separation width | variety, integration density can be improved, ensuring reverse breakdown voltage and punchthrough breakdown voltage. In addition, since trench isolation is used only in a memory area having a small separation width, and a LOCOS method can be used for a peripheral circuit requiring a large separation width, a difficult process such as filling a wide groove is avoided. Can prevent the cost increase.

In addition, in the method of manufacturing a semiconductor device of the present invention, first, source and drain regions of adjacent elements requiring element isolation are formed as impurity diffusion layer lines having a common width under the isolation grooves. Then, patterning is performed for separation of the first conductive film covering the gate insulating film and the separation insulating film. At the same time, through the separation insulating film in the same pattern using the anti-etching film used here, the substrate is etched, an element isolation groove (trenches) is formed in the substrate, and the impurity diffusion layer line formed in the substrate is formed by the element isolation groove. By dividing, a source line and a drain line are formed.

Therefore, trench isolation with a high reverse breakdown voltage and a punch through breakdown voltage and a small separation width can be formed at the same time as the patterning of the first conductive film, so that it is possible to reliably separate the elements without increasing the memory cell area in an extremely easy process. Can be done. In addition, since the trench isolation is adopted only in the memory area, for example, and the LOCOS can be employed in the peripheral circuit requiring a large separation width, for example, the separation process is difficult. It can be avoided and the cost increase can be suppressed.

Hereinafter, although the Example of this invention is described concretely, this invention is not limited to the following Example.

1 illustrates an embodiment of a semiconductor device of the present invention, and is an example of application to a separate source type. (a) is sectional drawing, (b) is top view, and is sectional drawing along the A-A line of (a) and (b). In addition, the circuit is shown in FIG.

Referring to the cross-sectional structure of the semiconductor device, a gate insulating film 21 having a film thickness of about 10 nm is formed on the surface of the substrate 10 and a separation insulating film 23 having a film thickness of about 30 to 100 nm is formed on both sides thereof. have. Impurity diffusion layers (source, drain) 12 and 13 are formed in the substrate 10 below the isolation insulating film 23. The first conductive film 31 is stacked on the gate insulating film 21 and the isolation insulating film 23 to form a floating gate. An element isolation groove 40 is formed in the substrate in the region where the first conductive film 31, the isolation insulating film 23, and the impurity diffusion layers 12 and 13 are separated. The element isolation groove 40 has an oxide film 25 formed on its inner wall and is filled with an insulating material 26. The upper surface of the insulating material 26 is almost the same height as the element isolation groove 40. Moreover, the channel stopper 14 is formed in the board | substrate below the element isolation | separation groove 40, and the separation | separation is completed completely. The ONO film 27 is formed over the said 1st conductive film 31, for example, and the 1st conductive film 31 is insulated from the circumference | surroundings by this. In addition, a second conductive film 32 is formed on the ONO 27, and the second conductive film 32 forms a control gate.

Next, the planar structure will be described. The second conductive film 32 extends in the left and right directions in the drawing and constitutes a word line WL. The bit line BL (drain 12) and the source line SL (source 13) extend in parallel with the word line WL in parallel. The memory transistors MTr1 to MTr4 are formed at a portion where the word line WL and the gate insulating film 21 cross each other, and the floating gate 31 is provided below the word line WL of the memory transistor. The trench isolation TI (element isolation groove 40) separates the source line SL and the bit line BL to separate memory transistors adjacent to the word line WL direction from each other. In the meantime, the memory transistors arranged in the vertical direction in the drawing share the bit line BL and the source line SL.

2, the pair of source lines SL and the bit lines (drains) BL are parallel, and the pair of source lines SL and the bit lines BL are shared. A plurality of memory transistors (MTr2 and MTr4 and MTr1 and MTr3 in the figure) are provided along the source line SL and the bit line BL. The word line WL is provided orthogonal to the bit line BL, and each constitutes a control gate of the memory transistor. The memory transistors (columns orthogonal to the bit lines) in the direction of the word lines WL that do not share the source lines SL and the bit lines BL divide the bit lines BL and the source lines SL. It is separated by the element isolation groove (trench) TI.

This memory writing and erasing, for example, injects electrons into the floating gate 31 and the FG to write data by FN tunneling using the entire surface of the control gate 32 and WL with a positive bias of about 20 V. On the other hand, erasing is performed by extracting electrons from the floating gate 31 and the FG using the control gate 32 and WL as negative biases.

The semiconductor device is trench-separated by element isolation grooves 40 and TI which are deep between the memory elements MTr1 and MTr2 adjacent to the word line WL direction and between the memory elements MTr3 and MTr4. Therefore, much higher reverse breakdown voltage and punch through breakdown pressure can be obtained than the LOCOS method. Therefore, no problem occurs even when a high bias voltage is applied to the control gate and the WL 32 during writing. In addition, unlike LOCOS, since there is no buzz beak to widen the isolation region, the device isolation region can be made smaller and the degree of integration can be improved.

An example of the manufacturing method of the semiconductor device mentioned above is demonstrated in FIGS. In addition, (a) is sectional drawing in each drawing, (b) is a top view.

First, as shown in FIG. 3, a pad oxide film 21 and then a silicon nitride film 22 are deposited on the silicon substrate 10, and patterned using photolithography and dry etching. In this case, polycrystalline silicon may be formed between the pad oxide film 21 and the silicon nitride film 22 to relieve stress of the silicon nitride film 22. In addition, before this step, LOCOS is formed in circuit portions other than memory cells such as peripheral circuits. Subsequently, phosphorus or arsenic is ion-implanted using the silicon nitride film 22 as a mask to form the impurity diffusion layer line 11. The impurity diffusion layer line 11 is later divided into element isolation grooves to constitute a source and a drain.

Next, as shown in FIG. 4, an oxide film (separation insulating film) 23 is formed by thermal oxidation using the silicon nitride film 22 as a mask. The film thickness of the oxide film 23 may be a thickness such that electrons do not pass through. Specifically, it is preferable to be thinner than the thickness of normal LOCOS and to be about 30 to 100 nm. The impurity diffusion layer line 11 is buried under the oxide film 23 to become a buried diffusion layer.

5, the silicon nitride film 22 and the pad oxide film 21 are peeled off, and then thermally oxidized to form the tunnel oxide film 24 with a film thickness of, for example, about 10 nm.

Then, as shown in FIG. 6, the 1st conductive layer 31 used as a floating gate is deposited by CVD method etc. of polycrystalline silicon. Next, the resist R1 is applied by spin coating or the like, and after the resist R1 is patterned by photolithography, the first conductive layer 31 is patterned using the resist R1 as an etching layer. At this time, as shown in FIG. 6 (b), the center portion of the oxide film 23 in the width direction of the impurity diffusion layer line 11 is not cut in the extending direction of the impurity diffusion layer line 11 (BB direction in the drawing). Etch in the extending direction.

Subsequently, in the present invention, as shown in FIG. 7, the oxide film 23 and the substrate 10 are continuously etched again using the resist R1 as a mask, so that the element isolation grooves (trench) 40 are formed in the substrate. Form. As a result, the impurity diffusion layer line 11 is divided by the separation groove 40 so that the source line 12 and the bit line 13 are formed in a self-aligned manner.

After the device isolation groove 40 is formed, ion implantation is performed as necessary to form the channel stopper 14. In this case, since the source and the drain are continuous in this embodiment, it is not necessary to ion implant into the sidewall of the separation groove from the viewpoint of sidewall inversion, and it is preferable to form the channel stopper 14 only on the bottom surface.

Next, as shown in FIG. 8, thermal oxidation is performed to form a thermal oxide film 25 on the inner wall of the separation groove 40, and then an insulating film 26 such as silicon oxide is deposited by CVD or the like. The separation groove 40 is filled with insulating material.

Next, as shown in FIG. 9, the insulating film 26 is etched back to expose the floating gate 23 and leave the insulating film 26 in the separation groove 40. At this time, it is preferable that the etching amount is sufficient to expose the side surface of the floating gate 23, and since this can increase the surface area of the floating gate 23, the coupling ratio is advantageous. In addition, in order to ensure insulation, the surface of the insulating film 26 filled with the separation groove after the etching back treatment needs to be higher than the surface of the silicon substrate 10, but since there is a margin equal to the thickness of the oxide film 23, Easy to control The thickness of the oxide film 23 should also be selected from this point of view.

Next, referring to FIG. 1, after forming the ONO film 27 having a thickness of about 20 nm, for example, polycrystalline silicon 32 serving as a control gate is deposited. After the resist film is formed, it is patterned to etch the polycrystalline silicon film 32 for the control gate, the ONO film 27 and the polycrystalline silicon 31 for the floating gate at once using the resist film as a mask. Again, boron ions are implanted using the same resist film as a mask, and memory cells adjacent to each other in the direction of the bit line 13 are separated. As a result, a memory cell region having a structure as shown in FIG. 1 can be obtained.

In Fig. 1B, one memory cell is shown with a broken line. If the minimum length is F, when the memory cells are arranged at the minimum pitch, a very small value of 6 F ² can be obtained.

According to this manufacturing process, since the isolation grooves are formed to be self-aligning with the same mask at the time of forming the floating gate, device isolation can be performed without increasing the memory cell area. In the above method, the LOCOS isolation method and the trench isolation method can be used in combination, and the LOCOS method is used for the separation width of the peripheral circuit and the like, and the trench isolation is used only in the narrow part of the memory cell, so that the separation width is wide. It is not necessary to use difficult and complicated processes for filling the places, for example, bias ECR, CVD, chemical mechanical polishing (CMP), selective epitaxial growth, and the like, and device separation can be performed in an extremely easy process.

In addition, although the cross-sectional shape of the element isolation | separation groove | channel 40 is etched vertically and is formed in substantially rectangular shape in the said example, as shown in FIG. . In FIG. 10, the same code | symbol is attached | subjected to the same member as the above. In the case of a normal trench, in order to avoid electric field concentration, it is preferable to have a tapered shape that gradually decreases in width as it goes to the bottom surface. The cross-sectional shape of the separation groove is preferably rectangular or tapered with a wide bottom surface. In forming the separation groove of such a shape, for example, it can be performed by controlling the gas ratio of the etching gas (for example, Cl ₂ and N ₂ ).

In addition, in the above description, the example applied to the separate source type is shown, but the semiconductor device of the present invention is not limited to this, and can be applied to, for example, a semiconductor device having a structure as shown in FIG. In the semiconductor device shown in FIG. 11, the gate insulating film 21 is formed on the surface of the semiconductor substrate 10, and the isolation insulating film 23 is formed on both sides of the gate insulating film 21. Impurity diffusion layers 12 and 13 are formed on the substrate under the isolation insulating film 23, and a first conductive film 31 is formed on the gate insulating film 21 and the isolation insulating film 23. In addition, an element isolation groove 40 is formed through the first conductive film 31 and the isolation insulating film 23 in a direction perpendicular to the substrate surface, and the element isolation groove 40 is filled with an insulating material 26. It is.

Next, an example in which the present invention is applied to an MNOS (Metal Nitride Oxide Semiconductor) type EEPROM will be described. The structure of the MNOS is, for example, as shown in FIG. 12, on which the silicon nitride film (trap insulation layer) 28 and the silicon oxide film 29 are laminated, for example, on the gate oxide film 21. The gate electrodes 33, such as polysilicon and aluminum, are laminated. In writing and erasing, a high voltage is applied to the gate insulating film 21 to allow a tunnel current to flow, and to trap electrons in the silicon nitride film.

This structure can be realized by the above steps. For example, it can be made the same to the process to FIG. However, since the 1st conductive film 31 is used in order to protect the oxide film 23, and it removes by a later etching, there exists no trouble other than polysilicon. In this case, if the ONO film is formed instead of the first conductive film 31, the ONO film is also etched at the same time during the etching back process when the device isolation groove 40 is filled with the insulating material 26. In addition, when the element isolation groove 40 is formed only by the pattern of the resist film directly without forming the first conductive film 31, the etching back treatment when the element isolation groove 40 is embedded with the insulating material 26 is formed. At this time, the oxide film 23 is etched this time. For this reason, some protective film, such as the 1st conductive film 31, is required. The film thickness of the gate oxide film (tunnel oxide film) may also be thinner than 10 nm.

From the state shown in FIG. 9, that is, the first conductive film 31 is patterned to form the device isolation groove 40, and then the device isolation groove 40 is embedded with the insulating material 26. The polysilicon film 31 is removed. As shown in FIG. 13, after the silicon nitride film 28 is formed to a film thickness of, for example, about 10 nm, the silicon nitride film 28 is thermally oxidized to form the silicon oxide film 29 as about 4 nm. It is formed into a film thickness. In addition, the formation process of this silicon oxide film 29 can also be skipped. Thereafter, a gate electrode film 33 such as polysilicon or aluminum is formed. The gate electrode film 33, the silicon oxide film 29, and the silicon nitride film 28 are patterned by etching to obtain an MNOS as shown in FIG.

The semiconductor device of the present invention has a high inversion breakdown voltage and a punch-through breakdown voltage, and a device isolation region having a small area occupied.

Moreover, according to the manufacturing method of the semiconductor device of this invention, such a semiconductor device can be manufactured easily and reliably.

1 illustrates an example in which the semiconductor device of the present invention is applied to a flash memory, in which (a) is a sectional view and (b) is a plan view.

FIG. 2 is a circuit diagram of the semiconductor device shown in FIG. 1. FIG.

3 shows an example of a manufacturing process of a semiconductor device of the present invention, where (a) is a sectional view and (b) is a plan view.

4 shows a subsequent process of FIG. 3, where (a) is a sectional view and (b) is a plan view;

FIG. 5 shows a subsequent process of FIG. 4, where (a) is a sectional view and (b) is a plan view. FIG.

FIG. 6 shows a subsequent process of FIG. 5, where (a) is a sectional view and (b) is a plan view; FIG.

FIG. 7 shows a subsequent process of FIG. 6, where (a) is a sectional view and (b) is a plan view. FIG.

8 shows a subsequent process of FIG. 7, where (a) is a sectional view and (b) is a plan view;

9 shows a subsequent process of FIG. 8, where (a) is a sectional view and (b) is a plan view;

10 is a cross-sectional view showing a modification of the semiconductor device of the present invention.

Fig. 11 is a sectional view showing the general structure of the semiconductor device of the present invention.

Fig. 12 is a sectional view showing the structure of an MNOS type nonvolatile memory.

13 is a sectional view showing an example in which the present invention is applied to MNOS.

14A to 14G are flowcharts illustrating, in cross-sectional view, a manufacturing process of a conventional flash memory;

15A to 15E are flowcharts illustrating the process of FIG. 14 in a plan view;

FIG. 16 is a circuit diagram of the flash memory shown in FIGS. 12 and 13;

<Explanation of symbols for the main parts of the drawings>

10: substrate

11: impurity diffusion layer line

12: source line

12: bit line (drain line)

14: channel stopper

23: separation insulating film

24: gate insulating film (tunnel oxide film)

27: ONO film

28 silicon nitride film (trap insulation layer)

29 silicon oxide film

31: first conductive film (floating gate)

32: second conductive film (control gate)

40: separation groove

WL: word line

BL: Bit line

SL: Source Line

MTr1 to MTr4: memory transistors

TI: Separation Groove

Claims (14)

In a semiconductor device, Semiconductor substrates; A gate insulating film formed on a surface of the semiconductor substrate; Isolation insulating films formed on both sides of the gate insulating film; An impurity diffusion layer formed on a substrate under the isolation insulating film; A first conductive film formed on the gate insulating film and the separation insulating film and used as a gate; And A device isolation groove formed by embedding an insulating material in at least a groove penetrating the separation insulating film and the impurity diffusion layer and reaching the inside of the substrate, The impurity region is divided by the device isolation groove, characterized in that the semiconductor device. The method of claim 1, An insulating film formed on the first conductive film; And A second conductive film formed on the insulating film, And the first conductive film is a floating gate, and the second conductive film constitutes a nonvolatile memory which is a control gate. The semiconductor device according to claim 1, wherein said device isolation groove is formed through said first conductive layer. The semiconductor device according to claim 1, wherein the impurity diffusion layer divided by the element isolation grooves constitutes source or drain lines of each of the memory elements adjacent to each other with respect to the element isolation grooves. 2. The semiconductor device according to claim 1, wherein a plurality of nonvolatile memory elements having the source line and the drain line in common are disposed along a direction in which the source line and the drain line extend. The insulating layer of claim 1, wherein an insulating layer including a silicon nitride film is formed on the isolation insulating film and the device isolation groove. And the first conductive film serving as a gate is formed on the insulating layer. The semiconductor device according to claim 1, wherein the device isolation groove has a cross-sectional shape that gradually widens toward an oblong or bottom portion. 2. The semiconductor device according to claim 1, wherein an impurity region serving as a channel stopper is formed at a bottom of the device isolation groove. 2. The device of claim 1, wherein the device isolation groove is used for separation between memory elements in a memory cell. A semiconductor device characterized in that element isolation by LOCOS is used in peripheral circuit portions other than memory cells. In the manufacturing method of a semiconductor device, Forming a plurality of impurity diffusion layer lines extending along each other in the semiconductor substrate; Forming a separation insulating film on a region of the impurity diffusion layer line; Forming a gate insulating film in a region between the impurity diffusion layer lines; Forming a mask layer covering the gate insulating film and the isolation insulating film; Forming an inner etching layer on the mask layer; Patterning the etching-resistant layer; Etching the mask layer, the isolation insulating film, and the substrate by using the patterned etched layer as a mask to form an element isolation groove for dividing the impurity diffusion layer line in the substrate to form a source line and a drain line; And And filling the device isolation groove with an insulating material. The method of claim 10, Forming an insulating film on the mask layer; Forming a conductive film on the insulating film; And And forming a pattern by simultaneously etching the conductive film, the insulating film, and the mask layer, The mask layer is a floating gate formed of a conductive material, The conductive film is a control gate, A method of manufacturing a semiconductor device, wherein the nonvolatile memory is formed by the above processes. 12. The method of claim 11, further comprising: forming an impurity diffusion separation layer for separating the memory cells in the direction of the impurity diffusion layer line of the nonvolatile memory after etching the floating gate, the insulating layer, and the control gate. The manufacturing method of the semiconductor device characterized by the above-mentioned. The method of claim 10, Removing the mask layer after the step of filling the device isolation groove with an insulating material; After the step of removing the mask layer, forming an insulating film including at least a silicon nitride layer on the gate insulating film, the isolation insulating film, and the device isolation groove; Forming a gate material layer on the insulating film; And Etching the gate material layer in a pattern; A method of manufacturing a semiconductor device, comprising forming a MNOS configuration by the above processes. The method of claim 10, In the process of filling the insulating material in the device isolation groove, After the insulating film layer for embedding in the element isolation groove is formed, the insulating film is etched back and controlled while controlling the surface after etching of the insulating film to be below the surface of the mask layer and above the surface of the isolation insulating film. The manufacturing method of the semiconductor device characterized by the above-mentioned.