JP4863935B2 - Electronic component package and manufacturing method thereof - Google Patents

Description

  The present invention relates to an electronic component package and a method for manufacturing the same.

  Many electronic devices are very sensitive and need to be protected from the harsh environment, including various contaminants present in the environment. An electronic component package having a hollow structure is one of the most effective means for providing such protection. By sealing the outer periphery of the hollow package, the environment of the electronic device existing in the package is kept airtight.

  Known hollow packages use metal, glass or ceramic, or sealing means such as solder or welding. For electronic devices that do not require perfect airtightness but require isolation from the environment, package structures, plastic capsules, molds, potting or polymer seals that provide some protection are used. To date, it has been necessary to make a compromise between a completely hermetic hollow package that provides maximum protection but at a high cost, and a hollow package that provides some protection but at a low cost.

  FIG. 14 shows the structure of the electronic component package described in Patent Document 1. The device substrate 1 on which the electronic device 2 is formed and the cover substrate 3 are hermetically joined by a seal portion 4 such as solder provided on the outer peripheral portion. The electronic device 2 is electrically connected to one end of a conductive path 5 formed through the cover substrate 3 while being enclosed in a hollow package constituted by the device substrate 1, the cover substrate 3, and the seal portion 4. In addition, it can be connected to an external device through an external connection terminal 6 provided at the other end of the conductive path 5.

This electronic component package is manufactured using a method of simultaneously sealing and electrically connecting a large number of electronic devices 2. In FIG. 15, reference numeral 101 denotes an apparatus wafer to be the above-described apparatus substrate 1, and a plurality of electronic devices 2 are formed thereon. Reference numeral 103 denotes a cover wafer serving as the above-described cover substrate 3, in which a plurality of conductive paths 5 arranged to face the plurality of electronic devices 2 are formed. The apparatus wafer 101 and the cover wafer 103 are joined together by a grid of the seal 4 material patterned around each electronic device 2, and at the same time, each electronic device 2 is connected to the corresponding conductive path 5. These electronic devices 2 are individually sealed and electrically connected together. Then, the bonded device wafer 101 and the cover wafer 103 are diced by the dicing line 7 and separated into electronic component packages each having the electronic device 2.
Japanese Patent No. 2820609

  However, in the conventional electronic component package structure described above, when the size of the chip (device substrate 1) is reduced and the number of chips per wafer (device wafer 101) is increased, the area of the sealing portion 4 for airtightness is increased. Since it becomes large and the load required for joining also becomes large, inconvenience arises. This will be described below.

  As shown in FIG. 15, the area of the seal part 4 per chip is expressed by the following formula when the chip size is Amm square, the width of the seal part 4 is Bmm, and the width of the dicing line 7 is Cmm. The

Seal area = (chip area on wafer) − (area other than seal area)
= (A + C) ^2- (A-2B) ²
For example, when the chip size is 6 mm square, the seal part width is 0.01 mm, and the dicing line width is 0.04 mm, the seal part area per chip can be calculated as 0.72 mm ² from the above formula. If the number of 6 mm square chips taken on a 4-inch wafer (φ100 mm) is 190, the seal area per wafer is about 140 mm ² .

Similarly, the seal area per wafer when the chip size is reduced to 1 mm square is obtained. If the seal part width and the dicing line width are the same as when the chip size is 6 mm square, the number of 1 mm square chips on a 4-inch wafer is 6400, for example, and the seal area is about 780 mm ² . This is an area that is 5 times or more of the chip size of 6 mm square.

Thus, when the chip size is reduced and the number of chips per wafer is increased, the area of the seal portion in the wafer surface is increased, and the load required for bonding is increased.
When gold (Au) is used as the material of the seal portion 4 (hereinafter referred to as a seal material), the applied pressure required to realize airtightness is about 0.25 GPa, and the 1 mm square chip is bonded to the wafer all at once. Requires a load of about 20 tons. Even if the variation in load is suppressed to 1% within the wafer surface, a partial offset load of 200 kg is partially applied, causing a problem of destruction of the electronic device 2. Even if no breakage occurs at the time of joining, damage may occur, and in that case, an inherent crack may develop and may lead to breakage. In either case, the reliability of the electronic device 2 is lowered. On the other hand, an insufficiently loaded portion occurs, resulting in poor continuity and airtight sealing, which may not satisfy the characteristics of the electronic device 2.

  In order to reduce the bonding load, it is conceivable that no sealing material is disposed on the dicing line 7 as shown in FIG. As a result, the area of the seal portion 4 is reduced, which is effective in reducing the load. However, since a gap is formed between the wafers 101 and 113 in the dicing line 7 portion, the load applied by the dicing blade 8 is not supported, and a structure in which chip cracks are likely to occur is obtained. When a chip crack occurs, the crack progresses and may break down.

  The present invention solves the above problems, and in an electronic component package formed by sealing a large number of electronic devices at the wafer level at the same time and then singulated, the electronic device is defective such as destruction, poor conduction, and insufficient sealing. It aims at suppressing.

In order to achieve the above object, a method of manufacturing an electronic component package according to the present invention includes a device substrate having a plurality of electronic devices and a cover substrate covering an electronic device forming surface of each of the device substrates. Are joined by the material of the first seal portion arranged so as to surround the periphery and form a gap between each other, to form a second seal portion covering a part of the outer peripheral surface of each of the first seal portions, The device substrate and the cover substrate are divided along a predetermined line passing through the second seal portion, the device substrate, and the cover substrate, and separated into electronic component packages each having the electronic device, and the first seal The portion has a multilayer structure including a first layer formed on the device substrate and a second layer formed on the cover substrate, and the widths of the first layer and the second layer are different from each other. The second seal portion is Serial to cover the outer peripheral surface width narrower one of the first layer and the second layer, characterized in that it does not cover the other of the outer peripheral surface.

  According to this, since the first seal portion is made as narrow as possible, the apparatus substrate and the cover substrate can be joined without requiring a large load, so that an airtight seal can be realized while avoiding an uneven load. It is also possible to suppress the destruction of the electronic device and poor conduction. Since the load can be received at the second seal portion during the division, chipping and cracks are unlikely to occur.

An electronic component package of the present invention includes a device substrate having an electronic device, a cover substrate covering an electronic device formation surface of the device substrate, and surrounding the electronic device and joining the device substrate and the cover substrate. And a second seal portion that covers a part of the outer peripheral surface of the first seal portion, and has an outer peripheral surface that passes through the device substrate, the cover substrate, and the second seal portion. The first seal portion has a multilayer structure including a first layer formed on the device substrate and a second layer formed on the cover substrate, and the widths of the first layer and the second layer are different. The second seal portion covers the outer peripheral surface of the first layer and the second layer, which has a narrower width, and does not cover the other outer peripheral surface .

  According to the present invention, since a device substrate having a plurality of electronic devices and a cover substrate covering the surface on which the electronic device is formed may be joined with the material of the first seal portion that is narrower than before, a large load is required. It is possible to achieve an airtight seal on the entire surface of the substrate without any problems. Since the load can be received at the second seal portion during division, chipping and cracking are unlikely to occur. Therefore, a highly airtight and highly reliable electronic component package can be realized.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a cross-sectional view showing the structure of an electronic component package according to the first embodiment of the present invention. In this electronic component package, a device substrate 1 having an electronic device 2 and a cover substrate 3 that covers an electronic device forming surface of the device substrate 1 are joined by a seal portion 4 at an outer peripheral portion.

  The electronic device 2 is held in a hollow package constituted by the device substrate 1, the cover substrate 3, and the seal portion 4, and is formed on the conductive path 5 penetrating the cover substrate 3 in the electrode portion 2a. It is electrically connected to the electrode part 3 a and can be connected to an external device through an external connection terminal 6 formed at the other end of the conductive path 5.

  The electronic device 2 is an integrated sensor, actuator, mechanism element component, and electronic circuit represented by MEMS (Micro Electro Mechanical Systems). Specific examples thereof include sensors such as a microphone, a mirror, and an angular velocity. It is. As described above, the cover substrate 3 forms a hollow structure for realizing or maintaining the reliability and characteristics of the electronic device 2 and also functions as a connection part of the electronic device 2 to an external device.

  The seal portion 4 includes a first seal portion 9 (9a, 9b) surrounding the electronic device 2 with a space therebetween, and a second seal portion 10 covering the outer peripheral surface of the first seal portion 9, Airtightness is high due to the multi-layer structure. The material of the first seal portion 9 is a metal. The material of the second seal portion 10 is a metal or a resin. These will be described later.

Hereinafter, an electronic component package manufacturing method will be described.
First, an apparatus wafer 101 and a cover wafer 103 shown in FIGS. 2 and 3 are prepared. The device wafer 101 and the cover wafer 103 are formed by successively forming a plurality of the above-described device substrates 1 or cover substrates 3 in order to collectively manufacture a plurality of electronic component packages.

  In the device wafer 101, an electronic device 2 (having electrode portions 2 a and the like) is formed for each region of the device substrate 1, and a frame-shaped first seal portion 9 a surrounding the periphery is formed in a pattern. Adjacent first seal portions 9 a have a groove 11 between them, and the width of the groove 11 is wider than that of the dicing line 7.

  In the cover wafer 103, for each region of the cover substrate 3, an electrode portion 3 a disposed opposite to the electrode portion 2 a of the electronic device 2, a through hole (not shown) serving as the conductive path 5, a first seal A first seal portion 9b arranged to face the portion 9a is formed.

  Specifically, Si, a compound semiconductor, glass, ceramic, metal, or the like used as a semiconductor substrate is used for the base material of the device wafer 101 and the cover wafer 103. When a semiconductor or a conductor is used as a base material, an insulating layer serving as a base for the metal material of the seal portion 4 (first seal portion 9 and second seal portion 10) is provided on at least one of the apparatus wafer 101 and the cover wafer 103. is required.

  The shape of the apparatus wafer 101 and the cover wafer 103 is a quadrangle because only a part is enlarged here, but a circle used for the wafer is generally used. There is no problem even if the whole is a polygon such as a rectangle.

  The size of the device wafer 101 and the cover wafer 103 is generally 2 to 6 inches in consideration of the efficiency of package formation. However, if the size is 1 to 12 inches, there is no problem and the same effect can be obtained. The shapes of the electrode portion 2a and the electrode portion 3a are illustrated as circular in plan view, but may be polygonal or elliptical.

  As the material of the electrode portion 2a and the first seal portion 9a of the electronic device 2 of the device wafer 101, Au that is easily joined by plastic deformation is preferable, but Al, Cu, Ni, Ti, solder, etc. may be used. Even if it has a multi-layer structure, there is no problem and the same effect can be obtained. Considering the production process of the device substrate 1, it is desirable that the electrode part 2a and the first seal part 9a are made of the same material, but it is also possible to use different materials.

  Similarly, as the material of the electrode portion 3a and the first seal portion 9b of the cover wafer 103, Au that is easily joined by plastic deformation is desirable. However, Al, Cu, Ni, Ti, solder, etc. may be used. Even if it is a layer structure, there is no problem and the same effect can be obtained. Considering the production process of the cover substrate 3, it is desirable that the electrode part 3a and the first seal part 9b are made of the same material, but it is also possible to use different materials.

  The use of the first seal portion 9 (9a, 9b) as a metal in this way is particularly effective when the inside of the hollow package needs to be completely airtight due to the characteristics of the electronic device 2. This is because complete hermeticity cannot be obtained with resin. For example, if the first seal portion 9 is made of resin and the second seal portion 10 to be described later is made of metal, moisture penetrates into the resin of the first seal portion 9 due to the influence of the plating solution, and causes a deterioration in reliability. It becomes.

  Next, the prepared apparatus wafer 101 and cover wafer 103 are bonded as shown in FIG. This joining is performed after aligning the patterns of the electrode portions 2a and 3a and the first seal portions 9a and 9b. As a result, the electrode portions 2a of the plurality of electronic devices 2 are connected to the corresponding electrode portions 3a at the same time, and at the same time, the plurality of electronic devices 2 are separated from each other by the first seal portions 9 (9a, 9b). A predetermined gap is formed between the apparatus wafer 101 and the cover wafer 103.

The bonding method at this time is not particularly limited, and there are bonding methods by pressure, bonding by heating, bonding by applying ultrasonic waves, bonding by applying a voltage, bonding by modifying the surface of the bonded object, or a bonding method combining these. It can be used. The bonding environment may be under atmospheric pressure, reduced pressure, or a specific gas atmosphere such as N ₂ or Ar so as to realize an environment desired for the electronic device 2 after packaging.

  Next, as shown in FIG. 4B, a sealing material is introduced between the bonded apparatus wafer 101 and the cover wafer 103 from the outer periphery of the wafer as indicated by an arrow. As a result, the sealing material is filled so as to fill the groove 11 on the outer peripheral side of each of the first seal portions 9 surrounding the electronic device 2 described above, and the second seal portion 10 described above is formed.

  At this time, when a metal is used as the sealing material, the plating solution is brought into contact with the entire surface between the apparatus wafer 101 and the cover wafer 103 by pouring the plating solution from a certain direction (for example, from the A direction). , Grow plating.

  When a resin is used as the sealing material, a low-viscosity resin is used, and the first filling is performed from the A direction, and the second filling is performed from the B direction. If the second resin filling is performed while the first filling resin is still soft, the grooves 11 between the first seal portions 9 are in a lattice shape (see FIGS. 2 and 3). The resin is filled while extruding the first filling resin, and the entire lattice-shaped filling path is filled with the resin. An elastic resin is effective in reducing the generated stress and ensuring reliability.

  After the sealing material is introduced (or prior to the introduction of the sealing material), the conductive path 5 is formed by filling the through-hole formed in the cover wafer 103 as described above by metal film formation or plating growth. As a result, each of the plurality of electronic devices 2 is electrically connected to the corresponding conductive path 5 and simultaneously sealed in a space surrounded by the first seal portion 9 and the second seal portion 10. The After the conductive path 5 is formed, the external connection terminal 6 is formed.

  The second seal portion 10 and the conductive path 5 may be formed first as described above, but when both are formed by plating growth, the bonded device wafer 101 and cover wafer 103 are joined. From the outside, both the second seal portion 10 and the conductive path 5 can be formed simultaneously by plating growth by providing a flow path so that the plating solution circulates in both the lattice-shaped filling path and the through hole. Is possible.

  The material of the conductive path 5 is preferably a metal for the hermeticity of the package, but it is also possible to use a conductive resin. When a conductive resin is used, it is based on a method such as screen printing or filling by coating.

  Thereafter, as shown in FIG. 4C, the bonded apparatus wafer 101 and cover wafer 103 are divided by a dicing blade 8 or the like. The dividing position is the dicing line 7 shown in FIG. 5, that is, the outer peripheral side of the first seal portion 9. As a result, an individual electronic component package in which the outer peripheral side of the electronic device 2 is sealed by the first seal portion 9 and the second seal portion 10 is obtained.

  At the time of division, since the second seal portion 10 exists as shown in the figure, that is, there is no gap as in the conventional case, the stress is relieved and the occurrence of chipping is suppressed. From the viewpoint of high reliability due to stress relaxation and downsizing of the package, the width of the second seal portion 10 (in the electronic component package after separation) is 0.1 to 10 times the width of the first seal portion 9. Degree is desirable.

  The conductive path 5 has been described as being formed in the cover wafer 103, but is not limited thereto, and may be formed in at least one of the cover wafer 103 and the apparatus wafer 101. When the conductive path 5 is formed on the apparatus wafer 101 (apparatus substrate 1), it is not necessary to provide the electrode portion 3a of the cover wafer 103 (cover substrate 3), so that the number of processes can be reduced. In the finished product, the cover substrate 3 has a function of forming a hollow structure for realizing or maintaining the reliability and characteristics of the electronic device 2.

  The first seal portions 4a and 4b before joining desirably have a height / width ratio of 1 or more from the viewpoint of ease of plastic deformation. On the other hand, in order to reduce the pressing area at the time of joining, a narrower width is desirable, and a width of 10 μm or less is optimal. Therefore, for example, when the first seal portions 4a and 4b are formed and patterned so as to have a width of 5 μm and the height is 10 μm by plating, the ratio of height / width is 2, which satisfies both conditions and is satisfactory. Joining is possible.

  There is no restriction on the relationship between the height and width of the first seal portions 4a, 4b. The ratio of the height / width of at least one of the first seal portions 4a and 4b only needs to be 1 or more, even if the other is in a thin film state or has a height of several μm by plating. An effect is obtained.

  For example, as shown in FIG. 1, the height and width of both the first seal portions 4a and 4b may be substantially the same. Or as shown in FIG. 6, the width | variety of 1st seal | sticker part 4a, 4b may be varied, and the 2nd seal | sticker part 10 of the width | variety of the difference may be provided. As shown in FIG. 7, even if one of the first seal portions 4a and 4b (here, the first seal portion 4a) is divided into a plurality of parts, the same effect can be obtained.

  The apparatus wafer 101 shown in FIG. 8 is provided with through-holes 12 penetrating in the wafer thickness direction so as to open in the grooves 11 formed in a lattice shape so as to surround the first seal portions 9a. The position of the through hole 12 is an intersection of the groove 11. The diameter of the through hole 12 is equal to or smaller than the dicing width.

If such an apparatus wafer 101 is used, the second seal portion 10 can be formed by introducing a seal material through the through-hole 12 after joining the cover wafer 103.
When the plating solution is introduced to form the second seal portion 10 with a metal, or when a low-viscosity resin is introduced to form the second seal portion 10 with a resin, referring to FIG. Since the flow path from the wafer center can be formed as compared with the case where the seal material is introduced from the outer periphery as described, the generation of voids in the second seal portion 10 can be suppressed. That is, when the sealing material is introduced from the through-hole 12 at the center of the wafer, the other through-holes 12 become gas vent holes and the sealing material flows to the entire wafer, so that generation of voids in the second seal portion 10 can be suppressed. .

  On the other hand, when a highly viscous resin is used, the layout of the second seal portion 10 can be limited. When the layout of the second seal portion 10 is limited, the sealing effect is reduced, but the reliability of the package is improved.

  For example, the electronic component package shown in FIG. 9 uses the apparatus wafer 101 shown in FIG. 8 and injects high-viscosity resin through the through holes 12 at the intersections of the grooves 11, thereby The 2nd seal | sticker part 10 which covers only this is formed. The presence of the second seal portion 10 is effective for stress concentration due to a difference in thermal expansion between the device substrate 1 and the cover substrate 3.

  The position of the through hole 12 is not particularly limited as long as it opens into the groove portion 11. The electronic component package shown in FIG. 10 has a through hole 12 provided at an intermediate position between the intersections of the groove portions 11 of the apparatus wafer 101 (not shown), and a high viscosity resin is injected through the through holes 12. The second seal portion 10 that covers the four side surfaces (except for the four corners) of the first seal portion 9 is formed. The presence of such a second seal portion 10 can further reduce chipping that is likely to occur at the time of dicing into pieces as compared with the structure of FIG. 9 that covers only the four corners of the first seal portion 9. .

If the through hole 12 is formed with a diameter larger than the dicing width, the filling speed of the sealing material is increased, and the formation efficiency of the second seal portion 10 can be improved.
For example, when the package shape shown in FIG. 1 is used, if the dicing width is 40 μm, the diameter of the through hole 12 must be 55 μm or less so that the trace of the through hole cannot be seen. Since it is not easy, the diameter of the through-hole 12 is intentionally larger than the dicing width, for example, φ60 to 70 μm.

  Increasing the dicing width in order to increase the diameter of the through hole 12 reduces the number of chips per wafer and is inefficient. However, as described above, the diameter of the through hole 12 is larger than the dicing width. By doing so, the sealing material filling process can be made more efficient while maintaining the same number of chips per wafer. As shown in FIG. 11, the resulting package shape has a through-hole groove 13 at the corner of the device substrate 1, but there is no problem.

  Similarly, when the package shape shown in FIG. 9 is used, by making the diameter of the through hole 12 provided at the intersection of the groove 11 larger than the dicing width, the number of chips per wafer can be made equal, The filling process of the sealing material can be made efficient. As shown in FIG. 12, the resulting package shape has a through-hole groove 13 at the corner of the device substrate 1, but there is no problem.

  Similarly, when the package shape shown in FIG. 10 is used, the number of chips obtained per wafer can be made equal by making the diameter of the through hole 12 provided so as to avoid the intersection of the grooves 11 larger than the dicing width. However, the sealing material filling process can be made more efficient. As shown in FIG. 13, the resulting package shape has a through-hole groove 13 on the four side surfaces (excluding the four corners) of the device substrate 1, but there is no problem.

11, 12, and 13, the groove portion 13 of the through hole trace is shown in a state where there is no deposit, but a seal material may exist in the groove portion 13.
11, 12, and 13, four through-hole groove portions 13 are shown, but one or more through-holes 12 may be provided to form the second seal portion 10 at a desired location. The number of groove portions 13 of the through hole trace is not limited to four.

  11, 12, and 13, the groove portion 13 of the through-hole trace is shown in the apparatus substrate 1, but the through-hole 12 is provided in at least one of the apparatus wafer 101 and the cover wafer 103 to obtain a desired location. The second seal portion 10 may be formed on the cover wafer 103. Although the illustration is omitted, when the through hole 12 is provided in the cover wafer 103, the groove portion 13 of the through hole trace remains in the cover substrate 3. If the above-described conductive path 5 is formed in the cover wafer 103, the through hole 12 can be formed in the same process as the through hole therefor, so that the number of processes can be reduced.

  According to the present invention, a highly airtight and highly reliable hollow package structure can be obtained, and an electronic component package such as a microphone, a sensor, and a mirror represented by MEMS can be realized with high reliability.

Sectional drawing of the electronic component package of the 1st Embodiment of this invention 1 is a partially enlarged view of an apparatus wafer used for manufacturing the electronic component package of FIG. FIG. 1 is a partially enlarged view of a cover wafer used for manufacturing the electronic component package of FIG. The perspective view explaining the manufacturing method of the electronic component package of FIG. Sectional drawing which shows 1 process of the manufacturing method of the electronic component package of FIG. Sectional drawing of the electronic component package of the 2nd Embodiment of this invention Sectional drawing of the electronic component package of the 3rd Embodiment of this invention 1 is a partially enlarged view of another apparatus wafer used for manufacturing the electronic component package of FIG. The perspective view of the electronic component package of the 4th Embodiment of this invention The perspective view of the electronic component package of the 5th Embodiment of this invention The perspective view of the electronic component package of the 6th Embodiment of this invention The perspective view of the electronic component package of the 7th Embodiment of this invention The perspective view of the electronic component package of the 8th Embodiment of this invention Sectional view of a conventional electronic component package Sectional drawing which shows 1 process of the manufacturing method of the electronic component package of FIG. Sectional drawing which shows 1 process of the manufacturing method of the other conventional electronic component package

Explanation of symbols

1 Device board 2 Electronic device
2a Electrode 3 Cover substrate
3a Electrode part 4 Seal part 5 Conductive path 7 Dicing line 9, 9a, 9b First seal part
10 Second seal part
11 Groove
12 Through hole
13 Groove
101 Equipment wafer
103 Cover wafer

Claims (10)

A device substrate having an electronic device;
A cover substrate covering an electronic device forming surface of the device substrate;
A first seal portion surrounding the electronic device and joining the device substrate and the cover substrate;
A second seal portion covering a part of the outer peripheral surface of the first seal portion;
Have a peripheral surface which passes through the said device substrate and the cover substrate said second sealing portion,
The first seal portion has a multilayer structure including a first layer formed on the device substrate and a second layer formed on the cover substrate, and the first layer and the second layer have different widths. Is,
The electronic component package according to claim 2, wherein the second seal portion covers an outer peripheral surface of the first layer and the second layer having a smaller width and does not cover the other outer peripheral surface . 2. The electronic component package according to claim 1, wherein the narrower one of the first layer and the second layer is divided into a plurality of parts. The electronic component package according to claim 1, wherein the first seal portion and the second seal portion form one outer peripheral surface. The electronic component package according to claim 1, wherein a material of the first seal portion is a metal. 5. The electronic component package according to claim 1, wherein a material of the second seal portion is a metal. 5. The electronic component package according to claim 1, wherein a material of the second seal portion is a resin. A device substrate having a plurality of electronic devices and a cover substrate covering an electronic device forming surface of the device substrate are arranged so as to surround each of the plurality of electronic devices and form a gap therebetween. Join by the material of the seal part,
Forming a second seal portion covering a part of the outer peripheral surface of each of the first seal portions;
The device substrate and the cover substrate are divided at a predetermined line passing through the second seal portion, the device substrate, and the cover substrate, and are separated into electronic component packages each having the electronic device ,
The first seal portion has a multilayer structure including a first layer formed on the device substrate and a second layer formed on the cover substrate, and the first layer and the second layer have different widths. Is,
The method for manufacturing an electronic component package, wherein the second seal portion covers an outer peripheral surface of the first layer and the second layer that has a narrower width and does not cover the other outer peripheral surface . 8. The method of manufacturing an electronic component package according to claim 7, wherein the narrower one of the first layer and the second layer is divided into a plurality of parts. 9. The method of manufacturing an electronic component package according to claim 7, wherein the first seal portion and the second seal portion form one outer peripheral surface. Said second sealing portion, according to any one of claims 7 to 9, characterized in that formed by filling the sealing material from the substrate end portion between the cover substrate and the device substrate Manufacturing method of electronic component package.

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