JP4821424B2 - Ceramic multilayer substrate and manufacturing method thereof - Google Patents

Ceramic multilayer substrate and manufacturing method thereof Download PDF

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JP4821424B2
JP4821424B2 JP2006131637A JP2006131637A JP4821424B2 JP 4821424 B2 JP4821424 B2 JP 4821424B2 JP 2006131637 A JP2006131637 A JP 2006131637A JP 2006131637 A JP2006131637 A JP 2006131637A JP 4821424 B2 JP4821424 B2 JP 4821424B2
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conductive resin
multilayer substrate
terminal electrode
ceramic multilayer
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伸明 小川
和弘 伊勢坊
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Murata Manufacturing Co Ltd
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Description

本発明は、セラミック多層基板及びその製造方法に関し、更に詳しくは、耐衝撃性を高め、信頼性を向上させることができるセラミック多層基板及びその製造方法に関する。   The present invention relates to a ceramic multilayer substrate and a manufacturing method thereof, and more particularly to a ceramic multilayer substrate capable of improving impact resistance and improving reliability and a manufacturing method thereof.

セラミック多層基板は、複数のセラミック層を積層してなるセラミック積層体と、セラミック積層体の内部に形成された内部導体パターンと、セラミック積層体の表面に形成された外部導体パターンと、を備えて構成されている。内部導体パターンは、セラミック層間に形成された複数の面内導体及び上下の面内導体等を接続するビアホール導体によって構成されている。また、外部導体パターンは、セラミック積層体の上下両面等の表面に形成された端子電極によって構成されている。   The ceramic multilayer substrate includes a ceramic laminate formed by laminating a plurality of ceramic layers, an internal conductor pattern formed inside the ceramic laminate, and an external conductor pattern formed on the surface of the ceramic laminate. It is configured. The internal conductor pattern is constituted by a plurality of in-plane conductors formed between ceramic layers and via-hole conductors connecting upper and lower in-plane conductors. The external conductor pattern is constituted by terminal electrodes formed on the upper and lower surfaces of the ceramic laminate.

このようなセラミック多層基板及びその製造方法としては、例えば特許文献１に記載の多層セラミック基板及びその作製方法が知られている。この多層セラミック基板の作製方法では、低温焼成用のセラミックグリーンシートに、電気・電子部品との接続のための第１の接続端子部、外部回路との接続のための第２の接続端子部、及び第１の接続端子部と第２の接続端子部を電気的に接続する導体回路部をそれぞれ金属ペーストを用いて形成した後、複数のセラミックグリーンシートを積層し、セラミックグリーンシート及び金属ペーストを同時に低温焼成して、基板部材を作製する。   As such a ceramic multilayer substrate and a manufacturing method thereof, for example, a multilayer ceramic substrate described in Patent Document 1 and a manufacturing method thereof are known. In this method for producing a multilayer ceramic substrate, a ceramic green sheet for low-temperature firing is provided with a first connection terminal portion for connection with an electric / electronic component, a second connection terminal portion for connection with an external circuit, And forming a conductor circuit portion for electrically connecting the first connection terminal portion and the second connection terminal portion using a metal paste, respectively, laminating a plurality of ceramic green sheets, At the same time, the substrate member is fabricated by low-temperature firing.

上記基板部材の導体回路部は、パンチング等の手法によりセラミックグリーンシートに形成されたビアホールやスルーホールに金属ペーストを充填し、乾燥させることによって形成する。また、第１、第２の接続端子部は、セラミックグリーンシートに金属ペーストをスクリーン印刷によって形成する。そして、これらのセラミックグリーンシートを積層し、圧着した後、セラミックグリーンシートと金属ペーストとを所定の焼成温度で同時焼成して基板部材を作製している。つまり、特許文献１に記載の多層セラミック基板の作製方法では、複数積層されたセラミックグリーンシートと金属ペーストとを同時に焼成する従来公知の技術が採用されている。   The conductor circuit portion of the substrate member is formed by filling a via paste or a through hole formed in the ceramic green sheet with a metal paste by a technique such as punching and drying it. The first and second connection terminal portions are formed by screen printing a metal paste on a ceramic green sheet. These ceramic green sheets are laminated and pressure-bonded, and then the ceramic green sheets and the metal paste are simultaneously fired at a predetermined firing temperature to produce a substrate member. That is, in the method for manufacturing a multilayer ceramic substrate described in Patent Document 1, a conventionally known technique of simultaneously firing a plurality of laminated ceramic green sheets and metal paste is employed.

特開平０６−２７５９５６Japanese Patent Application Laid-Open No. 06-275556

しかしながら、特許文献１に記載の多層セラミック基板等の従来のセラミック多層基板の場合には、セラミックグリーンシートと金属ペーストは、それぞれを構成する材料が異なるため、焼成時にそれぞれ異なった収縮挙動を示すことになる。この収縮挙動差によってセラミック層と焼結金属との間に隙間ができたり、セラミック多層基板に反りやうねりを生じる。そこで、金属ペーストの収縮挙動をセラミックグリーンシートの収縮挙動に合わせて両者間の収縮挙動差を極力抑制するために、金属ペーストの金属材料粉末の種類や粒径、粒度分布などを調整したり、焼成時の温度管理等を厳密にコントロールしなくてはならない。しかし、このような対策を講じたとしてもセラミックグリーンシートと金属ペーストとの収縮挙動差を完全に解消することができず、セラミック多層基板を構成するセラミック層と内部導体パターンとの間の収縮挙動差に基づく隙間や外部導体パターン周辺の反りやうねりを生じることが多々ある。その結果、セラミック多層基板の平坦性や耐めっき性が損なわれることがある。   However, in the case of a conventional ceramic multilayer substrate such as the multilayer ceramic substrate described in Patent Document 1, the ceramic green sheet and the metal paste have different contracting behaviors during firing because they are made of different materials. become. Due to this difference in shrinkage behavior, a gap is formed between the ceramic layer and the sintered metal, and warping and undulation are generated in the ceramic multilayer substrate. Therefore, in order to match the shrinkage behavior of the metal paste with the shrinkage behavior of the ceramic green sheet and suppress the difference in shrinkage behavior between the two as much as possible, adjust the type, particle size, particle size distribution, etc. of the metal material powder of the metal paste, The temperature control during firing must be strictly controlled. However, even if such measures are taken, the difference in the shrinkage behavior between the ceramic green sheet and the metal paste cannot be completely eliminated, and the shrinkage behavior between the ceramic layer and the internal conductor pattern constituting the ceramic multilayer substrate. There are many cases where gaps based on the difference and warpage and undulation around the outer conductor pattern occur. As a result, the flatness and plating resistance of the ceramic multilayer substrate may be impaired.

一方、セラミック多層基板は、高密度に導体パターンを形成することができ、しかもコンデンサやインダクタ等の受動素子を基板内に内蔵させることができるため、小型で高密度配線を要求される移動体通信端末等のように携帯可能な電子機器に多用されている。ところが、これらの電子機器は、携帯されるために落下等の衝撃を免れず、落下等の衝撃に対する耐衝撃性の向上が強く要求される。   On the other hand, ceramic multilayer substrates can form conductive patterns at high density, and passive elements such as capacitors and inductors can be built into the substrate. Widely used in portable electronic devices such as terminals. However, since these electronic devices are carried, they are not subject to impacts such as dropping, and it is strongly required to improve impact resistance against impacts such as dropping.

しかしながら、従来のセラミック多層基板の場合には、セラミック積層体の内部導体パターン及び端子電極のような外部導体パターンが焼結金属によって形成されているため、落下時等による衝撃がマザー基板に作用すると、その衝撃が端子電極等の外部導体パターンからセラミック積層体に直接伝播するため、セラミック積層体内の上述の収縮挙動差で生じた隙間等においてクラックを発生しやすく、信頼性を低下させる虞があった。   However, in the case of the conventional ceramic multilayer substrate, since the inner conductor pattern of the ceramic laminate and the outer conductor pattern such as the terminal electrode are formed of sintered metal, an impact caused by dropping or the like acts on the mother substrate. Because the impact propagates directly from the external conductor pattern such as the terminal electrode to the ceramic laminate, cracks are likely to occur in the gaps caused by the above-mentioned difference in shrinkage behavior in the ceramic laminate, which may reduce reliability. It was.

本発明は、上記課題を解決するためになされたもので、耐衝撃性、電気的接続性及び機械的接続性に優れ、且つ、平坦性及び耐めっき性に優れたセラミック多層基板及びその製造方法を提供することを目的としている。 The present invention has been made to solve the above-described problems, and is a ceramic multilayer substrate excellent in impact resistance , electrical connectivity and mechanical connectivity, and excellent in flatness and plating resistance, and a method for producing the same. The purpose is to provide.

本発明の請求項１に記載のセラミック多層基板は、複数のセラミック層を積層してなるセラミック積層体の内部に内部導体パターンを有し、上記セラミック積層体の主面に露出する端子電極を有するセラミック多層基板であって、上記端子電極は、上記内部導体パターンを構成するビアホール導体に接続されていると共に上記端子電極の面積が上記ビアホール導体の断面積より大きく形成され、また、上記端子電極の表面及び上記端子電極と上記セラミック積層体との境界部を覆い且つ上記主面に対して凸状となる導電性樹脂部が設けられており、上記端子電極の表面は、中央部が上記主面から上記導電性樹脂部内に突出して上記導電性樹脂部に接合されていることを特徴とするものである。 A ceramic multilayer substrate according to claim 1 of the present invention has an internal conductor pattern inside a ceramic laminate formed by laminating a plurality of ceramic layers, and has a terminal electrode exposed on the main surface of the ceramic laminate. A ceramic multilayer substrate, wherein the terminal electrode is connected to a via-hole conductor constituting the internal conductor pattern and has an area of the terminal electrode larger than a cross-sectional area of the via-hole conductor , conductive resin portion convex and that Do is provided to the surface and the boundary portion one且brewing covering over SL main surface of the terminal electrode and the ceramic laminate, the surface of the terminal electrode, the central The portion protrudes from the main surface into the conductive resin portion and is joined to the conductive resin portion .

また、本発明の請求項２に記載のセラミック多層基板は、請求項１に記載の発明において、上記内部導体パターン及び上記端子電極は、上記セラミック積層体との同時焼成によって得られる焼結金属であることを特徴とするものである。   The ceramic multilayer substrate according to claim 2 of the present invention is the sintered metal obtained in the invention according to claim 1, wherein the internal conductor pattern and the terminal electrode are obtained by simultaneous firing with the ceramic laminate. It is characterized by being.

また、本発明の請求項３に記載のセラミック多層基板は、請求項１または請求項２に記載の発明において、上記導電性樹脂部の表面にはめっき膜が形成されていることを特徴とするものである。 According to a third aspect of the present invention, there is provided the ceramic multilayer substrate according to the first or second aspect , wherein a plating film is formed on the surface of the conductive resin portion. Is.

また、本発明の請求項４に記載のセラミック多層基板は、請求項１〜請求項３のいずれか１項に記載の発明において、上記導電性樹脂部の高さは、上記主面に対して５〜１０００μｍであることを特徴とするものである。 Moreover, the ceramic multilayer substrate according to claim 4 of the present invention is the invention according to any one of claims 1 to 3 , wherein the height of the conductive resin portion is relative to the main surface. It is 5 to 1000 μm.

また、本発明の請求項５に記載のセラミック多層基板は、請求項１〜請求項４のいずれか１項に記載の発明において、上記セラミック積層体の上記主面には、その周縁部に複数の端子電極が配列されており、これらの端子電極のうち、少なくとも四隅の端子電極はそれぞれの表面の中央部が上記主面から突出して上記導電性樹脂部によって被覆されていることを特徴とするものである。 Moreover, the ceramic multilayer substrate according to claim 5 of the present invention is the invention according to any one of claims 1 to 4 , wherein the main surface of the ceramic laminate has a plurality of peripheral portions. The terminal electrodes of at least the four corners of these terminal electrodes are characterized in that the center portions of the respective surfaces protrude from the main surface and are covered with the conductive resin portion. Is.

また、本発明の請求項６に記載のセラミック多層基板の製造方法は、複数のセラミック層を積層してなるセラミック積層体の内部に内部導体パターンを有し、上記セラミック積層体の主面に露出する端子電極を有するセラミック多層基板を作製する際に、上記内部導体パターンを構成するビアホール導体にこのビアホール導体の断面積より大きな面積を有する上記端子電極を接続すると共に上記端子電極の表面の中央部が上記主面から突出する上記セラミック積層体を作製する第１の工程と、上記端子電極の表面及び上記端子電極と上記セラミック積層体との境界部を覆い且つ上記主面に対して凸状となる導電性樹脂部を上記主面に形成する第２の工程と、を備えたものである。 According to a sixth aspect of the present invention, there is provided a method for producing a ceramic multilayer substrate, comprising: an inner conductor pattern inside a ceramic laminate formed by laminating a plurality of ceramic layers; and exposed to the main surface of the ceramic laminate. in making ceramic multilayer substrate having a terminal electrode to the central portion of the surface of the terminal electrodes while connecting the terminal electrodes having a larger area than the cross-sectional area of the via-hole conductors in the via hole conductors constituting the internal conductor pattern There first step and, convex with respect to the surface and and the main surface has covering the boundary between the terminal electrode and the ceramic laminate of the terminal electrodes for making the ceramic laminated body projecting from the main surface And a second step of forming a conductive resin portion on the main surface .

また、本発明の請求項７に記載のセラミック多層基板の製造方法は、請求項６に記載の発明において、上記内部導体パターン及び上記端子電極を、上記セラミック積層体と同時焼成することを特徴とすることを特徴とするものである。 The method for producing a ceramic multilayer substrate according to claim 7 of the present invention is characterized in that, in the invention according to claim 6 , the internal conductor pattern and the terminal electrode are simultaneously fired with the ceramic laminate. It is characterized by doing.

また、本発明の請求項８に記載のセラミック多層基板の製造方法は、請求項６または請求項７に記載の発明において、上記導電性樹脂部を形成する際に、上記主面に導電性樹脂層を形成した後、平滑面を有する平滑部材を、上記平滑面が上記導電性樹脂層の表面に接触するように上記導電性樹脂層上に載置することを特徴とするものである。 The method for producing a ceramic multilayer substrate according to claim 8 of the present invention is the method according to claim 6 or 7 , wherein the conductive resin portion is formed on the main surface when the conductive resin portion is formed. After the layer is formed, a smooth member having a smooth surface is placed on the conductive resin layer so that the smooth surface is in contact with the surface of the conductive resin layer.

また、本発明の請求項９に記載のセラミック多層基板の製造方法は、請求項８に記載の発明において、上記平滑部材の平滑面を複数の上記導電性樹脂層の表面に同時に接触させて、上記各導電性樹脂層それぞれの表面を同一高さに形成することを特徴とするものである。 The method for producing a ceramic multilayer substrate according to claim 9 of the present invention is the method according to claim 8 , wherein the smooth surface of the smooth member is simultaneously brought into contact with the surfaces of the plurality of conductive resin layers, The surfaces of the respective conductive resin layers are formed at the same height.

また、本発明の請求項１０に記載のセラミック多層基板の製造方法は、請求項８または請求項９に記載の発明において、上記平滑部材として、上記導電性樹脂層に対応する凹部を有し且つこの凹部内に上記平滑面が形成された板状部材を用いることを特徴とするものである。 A method for producing a ceramic multilayer substrate according to claim 10 of the present invention is the invention according to claim 8 or 9 , wherein the smooth member has a recess corresponding to the conductive resin layer, and A plate-like member in which the smooth surface is formed in the recess is used.

また、本発明の請求項１１に記載のセラミック多層基板の製造方法は、請求項６〜請求項１０のいずれか１項に記載の発明において、上記導電性樹脂部の表面にめっき膜を形成することを特徴とするものである。 Moreover, the manufacturing method of the ceramic multilayer substrate of Claim 11 of this invention forms a plating film in the surface of the said conductive resin part in the invention of any one of Claims 6-10. It is characterized by this.

また、本発明の請求項１２に記載のセラミック多層基板の製造方法は、請求項６〜請求項１１のいずれか１項に記載の発明において、上記内部導体パターンを有するセラミックグリーンシート及び上記端子電極を有するセラミックグリーンシートを積層して未焼成のセラミック積層体を作製し、これをその両主面が平坦化するように加圧することを特徴とするものである。 According to a twelfth aspect of the present invention, there is provided a method for producing a ceramic multilayer substrate according to any one of the sixth to eleventh aspects, wherein the ceramic green sheet having the internal conductor pattern and the terminal electrode are provided. An unfired ceramic laminate is produced by laminating ceramic green sheets having the above-mentioned properties, and this is pressurized so that both main surfaces thereof are flattened.

本発明によれば、耐衝撃性、電気的接続性及び機械的接続性に優れ、且つ、平坦性及び耐めっき性に優れたセラミック多層基板及びその製造方法を提供することができる。
According to the onset bright, impact resistance, excellent electrical connectivity and mechanical connectivity, and can provide a superior ceramic multilayer substrate and a method of manufacturing the flatness and plating resistance.

以下、図１〜図１２に示す実施形態に基づいて本発明を説明する。   Hereinafter, the present invention will be described based on the embodiment shown in FIGS.

第１の実施形態
本実施形態のセラミック多層基板１０は、例えば図１の（ａ）に示すように、複数のセラミック層１１Ａが積層されたセラミック積層体１１と、セラミック積層体１１の内部に所定のパターンで形成された内部導体パターン１２と、セラミック積層体１１の表面に形成された外部導体パターン１３と、を備えている。そして、セラミック多層基板１０は、セラミック積層体１１の第１の主面（下面）のキャビティＣ内に半導体素子２０が実装され、セラミック積層体１１の第２の主面（上面）には第１、第２の表面実装部品３０Ａ、３０Ｂが実装されて、電子部品として構成されている。そして、セラミック多層基板１０の上面側には金属製ケース４０が装着され、金属製ケース４０によって半導体素子２０及び第１、第２の表面実装部品３０Ａ、３０Ｂを外部の電磁波等から保護している。また、金属製ケース４０をセラミック多層基板１０に装着することで電子部品としての面実装を容易にしている。 First Embodiment A ceramic multilayer substrate 10 of the present embodiment includes, for example, a ceramic laminate 11 in which a plurality of ceramic layers 11A are laminated, and a predetermined inside of the ceramic laminate 11 as shown in FIG. And an external conductor pattern 13 formed on the surface of the ceramic laminate 11. In the ceramic multilayer substrate 10, the semiconductor element 20 is mounted in the cavity C of the first main surface (lower surface) of the ceramic multilayer body 11, and the first main surface (upper surface) of the ceramic multilayer body 11 is the first. The second surface mount components 30A and 30B are mounted and configured as electronic components. A metal case 40 is mounted on the upper surface side of the ceramic multilayer substrate 10, and the metal case 40 protects the semiconductor element 20 and the first and second surface mount components 30A and 30B from external electromagnetic waves and the like. . Further, mounting the metal case 40 on the ceramic multilayer substrate 10 facilitates surface mounting as an electronic component.

内部導体パターン１２は、図１の（ａ）に示すように、上下のセラミック層１１Ａ、１１Ａの界面に所定のパターンで形成された複数の面内導体１２Ａと、所望のセラミック層１１Ａを貫通するように所定のパターンで形成れたビアホール導体１２Ｂとから構成されている。外部導体パターン１３は、セラミック積層体１１の下面に所定のパターンで形成された第１の端子電極１３Ａと、キャビティＣ内の大きな開口部と小さな開口部を繋ぐ水平面内に所定のパターンで形成された第２の接続端子１３Ｂと、セラミック積層体１１の上面に所定のパターンで形成された第３の端子電極１３Ｃとから構成されている。   As shown in FIG. 1A, the internal conductor pattern 12 penetrates a plurality of in-plane conductors 12A formed in a predetermined pattern at the interface between the upper and lower ceramic layers 11A and 11A and the desired ceramic layer 11A. The via hole conductor 12B is formed in a predetermined pattern as described above. The external conductor pattern 13 is formed in a predetermined pattern in a horizontal plane connecting the first terminal electrode 13A formed in a predetermined pattern on the lower surface of the ceramic laminate 11 and the large opening in the cavity C and the small opening. The second connection terminal 13 </ b> B and the third terminal electrode 13 </ b> C formed in a predetermined pattern on the upper surface of the ceramic laminate 11.

また、第１の端子電極１３Ａは、例えば半田ボールや導電性樹脂等を用いてセラミック多層基板１０をマザー基板５０の表面電極５０Ａに電気的に接続するために用いられる。第２の接続端子１３Ｂは、例えば金等からなるボンディングワイヤー２０Ａを用いて半導体素子２０の端子電極（図示せず）に電気的に接続するために用いられる。第３の端子電極１３Ｃは、例えば半田ボール等を用いて第１、第２の表面実装部品３０Ａ、３０Ｂそれぞれの端子電極に電気的に接続するために用いられる。尚、第１の表面実装部品３０Ａとしては、例えばシリコン半導体素子、ガリウム砒素半導体素子等の能動素子があり、第２の表面実装部品３０Ｂとしては、例えばコンデンサ、インダクタ、抵抗等の受動素子等がある。   The first terminal electrode 13A is used for electrically connecting the ceramic multilayer substrate 10 to the surface electrode 50A of the mother substrate 50 using, for example, solder balls or conductive resin. The second connection terminal 13B is used for electrical connection to a terminal electrode (not shown) of the semiconductor element 20 using a bonding wire 20A made of, for example, gold. The third terminal electrode 13C is used to electrically connect to the terminal electrodes of the first and second surface mount components 30A and 30B using, for example, solder balls. The first surface mount component 30A includes active elements such as silicon semiconductor elements and gallium arsenide semiconductor elements, and the second surface mount component 30B includes passive elements such as capacitors, inductors, resistors, and the like. is there.

セラミック積層体１１を形成するセラミック材料は特に制限されないが、セラミック材料としては、例えば低温焼結セラミック（ＬＴＣＣ：Low Temperature Co-fired Ceramic）材料を使用することができる。低温焼結セラミック材料とは、１０５０℃以下の温度で焼結可能であって、比抵抗の小さなＡｕ、ＡｇやＣｕ等と同時焼成が可能なセラミック材料である。低温焼結セラミック材料としては、具体的には、アルミナやジルコニア、マグネシア、フォルステライト等のセラミック粉末にホウ珪酸系ガラスを混合してなるガラス複合系ＬＴＣＣ材料、ＺｎＯ−ＭｇＯ−Ａｌ２Ｏ３−ＳｉＯ２系の結晶化ガラスを用いた結晶化ガラス系ＬＴＣＣ材料、ＢａＯ−Ａｌ２Ｏ３−ＳｉＯ２系セラミック粉末やＡｌ２Ｏ３−ＣａＯ−ＳｉＯ２−ＭｇＯ−Ｂ２Ｏ３系セラミック粉末等を用いた非ガラス系ＬＴＣＣ材料等が挙げられる。低温焼結セラミック材料を用いることにより、セラミック焼結体を素体とするコンデンサやインダクタ等の受動素子をセラミック積層体１１内に組み込むことができる。 Although the ceramic material which forms the ceramic laminated body 11 is not specifically limited, For example, a low temperature co-fired ceramic (LTCC) material can be used as the ceramic material. The low-temperature sintered ceramic material is a ceramic material that can be sintered at a temperature of 1050 ° C. or less and can be simultaneously fired with Au, Ag, Cu, or the like having a small specific resistance. Specifically, as the low-temperature sintered ceramic material, a glass composite LTCC material obtained by mixing borosilicate glass with ceramic powder such as alumina, zirconia, magnesia, and forsterite, ZnO—MgO—Al 2 O 3 — Crystallized glass-based LTCC material using crystallized glass of SiO 2 , BaO—Al 2 O 3 —SiO 2 ceramic powder, Al 2 O 3 —CaO—SiO 2 —MgO—B 2 O 3 ceramic powder, etc. Non-glass type LTCC materials using By using a low-temperature sintered ceramic material, a passive element such as a capacitor or an inductor having a ceramic sintered body as an element can be incorporated in the ceramic laminate 11.

また、セラミック積層体１１を形成するセラミック材料としては、低温焼結セラミックに限らず、高温焼結セラミック（ＨＴＣＣ：High Temperature Co-fired Ceramic）材料を使用することもできる。高温焼結セラミック材料としては、例えば、アルミナ、窒化アルミニウム、ムライト、その他の材料にガラスなどの焼結助材を加え、１１００℃以上で焼結可能なセラミック材料がある。この場合、内部導体パターン１２及び外部導体パターン１３としては、Ｍｏ、Ｐｔ、Ｐｄ、Ｗ、Ｎｉ及びこれらの合金から選択される金属を使用する。   Moreover, as a ceramic material which forms the ceramic laminated body 11, not only a low temperature sintered ceramic but a high temperature sintered ceramic (HTCC: High Temperature Co-fired Ceramic) material can also be used. Examples of the high-temperature sintered ceramic material include ceramic materials that can be sintered at 1100 ° C. or higher by adding a sintering aid such as glass to alumina, aluminum nitride, mullite, and other materials. In this case, as the inner conductor pattern 12 and the outer conductor pattern 13, a metal selected from Mo, Pt, Pd, W, Ni and alloys thereof is used.

セラミック積層体１１に形成された内部導体パターン１２及び外部導体パターン１３は、いずれも導電性金属材料によって形成することができる。導電性金属材料としては、Ａｇ、Ａｇ−Ｐｔ合金、Ａｇ−Ｐｄ合金、Ｃｕ、Ｎｉ、Ｐｔ、Ｐｄ、Ｗ、Ｍｏ及びＡｕの少なくとも一種を主成分とする金属を用いることができる。これらの導電性金属材料のうち、Ａｇ、Ａｇ−Ｐｔ合金、Ａｇ−Ｐｄ合金及びＣｕは、比抵抗が小さいため、特に高周波向けの導体パターンにおいてより好ましく用いることができる。また、セラミック積層体１１の材料として低温焼結セラミック材料を用いる場合には、ＡｇまたはＣｕ等の低抵抗で１０５０℃以下の融点をもつ金属を用いることができ、セラミック積層体１１と内部導体パターン１２及び外部導体パターン１３は１０５０℃以下の低温で同時焼成することができる。従って、内部導体パターン１２及び外部導体パターン１３は、いずれも焼結金属として形成されている。   Both the inner conductor pattern 12 and the outer conductor pattern 13 formed on the ceramic laminate 11 can be formed of a conductive metal material. As the conductive metal material, a metal mainly containing at least one of Ag, Ag—Pt alloy, Ag—Pd alloy, Cu, Ni, Pt, Pd, W, Mo, and Au can be used. Among these conductive metal materials, Ag, Ag—Pt alloy, Ag—Pd alloy, and Cu can be used more preferably in a conductor pattern especially for high frequency because of their low specific resistance. Further, when a low-temperature sintered ceramic material is used as the material of the ceramic laminate 11, a metal having a low resistance such as Ag or Cu and a melting point of 1050 ° C. or less can be used. 12 and the external conductor pattern 13 can be simultaneously fired at a low temperature of 1050 ° C. or lower. Therefore, both the inner conductor pattern 12 and the outer conductor pattern 13 are formed as sintered metal.

而して、本実施形態では、第１の端子電極１３Ａは、例えば図１の（ａ）〜（ｃ）に示すように、下端の表面がセラミック積層体１１の下面と段差なく面一に形成されている。この第１の端子電極１３Ａの表面には同図に示すように導電性樹脂部１４が被覆され、この導電性樹脂部１４の平面積は同図の（ｂ）、（ｃ）で拡大して示すように、第１の端子電極１３Ａの平面積より広く、しかもセラミック積層体１１の下面から突出する凸状の導電性樹脂部として形成されている。従って、導電性樹脂部１４は、同図の（ｂ）、（ｃ）に示すように第１の端子電極１３Ａの表面及び第１の端子電極１３Ａとセラミック積層体１１の境界部（図１の（ｃ）では破線で示してある）を覆い、第１の端子電極１３Ａ及びセラミック積層体１１との境界部を含む大きさに形成されている。導電性樹脂部１４のセラミック積層体１１の下面からの突出量、つまり導電性樹脂部１４の厚みが５〜１０００μｍになるように形成されていることが好ましく、５〜１００μｍがより好ましく、２０〜１００μｍが更に好ましい。導電性樹脂部１４の厚みが５μｍ未満では耐衝撃性が十分でなく、その厚みが１０００μｍを超えると導体としての抵抗値が大きくなる。   Thus, in the present embodiment, the first terminal electrode 13A is formed such that, for example, as shown in FIGS. 1A to 1C, the lower end surface is flush with the lower surface of the ceramic laminate 11 without any step. Has been. The surface of the first terminal electrode 13A is covered with a conductive resin portion 14 as shown in the figure, and the plane area of the conductive resin portion 14 is enlarged by (b) and (c) in the figure. As shown, it is formed as a convex conductive resin portion that is larger than the plane area of the first terminal electrode 13 </ b> A and protrudes from the lower surface of the ceramic laminate 11. Therefore, the conductive resin portion 14 is formed on the surface of the first terminal electrode 13A and the boundary portion between the first terminal electrode 13A and the ceramic laminate 11 (shown in FIG. 1), as shown in FIGS. (C), and is formed in a size including the boundary between the first terminal electrode 13A and the ceramic laminate 11. The protruding amount of the conductive resin portion 14 from the lower surface of the ceramic laminate 11, that is, the thickness of the conductive resin portion 14 is preferably 5 to 1000 μm, more preferably 5 to 100 μm, and more preferably 20 to 20 μm. More preferably, it is 100 μm. If the thickness of the conductive resin portion 14 is less than 5 μm, the impact resistance is not sufficient, and if the thickness exceeds 1000 μm, the resistance value as a conductor increases.

導電性樹脂部１４は、例えば、エポキシ樹脂、シリコーン樹脂、ウレタン樹脂等の熱硬化性樹脂と、Ａｇ、Ｃｕ、Ｎｉ、Ａｕ、Ａｌ、Ａｇ−Ｐｄ合金等の導電性に優れた金属材料粉末とを主体成分とするものが好ましい。金属材料粉末は、球形状、フレーク状、不定形状等のものが挙げられ、例えば低抵抗で適度な流動性を確保する上で球形状の粉末とフレーク状の粉末との混合物が好ましい。金属材料粉末の平均粒径は、１〜３０μｍ程度が好ましい。金属材料粉末の平均粒径が１μｍ未満では金属材料粉末の形成が難しく高コスト化し、また、その平均粒径が３０μｍを超えると樹脂による衝撃吸収効果が阻害され、耐衝撃性が十分発揮されないことがある。金属材料粉末の含有量は、６０〜９５重量％が好ましい。金属材料粉末の含有量が６０重量％未満では抵抗値が大きくなり、その含有量が９０重量％を超えると導電性樹脂部としての弾性が低下する傾向にある。   The conductive resin portion 14 includes, for example, a thermosetting resin such as an epoxy resin, a silicone resin, and a urethane resin, and a metal material powder excellent in conductivity such as an Ag, Cu, Ni, Au, Al, and Ag—Pd alloy. Those having as the main component are preferred. Examples of the metal material powder include a spherical shape, a flake shape, and an indefinite shape. For example, a mixture of a spherical powder and a flaky powder is preferable in order to ensure a low resistance and appropriate fluidity. The average particle size of the metal material powder is preferably about 1 to 30 μm. If the average particle size of the metal material powder is less than 1 μm, it is difficult to form the metal material powder and the cost is increased. If the average particle size exceeds 30 μm, the impact absorbing effect by the resin is hindered and the impact resistance is not sufficiently exhibited. There is. The content of the metal material powder is preferably 60 to 95% by weight. When the content of the metal material powder is less than 60% by weight, the resistance value increases, and when the content exceeds 90% by weight, the elasticity as the conductive resin portion tends to decrease.

更に、導電性樹脂部１４の表面にはめっき膜１５が形成されている。めっき膜１５は、例えば、Ｎｉ／ＳｎまたはＮｉ／Ａｕ等を湿式めっきによって形成することが好ましい。本実施形態では、第１の端子電極１３Ａを被覆する導電性樹脂部１４の表面にめっき膜１５を形成するため、セラミック積層体１１と第１の端子電極１３Ａとの収縮挙動差によってこれら両者間に隙間が形成されることがあってもめっき液が隙間に侵入し、あるいは焼結金属からなる第１の端子電極１３Ａの表面にめっき液が残留するなどの問題はなく、その結果、半田付け後のリフロー時の熱で残留めっき液が爆ぜて溶融半田を飛散させるなどの問題を生じることがない。また、めっき膜１５によって第１の端子電極１３Ａにおける半田に対する濡れ性が高まり、マザー基板５０の表面電極５０Ａとの電気的な接続性を高めることができる。   Further, a plating film 15 is formed on the surface of the conductive resin portion 14. The plating film 15 is preferably formed by wet plating of, for example, Ni / Sn or Ni / Au. In the present embodiment, since the plating film 15 is formed on the surface of the conductive resin portion 14 covering the first terminal electrode 13A, the difference between the shrinkage behavior between the ceramic laminate 11 and the first terminal electrode 13A is caused. Even if a gap is formed, there is no problem that the plating solution enters the gap or the plating solution remains on the surface of the first terminal electrode 13A made of sintered metal. There is no problem that the residual plating solution explodes due to heat at the time of subsequent reflow and the molten solder is scattered. Further, the plating film 15 increases the wettability of the first terminal electrode 13A with respect to the solder, and the electrical connectivity with the surface electrode 50A of the mother substrate 50 can be improved.

次いで、本発明のセラミック多層基板の製造方法の一実施形態について図２、図３をも参照しながら説明する。   Next, an embodiment of a method for producing a ceramic multilayer substrate according to the present invention will be described with reference to FIGS.

まず、低温焼結セラミック粉末として例えばアルミナ粉末及びホウ珪酸ガラスからなる混合粉末を調製する。この混合粉末を有機ビヒクル中に分散させてスラリーを調製し、これをキャスティング法によってＰＥＴ等の樹脂フィルム上に塗布し、厚み１０〜２００μｍ程度のセラミックグリーンシートを所定枚数作製する。次いで、例えばレーザ光や金型を用いて所定のセラミックグリーンシートに直径０．１ｍｍ程度のビアホールを所定のパターンで形成する。   First, a mixed powder made of, for example, alumina powder and borosilicate glass is prepared as a low-temperature sintered ceramic powder. This mixed powder is dispersed in an organic vehicle to prepare a slurry, which is applied onto a resin film such as PET by a casting method, and a predetermined number of ceramic green sheets having a thickness of about 10 to 200 μm are produced. Next, via holes having a diameter of about 0.1 mm are formed in a predetermined pattern on a predetermined ceramic green sheet using, for example, laser light or a mold.

その後、図２の（ａ）に示すよう、セラミックグリーンシート１１１Ａのビアホール内に導電性ペーストを充填してビアホール導体部１１２Ｂを形成する。導電性ペーストとしては、例えばＡｇまたはＣｕを主成分とする金属材料粉末、樹脂、有機溶剤を混練して調整されたものを用いる。その後、例えばスクリーン印刷法によって同一の導電性ペーストを複数のセラミックグリーンシート１１１Ａ上にそれぞれ所定のパターンで印刷、乾燥して面内導体部１１２Ａ及び第１、第２の端子電極部１１３Ａ、１１３Ｂを同図の（ａ）に示すように形成する。また、ＰＥＴ等の樹脂フィルム１００上に導電性ペーストを所定のパターンで塗布、乾燥し、第３の端子電極部１１３Ｃを形成する。次いで、例えばレーザ光や金型を用いて所定のセラミックグリーンシート１１１Ａに所定の大きさのキャビティ用の開口部を開ける。図１の（ａ）に示すキャビティＣは段部があるため、図２の（ａ）に示すようにキャビティ用の開口部として大小二種類の孔Ｃ’、Ｃ”を設ける。   Thereafter, as shown in FIG. 2A, the via hole conductor 112B is formed by filling the via hole of the ceramic green sheet 111A with a conductive paste. As the conductive paste, for example, a paste prepared by kneading a metal material powder mainly composed of Ag or Cu, a resin, and an organic solvent is used. Thereafter, for example, the same conductive paste is printed in a predetermined pattern on the plurality of ceramic green sheets 111A by, for example, a screen printing method and dried to form the in-plane conductor portion 112A and the first and second terminal electrode portions 113A and 113B. It is formed as shown in FIG. Further, a conductive paste is applied in a predetermined pattern on a resin film 100 such as PET and dried to form the third terminal electrode portion 113C. Next, a cavity opening having a predetermined size is opened in a predetermined ceramic green sheet 111A using, for example, a laser beam or a mold. Since the cavity C shown in FIG. 1A has a stepped portion, as shown in FIG. 2A, two types of large and small holes C ′ and C ″ are provided as openings for the cavity.

次いで、キャビティ用の大小の開口部Ｃ’、Ｃ”を有する複数のセラミックグリーンシート１１１Ａ、その他の複数のセラミックグリーンシート１１１Ａ及び第３の端子電極部１１３Ｃを下向きにして樹脂フィルム１００を積層した後、４０〜１００℃の温度、１０〜１５０ＭＰａの圧力で等方圧プレスにより圧着してセラミックグリーン積層体１１１を得る。これによりセラミックグリーン積層体１１１の主面を平坦化することができる。   Next, after laminating the resin film 100 with the plurality of ceramic green sheets 111A having large and small openings C ′ and C ″ for the cavity, the other plurality of ceramic green sheets 111A, and the third terminal electrode portion 113C facing downward The ceramic green laminate 111 is obtained by pressure bonding by an isotropic press at a temperature of 40 to 100 ° C. and a pressure of 10 to 150 MPa, whereby the main surface of the ceramic green laminate 111 can be flattened.

然る後、セラミックグリーン積層体１１１を例えば所定温度で焼成して、図２の（ｂ）に示すセラミック積層体１１を得る。導電性ペーストの金属材料粉末がＡｇ系の場合には例えば空気中８５０℃前後の温度で焼成し、その金属材料粉末がＣｕ系の場合には例えばＮ２ガス中９５０℃前後の温度で焼成する。 Thereafter, the ceramic green laminate 111 is fired at a predetermined temperature, for example, to obtain the ceramic laminate 11 shown in FIG. When the metal material powder of the conductive paste is Ag-based, it is fired at a temperature of about 850 ° C. in air, for example. When the metal material powder is Cu-based, it is baked at a temperature of about 950 ° C. in N 2 gas, for example. .

更に、図２の（ｃ）に示すように、セラミック積層体１１のキャビティＣを上向きにした後、第１の端子電極１３Ａのうち、導電性樹脂部１４を設ける部分が開口されたマスク２００を用いて導電性ペーストをスクリーン印刷すると、所望の第１の端子電極１３Ａの表面及びセラミック積層体１１との境界を覆う導電性樹脂層１１４が形成される。その後、導電性樹脂層１１４を１５０〜２００℃程度で熱処理し、導電性樹脂層１１４の熱硬化性樹脂を硬化させて、導電性樹脂部１４を形成することで、図１の（ａ）に示すセラミック多層基板１０を得ることができる。この導電性樹脂部１４は、前述したように５〜１０００μｍの厚みをもって形成されている。   Further, as shown in FIG. 2 (c), after the cavity C of the ceramic laminate 11 is directed upward, a mask 200 in which a portion where the conductive resin portion 14 is provided in the first terminal electrode 13A is opened. When the conductive paste is used for screen printing, a conductive resin layer 114 that covers the desired surface of the first terminal electrode 13A and the boundary with the ceramic laminate 11 is formed. Thereafter, the conductive resin layer 114 is heat-treated at about 150 to 200 ° C., the thermosetting resin of the conductive resin layer 114 is cured, and the conductive resin portion 14 is formed. The ceramic multilayer substrate 10 shown can be obtained. As described above, the conductive resin portion 14 is formed with a thickness of 5 to 1000 μm.

また、セラミックグリーン積層体を焼成する時には、焼成前後で平面方向の収縮がなく面方向の寸法が実質的に変化しない無収縮工法を用いることもできる。この場合には、例えば、図３の（ａ）に示すように拘束層３００上に、キャビティ用の孔Ｃ’、 Ｃ”を有する複数のセラミックグリーンシート１１１Ａ及びその他の複数のセラミックグリーンシート１１１Ａを積層した後、上面に拘束層３００Ａを配置し、上下の拘束層３００、３００Ａを介してセラミックグリーンシート１１１Ａの積層体を４０〜１００℃の温度、１０〜１５０ＭＰａの圧力で圧着して圧着体１１１’を得る。ここで、拘束層３００、３００Ａとしては、セラミックグリーンシート１１１Ａの焼結温度では焼結しない難焼結性粉末として例えばＡｌ２Ｏ３を主成分として含み、有機バインダを副成分として含むスラリーから同図に示すようにシート状に形成されたものを用いる。そして、キャビティＣ側の拘束層３００Ａにはキャビティの大きな開口部Ｃ’に即した開口部と導電性樹脂部１４に相当する開口部３００Ｂがそれぞれ形成されている。この圧着体１１１’を前述の場合と同様に焼成する、その後、同図の（ｂ）に示すように拘束層３００Ａの開口部３００Ｂ内に導電性樹脂材料を充填し、硬化させて導電性樹脂層１１４を形成した後、導電性樹脂層１１４を熱処理して硬化させる。その後、拘束層３００、３００Ａを除去する。これによって導電性樹脂部１４を有する図１の（ａ）に示すセラミック多層基板１０を得ることができる。 Further, when firing the ceramic green laminate, a non-shrinking method can be used in which there is no shrinkage in the plane direction before and after firing and the dimensions in the plane direction do not change substantially. In this case, for example, as shown in FIG. 3A, a plurality of ceramic green sheets 111A having cavities C ′ and C ″ and a plurality of other ceramic green sheets 111A are formed on the constraining layer 300. After the lamination, the constraining layer 300A is disposed on the upper surface, and the laminate of the ceramic green sheets 111A is pressure-bonded at a temperature of 40 to 100 ° C. and a pressure of 10 to 150 MPa via the upper and lower constraining layers 300 and 300A. Here, the constraining layers 300 and 300A include, for example, Al 2 O 3 as a main component as a non-sinterable powder that does not sinter at the sintering temperature of the ceramic green sheet 111A, and an organic binder as a subcomponent. The slurry formed in the form of a sheet as shown in the figure is used, and the constraining layer 300A on the cavity C side Are respectively formed with an opening corresponding to the opening C ′ having a large cavity and an opening 300B corresponding to the conductive resin portion 14. The pressure-bonded body 111 ′ is fired in the same manner as described above. As shown in FIG. 6B, after filling the opening 300B of the constraining layer 300A with a conductive resin material and curing to form the conductive resin layer 114, the conductive resin layer 114 is cured by heat treatment. After that, the constraining layers 300 and 300A are removed, whereby the ceramic multilayer substrate 10 shown in FIG.

上述のようにしてセラミック多層基板１０を作製した後、キャビティＣの底面に接着剤で半導体素子２０を固定した後、ボンディングワイヤー２０Ａによって半導体素子２０の端子電極（図示せず）とキャビティＣ内の水平面に形成された第２の端子電極１３Ｂを接続する。また、セラミック多層基板１０の上面には第１、第２の表面実装部品３０Ａ、３０Ｂそれぞれの端子電極（図示せず）を、半田ボールまたは導電性樹脂を用いて第３の端子電極１３Ｃに接続する。更に、金属製ケース４０を取り付けると、セラミック多層基板１０に半導体素子２０及び第１、第２の表面実装部品３０Ａ、３０Ｂがそれぞれ実装された図１の（ａ）に示す電子部品を得ることができる。   After manufacturing the ceramic multilayer substrate 10 as described above, the semiconductor element 20 is fixed to the bottom surface of the cavity C with an adhesive, and then the terminal electrode (not shown) of the semiconductor element 20 and the inside of the cavity C are bonded by the bonding wire 20A. The second terminal electrode 13B formed on the horizontal plane is connected. Further, terminal electrodes (not shown) of the first and second surface mount components 30A and 30B are connected to the third terminal electrode 13C on the upper surface of the ceramic multilayer substrate 10 by using solder balls or conductive resin. To do. Further, when the metal case 40 is attached, the electronic component shown in FIG. 1A in which the semiconductor element 20 and the first and second surface mount components 30A and 30B are mounted on the ceramic multilayer substrate 10 can be obtained. it can.

以上説明したように本実施形態によれば、セラミック多層基板１０をマザー基板５０に接続する場合に使用される第１の端子電極１３Ａの表面に導電性樹脂部１４を設け、この導電性樹脂部１４が第１の端子電極１３Ａ及び第１の端子電極１３Ａとセラミック積層体１１との境界部とを覆うように形成され、しかもセラミック積層体１１の下面に対して凸状に突出して形成されているため、セラミック多層基板１０が実装されたマザー基板５０が落下するなどして、マザー基板５０に衝撃力が作用しても、マザー基板５０からの衝撃力を導電性樹脂部１４によって吸収し、セラミック積層体１１への衝撃力を緩和することができる。その結果、セラミック多層基板１０におけるセラミック積層体１１と内部導体パターン１２及び外部導体パターン１３との収縮挙動差に起因する隙間等においてクラックが発生することを防止することができ、セラミック多層基板１０としての信頼性を向上させることができる。また、マザー基板５０に撓み等の変形があっても、導電性樹脂部１４がその変形に追随し、マザー基板５０からの集中応力を緩和して、セラミック積層体１１でのクラックの発生を防止することができる。また、凸状の導電性樹脂部１４の高さは、セラミック積層体１１の下面から５〜１００μｍに設定されているため、セラミック多層基板１０とマザー基板５０との間の導通性を阻害することなく、マザー基板５０からセラミック多層基板１０への衝撃をより確実に緩和することができ、信頼性を更に高めることができる。   As described above, according to the present embodiment, the conductive resin portion 14 is provided on the surface of the first terminal electrode 13A used when the ceramic multilayer substrate 10 is connected to the mother substrate 50, and the conductive resin portion. 14 is formed so as to cover the first terminal electrode 13 </ b> A and the boundary between the first terminal electrode 13 </ b> A and the ceramic laminate 11, and is formed so as to protrude in a convex shape with respect to the lower surface of the ceramic laminate 11. Therefore, even if the mother substrate 50 on which the ceramic multilayer substrate 10 is mounted falls and an impact force acts on the mother substrate 50, the impact force from the mother substrate 50 is absorbed by the conductive resin portion 14, The impact force on the ceramic laminate 11 can be reduced. As a result, it is possible to prevent cracks from occurring in gaps or the like due to differences in shrinkage behavior between the ceramic laminate 11 and the inner conductor pattern 12 and the outer conductor pattern 13 in the ceramic multilayer substrate 10. Reliability can be improved. Further, even if the mother substrate 50 is deformed such as bending, the conductive resin portion 14 follows the deformation, and the concentrated stress from the mother substrate 50 is relieved to prevent generation of cracks in the ceramic laminate 11. can do. Moreover, since the height of the convex conductive resin portion 14 is set to 5 to 100 μm from the lower surface of the ceramic laminate 11, the conductivity between the ceramic multilayer substrate 10 and the mother substrate 50 is inhibited. In addition, the impact from the mother substrate 50 to the ceramic multilayer substrate 10 can be more reliably mitigated, and the reliability can be further improved.

また、本実施形態によれば、等方圧プレスによりセラミックグリーン積層体１１１の上下両面を平坦化するため、スクリーン印刷により第１の端子電極１３Ａ上に導電性樹脂部１４を形成することができる。また、本実施形態によれば、第１の端子電極１３Ａは、セラミック積層体１１と同時に焼成されているため、焼結金属によって形成されていて、導通性に優れているが、表面が粗く、セラミック積層体１１との間に僅かな隙間が発生しているため、めっき膜１５を形成する時にめっき液が第１の端子電極１３Ａの表面に残留すると共に、めっき液が隙間から侵入しやすくなっている。ところが、本実施形態では第１の端子電極１３Ａの表面及び第１端子電極１３Ａとセラミック積層体１１との隙間を導電性樹脂部１４によって覆っているため、第１の端子電極１３Ａの表面にめっき液が残留したり、隙間からめっき液が侵入することがない。従って、従来であれば、端子電極の表面に残留しためっき液や隙間に侵入しためっき液がセラミック多層基板１０の半田付けに行われるリフロー工程における熱でめっき液が膨張し、破裂するなどして半田を周囲に飛散させる不具合を生じていたが、本実施形態ではこのような不具合を生じることがない。   In addition, according to the present embodiment, since the upper and lower surfaces of the ceramic green laminate 111 are flattened by isotropic pressure pressing, the conductive resin portion 14 can be formed on the first terminal electrode 13A by screen printing. . In addition, according to the present embodiment, the first terminal electrode 13A is fired at the same time as the ceramic laminate 11, and thus is formed of sintered metal and has excellent conductivity, but the surface is rough. Since a slight gap is generated between the ceramic laminate 11 and the plating film 15 is formed, the plating solution remains on the surface of the first terminal electrode 13A and the plating solution easily enters from the gap. ing. However, in the present embodiment, the surface of the first terminal electrode 13A and the gap between the first terminal electrode 13A and the ceramic laminate 11 are covered with the conductive resin portion 14, so that the surface of the first terminal electrode 13A is plated. The solution does not remain or the plating solution does not enter from the gap. Therefore, conventionally, the plating solution that has remained on the surface of the terminal electrode or the plating solution that has entered the gap expands and bursts due to heat in the reflow process in which the ceramic multilayer substrate 10 is soldered. Although the trouble which disperses solder to the circumference has arisen, in this embodiment, such a trouble does not arise.

また、本実施形態によれば、導電性樹脂部１４の表面にめっき膜１５が形成されているため、マザー基板５０の表面電極５０Ａと電気的に確実に接続することができる。更に、導電性樹脂部１４とセラミック積層体１１との間の接合力は、導電性樹脂部１４と第１の端子電極１３Ａとの接合力より大きいことから、本実施形態では導電性樹脂部１４が第１の端子電極１３Ａとセラミック積層体１１の双方に接合されているため、導電性樹脂部１４の接合力が強化され、導電性樹脂部１４のセラミック積層体１１からの脱落を確実に防止することができる。   In addition, according to the present embodiment, since the plating film 15 is formed on the surface of the conductive resin portion 14, it can be reliably connected to the surface electrode 50 </ b> A of the mother substrate 50. Furthermore, since the bonding force between the conductive resin portion 14 and the ceramic laminate 11 is larger than the bonding force between the conductive resin portion 14 and the first terminal electrode 13A, in this embodiment, the conductive resin portion 14 is used. Is bonded to both the first terminal electrode 13A and the ceramic laminate 11, the bonding force of the conductive resin portion 14 is strengthened, and the drop of the conductive resin portion 14 from the ceramic laminate 11 is surely prevented. can do.

第２の実施形態
本実施形態のセラミック多層基板１０Ａは、例えば図４の（ａ）、（ｂ）に示すように、第１の実施形態における第１の端子電極１３Ａを省略し、ビアホール導体１２Ｂの下面が第３の端子電極を兼用する点に特徴がある。その他は、第１の実施形態に準じて構成さているため、第１の実施形態と同一または相当部分には同一符号を附して本実施形態を説明する。 Second Embodiment A ceramic multilayer substrate 10A according to the present embodiment omits the first terminal electrode 13A according to the first embodiment, for example, as shown in FIGS. This is characterized in that the lower surface of each also serves as the third terminal electrode. Since the rest is configured according to the first embodiment, the same reference numerals are given to the same or corresponding parts as in the first embodiment, and this embodiment will be described.

本実施形態では、図４の（ａ）に示すようにキャビティＣを囲むビアホール導体１２Ｂの下面がセラミック積層体１１の下面において露呈し、その下面とセラミック積層体１１の下面とが面一に形成されており、第１の端子電極が省略されている。ビアホール導体１２Ｂが第１の端子電極を兼ねるため、第１の端子電極を省略できる反面、ビアホール導体はその体積が大きいため、金属材料とセラミック材料の収縮挙動の差によりスクリーン印刷による第１の端子電極１３Ａよりもセラミック積層体１１との間に隙間が生じやすくなる。しかし、本実施形態では、同図の（ｂ）に拡大して示すように導電性樹脂部１４がビアホール導体１２Ｂの下面及びビアホール導体１２Ｂとセラミック積層体１１との境界を覆うように凸状に形成され、その表面にめっき膜１５が形成されている。従って、ビアホール導体１２Ｂが第１の端子電極を兼用しても、第１の実施形態と同様の作用効果を期することができる他、第１の端子電極の形成工程を省略することができる。   In this embodiment, as shown in FIG. 4A, the lower surface of the via-hole conductor 12B surrounding the cavity C is exposed on the lower surface of the ceramic laminate 11, and the lower surface and the lower surface of the ceramic laminate 11 are formed flush with each other. The first terminal electrode is omitted. Since the via hole conductor 12B also serves as the first terminal electrode, the first terminal electrode can be omitted. However, since the via hole conductor has a large volume, the first terminal by screen printing is caused by a difference in shrinkage behavior between the metal material and the ceramic material. A gap is more likely to be formed between the ceramic laminate 11 and the electrode 13A. However, in this embodiment, the conductive resin portion 14 is convex so as to cover the lower surface of the via-hole conductor 12B and the boundary between the via-hole conductor 12B and the ceramic laminate 11 as shown in an enlarged view in FIG. The plating film 15 is formed on the surface. Therefore, even if the via-hole conductor 12B also serves as the first terminal electrode, the same effect as that of the first embodiment can be obtained, and the step of forming the first terminal electrode can be omitted.

第３の実施形態
本実施形態のセラミック多層基板１０Ｂは、図５に示すようにビアホール導体１２Ｂがセラミック積層体１１の下面から導電性樹脂部１４内へ突出して形成されたものであり、その他は第２の実施形態に準じて構成されている。従って、第２の実施形態と同一または相当部分には同一符号を附して本実施形態について説明する。 Third Embodiment A ceramic multilayer substrate 10B according to the present embodiment is formed by projecting via-hole conductors 12B from the lower surface of the ceramic laminate 11 into the conductive resin portion 14 as shown in FIG. It is configured according to the second embodiment. Therefore, the present embodiment will be described with the same reference numerals assigned to the same or corresponding parts as in the second embodiment.

本実施形態におけるビアホール導体１２Ｂの突出量は、５μｍ以上あることが好ましい。ビアホール導体１２Ｂをセラミック積層体１１の下面から導電性樹脂部１４内へ５μｍ以上突出させることで、ビアホール導体１２Ｂと導電性樹脂部１４との接合面積が大きくなる。これにより、ビアホール導体１２Ｂと導電性樹脂部１４との導通面積が大きくなって導通性が高くなることで、セラミック多層基板１０Ｂの信頼性が向上する。また、導電性樹脂部１４とビアホール導体１２Ｂとの接合面積が大きくなって接合力が強くなる。しかも、ビアホール導体１２Ｂが焼結金属であり、その表面粗さが最大数１０μｍに達することから、導電性樹脂部１４に対するビアホール導体１２Ｂによるアンカー効果を期することができる。その他は第２の実施形態と同様の作用効果を期することができる。   The protruding amount of the via-hole conductor 12B in this embodiment is preferably 5 μm or more. By protruding the via-hole conductor 12B from the lower surface of the ceramic laminate 11 into the conductive resin portion 14 by 5 μm or more, the bonding area between the via-hole conductor 12B and the conductive resin portion 14 is increased. As a result, the conduction area between the via-hole conductor 12B and the conductive resin portion 14 is increased and the conductivity is increased, so that the reliability of the ceramic multilayer substrate 10B is improved. Further, the bonding area between the conductive resin portion 14 and the via-hole conductor 12B is increased, and the bonding force is increased. Moreover, since the via-hole conductor 12B is a sintered metal and the surface roughness reaches a maximum of several tens of micrometers, an anchor effect by the via-hole conductor 12B on the conductive resin portion 14 can be expected. Otherwise, the same effects as those of the second embodiment can be expected.

第４の実施形態
本実施形態のセラミック多層基板１０Ｃは、図６に示すように第１の端子電極１３Ａの表面の中央部がセラミック積層体１１の下面から導電性樹脂部１４内へ突出して形成されたものであり、その他は第１の実施形態に準じて構成されている。従って、第１の実施形態と同一または相当部分には同一符号を附して本実施形態について説明する。 Fourth Embodiment A ceramic multilayer substrate 10C of the present embodiment is formed such that the center portion of the surface of the first terminal electrode 13A protrudes from the lower surface of the ceramic laminate 11 into the conductive resin portion 14 as shown in FIG. The others are configured according to the first embodiment. Accordingly, the present embodiment will be described with the same reference numerals assigned to the same or corresponding parts as in the first embodiment.

本実施形態における第１の端子電極１３Ａは、その下面中央部が突出し、これに接続されたビアホール導体１２Ｂと同一径に形成されている。第１の端子電極１３Ａの中央部の突出量は、第３の実施形態のセラミック多層基板１０Ｂの場合と同様に５μｍ以上あることが好ましい。この場合には、ビアホール導体１２Ｂを第１の端子電極として突出させた場合よりも導電性樹脂部１４との接合面積が大きく、第１の端子電極１３Ａと導電性樹脂部１４との電気的接合及び機械的接合を高めることができ、信頼性を更に高めることができる。その他は第１の実施形態と同様の作用効果を期することができる。   The first terminal electrode 13A in the present embodiment protrudes from the center of the lower surface and has the same diameter as the via-hole conductor 12B connected thereto. The protruding amount of the central portion of the first terminal electrode 13A is preferably 5 μm or more as in the case of the ceramic multilayer substrate 10B of the third embodiment. In this case, the bonding area with the conductive resin portion 14 is larger than when the via-hole conductor 12B is protruded as the first terminal electrode, and the electric bonding between the first terminal electrode 13A and the conductive resin portion 14 is performed. In addition, mechanical bonding can be enhanced, and reliability can be further enhanced. The other effects can be obtained as in the first embodiment.

第５の実施形態
本実施形態のセラミック多層基板１０Ｄは、図７に示すように第１の端子電極１３Ａがセラミック積層体１１の下面の外周縁部に沿って配列されている。そして、導電性樹脂部１４は、セラミック積層体１１の四隅に配置された４箇所の第１の端子電極１３Ａにそれぞれ形成されている。セラミック積層体１１の四隅に配置された各第１の端子電極１３Ａにはマザー基板からの衝撃による応力が集中しやすい。これらの部分に導電性樹脂部１４を設けることによって、マザー基板からの衝撃による集中応力を４箇所の導電性樹脂部１４によって吸収し、セラミック多層基板１０Ｄに対する衝撃を緩和して、セラミック多層基板１０Ｄで発生するクラックを効果的に防止することができる。本実施形態では第１の端子電極１３Ａに導電性樹脂部１４を設けているが、第１の端子電極１３Ａを省略し、ビアホール導体がセラミック積層体１１の下面に露呈している場合には、四隅のビアホール導体に導電性樹脂部を設ければ良い。勿論、これらの導電性樹脂部１４の表面にはめっき膜が施されている。 Fifth Embodiment As shown in FIG. 7, in the ceramic multilayer substrate 10 </ b> D of the present embodiment, the first terminal electrodes 13 </ b> A are arranged along the outer peripheral edge of the lower surface of the ceramic laminate 11. The conductive resin portion 14 is formed on each of the four first terminal electrodes 13 </ b> A arranged at the four corners of the ceramic laminate 11. Stress due to an impact from the mother substrate tends to concentrate on the first terminal electrodes 13A arranged at the four corners of the ceramic laminate 11. By providing the conductive resin portions 14 in these portions, the concentrated stress due to the impact from the mother substrate is absorbed by the four conductive resin portions 14, and the impact on the ceramic multilayer substrate 10D is alleviated, and the ceramic multilayer substrate 10D. The crack which generate | occur | produces in can be prevented effectively. In the present embodiment, the conductive resin portion 14 is provided on the first terminal electrode 13A, but when the first terminal electrode 13A is omitted and the via-hole conductor is exposed on the lower surface of the ceramic laminate 11, What is necessary is just to provide an electroconductive resin part in the via-hole conductor of four corners. Of course, the surface of these conductive resin portions 14 is provided with a plating film.

第６の実施形態
本実施形態のセラミック多層基板１０Ｅの場合には、図８に示すようにセラミック積層体１１の下面の外周縁部に沿って配列された第１の端子電極１３Ａのうち、例えば短辺側に沿って配列された第１の端子電極１３Ａの全てに導電性樹脂部１４が形成されている以外は、第５の実施形態に準じて構成されている。本実施形態によれば、マザー基板から衝撃が集中しやすい四隅の第１の端子電極１３Ａの他、短辺側の四隅の間にある第１の端子電極１３Ａにも導電性樹脂部１４が形成されているため、マザー基板からの衝撃による集中応力を四隅以外の第１の端子電極１３Ａにも分散できるため、四隅の導電性樹脂部１４における負荷が軽減され、耐衝撃性が向上すると共に長寿命化する。 Sixth Embodiment In the case of the ceramic multilayer substrate 10E of the present embodiment, among the first terminal electrodes 13A arranged along the outer peripheral edge of the lower surface of the ceramic laminate 11 as shown in FIG. Except that the conductive resin portion 14 is formed on all of the first terminal electrodes 13A arranged along the short side, the configuration is the same as that of the fifth embodiment. According to the present embodiment, the conductive resin portion 14 is also formed on the first terminal electrode 13A located between the four corners on the short side, in addition to the first terminal electrode 13A on the four corners where the impact is likely to concentrate from the mother substrate. Therefore, the concentrated stress due to the impact from the mother substrate can be distributed to the first terminal electrodes 13A other than the four corners, so that the load on the conductive resin portion 14 at the four corners is reduced, and the impact resistance is improved and the length is increased. Life expectancy.

第１〜第６の実施形態では、セラミック積層体１１の下面に導電性樹脂層１１４を印刷により形成し、そのまま硬化させて導電性樹脂部１４を形成している。しかしながら、導電性樹脂層１１４を印刷したまま硬化させた場合には、その表面が必ずしも平滑になっているとは限らない。また、複数の導電性樹脂間の表面が同一高さであるとも限らない。そこで、第７の実施形態では導電性樹脂部１４の表面を平滑に調整することができ、また、複数の導電性樹脂部１４の表面を同一高さに調整することができるセラミック多層基板の製造方法について説明する。   In the first to sixth embodiments, the conductive resin layer 114 is formed on the lower surface of the ceramic laminate 11 by printing and cured as it is to form the conductive resin portion 14. However, when the conductive resin layer 114 is cured while being printed, the surface is not necessarily smooth. Further, the surface between the plurality of conductive resins is not necessarily the same height. Therefore, in the seventh embodiment, the surface of the conductive resin portion 14 can be adjusted smoothly, and the production of the ceramic multilayer substrate that can adjust the surfaces of the plurality of conductive resin portions 14 to the same height is possible. A method will be described.

第７の実施形態
本実施形態のセラミック多層基板の製造方法では、例えば図９に示すようにセラミック積層体１１の下面に形成された導電性樹脂部１４の表面をそれぞれ平滑にすると共にそれぞれの表面を同一の高さに揃えることができる製造方法である。本実施形態ではセラミック積層体１１の下面に導電性樹脂層１１４を形成するまでの工程は、第１の実施形態に準じて行われる。 Seventh Embodiment In the method for manufacturing a ceramic multilayer substrate according to the present embodiment, for example, as shown in FIG. 9, the surface of the conductive resin portion 14 formed on the lower surface of the ceramic laminate 11 is smoothed and the respective surfaces are made. It is a manufacturing method which can arrange | equalize with the same height. In the present embodiment, the steps until the conductive resin layer 114 is formed on the lower surface of the ceramic laminate 11 are performed according to the first embodiment.

本実施形態では、図９の（ａ）に示すようにセラミック積層体１１の下面に形成された導電性樹脂層１１４を例えばオーブン内で熱処理する際に、導電性樹脂層１１４が完全に硬化する前にオーブンからセラミック積層体１１を取り出す。導電性樹脂層１１４の硬化度は一概に規定できないが、その表面を指で押して指紋が残る程度の硬さが好ましい。この状態の導電性樹脂層を以下では半硬化状態と称する。導電性樹脂層が紫外線硬化樹脂を含む場合には、紫外線照射により熱硬化処理と同程度まで導電性樹脂層を硬化させる。その後、同図の（ａ）に示すようにセラミック積層体１１の導電性樹脂層１１４の上方に、片面に平滑面を有する平滑部材２００を平滑面が下向きになるように配置する。   In the present embodiment, as shown in FIG. 9A, when the conductive resin layer 114 formed on the lower surface of the ceramic laminate 11 is heat-treated in, for example, an oven, the conductive resin layer 114 is completely cured. Before removing the ceramic laminate 11 from the oven. The degree of cure of the conductive resin layer 114 cannot be generally defined, but is preferably hard enough to leave a fingerprint when the surface is pressed with a finger. Hereinafter, the conductive resin layer in this state is referred to as a semi-cured state. When the conductive resin layer contains an ultraviolet curable resin, the conductive resin layer is cured to the same extent as the thermosetting treatment by ultraviolet irradiation. Thereafter, as shown in FIG. 5A, the smooth member 200 having a smooth surface on one side is disposed above the conductive resin layer 114 of the ceramic laminate 11 so that the smooth surface faces downward.

平滑部材２００は、例えば重さが５〜１０ｇで、平滑面の表面粗さが３μｍ以下（セラミック積層体１１の表面粗さ以下であることが好ましい）の平滑性を有し、全体の反りが１０μｍ以下のガラス板が好ましい。そして、ガラス板の平滑面にはフッ素等による離型処理が施されていることが好ましい。   The smooth member 200 has a smoothness of, for example, a weight of 5 to 10 g, and a smooth surface having a surface roughness of 3 μm or less (preferably less than the surface roughness of the ceramic laminate 11), and the entire warp. A glass plate of 10 μm or less is preferred. The smooth surface of the glass plate is preferably subjected to release treatment with fluorine or the like.

更に、図９の（ｂ）に示すように平滑部材２００をセラミック積層体１１の半硬化状態の導電性樹脂層１１４上に載置し、平滑部材２００の平滑面を複数箇所の導電性樹脂層１１４の表面に接触させた状態で導電性樹脂層１１４の熱処理を行うと、平滑部材２００の重みで各導電性樹脂層１１４がやや圧縮されてそれぞれの表面が平滑部材２００の平滑面に倣って同時に平滑化すると共にそれぞれの表面が同一の高さに揃って、導電性樹脂層１１４が完全に熱硬化して導電性樹脂部１４として形成されることになる。導電性樹脂層１１４が硬化する時に、平滑部材２００に所定の押圧力を付与することにより、導電性樹脂層１１４の表面をより確実に平滑化することができる。押圧力としては、例えば１〜５ｇ／ｃｍ２の範囲が好ましい。平滑部材２００による平滑化処理と並行して導電性樹脂層１１４を完全に硬化させた後、同図の（ｃ）に示すように平滑部材２００を除去すると、表面が平滑で同一の高さに揃った導電性樹脂部１４が形成される。 Further, as shown in FIG. 9B, the smooth member 200 is placed on the semi-cured conductive resin layer 114 of the ceramic laminate 11, and the smooth surface of the smooth member 200 is formed at a plurality of conductive resin layers. When the conductive resin layer 114 is heat-treated while being in contact with the surface of 114, each conductive resin layer 114 is slightly compressed by the weight of the smooth member 200, and each surface follows the smooth surface of the smooth member 200. At the same time, the surfaces are leveled and the conductive resin layer 114 is completely thermoset to form the conductive resin portion 14. By applying a predetermined pressing force to the smooth member 200 when the conductive resin layer 114 is cured, the surface of the conductive resin layer 114 can be more reliably smoothed. As a pressing force, the range of 1-5 g / cm < 2 > is preferable, for example. After the conductive resin layer 114 is completely cured in parallel with the smoothing process by the smooth member 200, the smooth member 200 is removed as shown in FIG. A uniform conductive resin portion 14 is formed.

引き続き、第１の実施形態と同様に、導電性樹脂部１４に表面にめっき処理を施して第１の端子電極を形成した後、セラミック積層体１１のキャビティＣ内に半導体素子を実装すると共にその反対側の面に第１、第２の表面実装部品を実装し、更に、第１、第２の表面実装部品を樹脂封止することによって第１の接続端子の一部が突出したセラミック多層基板を得ることができる。   Subsequently, as in the first embodiment, after the surface of the conductive resin portion 14 is plated to form the first terminal electrode, the semiconductor element is mounted in the cavity C of the ceramic laminate 11 and the A ceramic multilayer substrate in which the first and second surface mount components are mounted on the opposite surface, and the first and second surface mount components are resin-sealed to project a part of the first connection terminals. Can be obtained.

本実施形態によれば、第１の端子電極１３Ａの表面が平滑でしかもその表面が同一高さであるため、導通性等の電気的特性を確認する際に、テストピンとの接触不良が起こりにくく、電気的特性の誤判断を改善することができる。また、例えば図１０に示すように本実施形態のセラミック多層基板１０Ｆを製品として出荷する時には、セラミック多層基板１０Ｆをテープ３００に所定間隔おきに多数配列して形成された凹陥部３００Ａに固定してユーザーに出荷する。この際、セラミック多層基板１０Ｆの導電性樹脂部１４の表面が同一高さに揃っているため、セラミック多層基板１０Ｆをテープ３００の凹陥部３００Ａ内で水平に配置することができる。そのため、ユーザーでは、セラミック多層基板１０Ｆをマザー基板に実装する際に、マウンターによりセラミック多層基板１０Ｆを確実にピックアップすることができる。   According to the present embodiment, since the surface of the first terminal electrode 13A is smooth and the surface is the same height, poor contact with the test pin is unlikely to occur when confirming electrical characteristics such as conductivity. In addition, misjudgment of electrical characteristics can be improved. Further, for example, as shown in FIG. 10, when the ceramic multilayer substrate 10F of the present embodiment is shipped as a product, the ceramic multilayer substrate 10F is fixed to the recessed portions 300A formed by arranging a large number of ceramic multilayer substrates 10F on the tape 300 at predetermined intervals. Ship to user. At this time, since the surface of the conductive resin portion 14 of the ceramic multilayer substrate 10F is aligned at the same height, the ceramic multilayer substrate 10F can be horizontally disposed in the recessed portion 300A of the tape 300. Therefore, the user can reliably pick up the ceramic multilayer substrate 10F by the mounter when mounting the ceramic multilayer substrate 10F on the mother substrate.

更に、導電性樹脂部１４の表面が平滑で同一高さになっているため、マザー基板の表面電極との接続信頼性が向上する。また、マザー基板と半田等の接続材料の厚みが均一になるため、実装後のセラミック多層基板１０Ｆに傾きかがなく実装高さを低くすることができ、更に落下等による衝撃による応力が複数の第１の端子電極に均等にかかり、耐衝撃性が向上する。   Furthermore, since the surface of the conductive resin portion 14 is smooth and has the same height, the connection reliability with the surface electrode of the mother board is improved. Further, since the thickness of the connecting material such as the mother substrate and the solder becomes uniform, the mounted ceramic multilayer substrate 10F is not inclined, and the mounting height can be lowered. Evenly applied to the first terminal electrode, impact resistance is improved.

第７の実施形態の変形例
この変形例では平滑部材２０１として、例えば図１１、図１２に示すようにセラミック積層体１１の複数の導電性樹脂部１４に対応する凹部２０１Ａが片面に形成されたガラス板を用いること以外は、第７の実施形態の場合と同一要領で導電性樹脂部を形成する。この平滑部材２０１は、各図に示すように、セラミック積層体１１の下面の凸状の導電性樹脂層１１４に対応する凹部２０１Ａが形成され、凹部２０１Ａの底面が平滑面として形成されていると共に平滑面が同一深さに形成されている。そして、凹部２０１Ａの平滑面及び内周面には離型処理が施されている。凹部２０１Ａは導電性樹脂１１４の突出高さよりも浅く、導電性樹脂１１４の凸部と嵌合するようにやや広く形成されている。 Modified Example of Seventh Embodiment In this modified example, as the smooth member 201, for example, as shown in FIGS. 11 and 12, concave portions 201A corresponding to the plurality of conductive resin portions 14 of the ceramic laminate 11 are formed on one side. The conductive resin portion is formed in the same manner as in the seventh embodiment except that a glass plate is used. As shown in each drawing, the smooth member 201 has a recess 201A corresponding to the convex conductive resin layer 114 on the lower surface of the ceramic laminate 11, and the bottom surface of the recess 201A is formed as a smooth surface. Smooth surfaces are formed at the same depth. And the mold release process is performed to the smooth surface and inner peripheral surface of the recessed part 201A. The recessed portion 201A is shallower than the protruding height of the conductive resin 114, and is formed slightly wider so as to be fitted to the protruding portion of the conductive resin 114.

この平滑部材２０１の凹部２０１Ａを下向きにして、図１２の（ａ）に示すようにセラミック積層体１１の導電性樹脂層１１４側の上方に平滑部材２０１を配置する。この際、平滑部材２０１の凹部２０１Ａと半硬化状態の導電性樹脂層１１４との位置合わせを行っておく。次いで、同図の（ｂ）に示すように平滑部材２０１をセラミック積層体１１の半硬化状態の導電性樹脂層１１４上に載置して熱処理すると、平滑部材２０１の凹部２０１Ａが複数箇所の導電性樹脂層１１４のセラミック積層体１１からの突出部と嵌合した状態で平滑部材２０１の重みにより各導電性樹脂層１１４がやや圧縮されてそれぞれの表面が凹部２０１Ａの平滑面に倣って同時に平滑化すると共にそれぞれの導電性樹脂層１１４の表面が同一高さになる。その後、同図の（ｃ）に示すように平滑部材２０１を除去すると、表面が平滑で同一の高さに揃った複数の導電性樹脂部１４が形成される。尚、平滑部材２０１の凹部２０１Ａ内に予め半硬化状態の導電性樹脂を充填しておき、セラミック積層体１１の第１の端子電極１３Ａに導電性樹脂層１１４を転写して硬化させても良い。この変形例においても第７の実施形態と同様の作用効果を期することができる。   The smooth member 201 is disposed above the ceramic laminate 11 on the conductive resin layer 114 side, with the concave portion 201A of the smooth member 201 facing downward, as shown in FIG. At this time, the recess 201A of the smooth member 201 and the semi-cured conductive resin layer 114 are aligned. Next, when the smooth member 201 is placed on the semi-cured conductive resin layer 114 of the ceramic laminate 11 and heat-treated, as shown in FIG. Each conductive resin layer 114 is slightly compressed by the weight of the smooth member 201 in a state in which the conductive resin layer 114 is fitted to the protruding portion from the ceramic laminate 11, and the respective surfaces follow the smooth surface of the recess 201A and are simultaneously smoothed. And the surface of each conductive resin layer 114 becomes the same height. Thereafter, when the smooth member 201 is removed as shown in FIG. 5C, a plurality of conductive resin portions 14 having a smooth surface and the same height are formed. Alternatively, the recess 201A of the smooth member 201 may be filled with a semi-cured conductive resin in advance, and the conductive resin layer 114 may be transferred to the first terminal electrode 13A of the ceramic laminate 11 and cured. . Also in this modified example, the same effect as the seventh embodiment can be expected.

本発明は、上記各実施形態に何等制限されるものではない。例えば、上記各実施形態ではキャビティ付きのセラミック多層基板を例に挙げて説明したが、キャビティのないセラミック多層基板についても本発明を適用することができる。また、上記各実施形態ではキャビティ内の半導体素子が露呈している場合について説明したが、キャビティ内の半導体素子を熱伝導性に優れた樹脂等によって封止し、半導体素子からの放熱性を高めたものについても本発明を適用することができる。   The present invention is not limited to the above embodiments. For example, in each of the embodiments described above, a ceramic multilayer substrate with a cavity has been described as an example, but the present invention can also be applied to a ceramic multilayer substrate without a cavity. In each of the above embodiments, the case where the semiconductor element in the cavity is exposed has been described. However, the semiconductor element in the cavity is sealed with a resin or the like having excellent thermal conductivity to improve heat dissipation from the semiconductor element. The present invention can also be applied to those that have been used.

本発明は、例えば移動体通信端末等の携帯用の電子機器に用いられるセラミック多層基板及びその製造方法に対して広く利用することができる。   The present invention can be widely used for a ceramic multilayer substrate used for portable electronic devices such as mobile communication terminals and a method for manufacturing the same.

（ａ）〜（ｃ）はそれぞれ本発明のセラミック多層基板の一実施形態を示す図で、（ａ）はその断面図、（ｂ）は（ａ）の要部を拡大して示す断面図、（ｃ）は（ｂ）の下方からの平面図である。(A)-(c) is a figure which shows one Embodiment of the ceramic multilayer substrate of this invention, respectively, (a) is the sectional drawing, (b) is sectional drawing which expands and shows the principal part of (a), (C) is a top view from the bottom of (b). （ａ）〜（ｃ）はそれぞれ図１に示すセラミック多層基板の製造工程の要部を工程順に示す断面図である。(A)-(c) is sectional drawing which shows the principal part of the manufacturing process of the ceramic multilayer substrate shown in FIG. （ａ）、（ｂ）はそれぞれセラミック多層基板の他の製造工程の要部を工程順に示す断面図である。(A), (b) is sectional drawing which shows the principal part of the other manufacturing process of a ceramic multilayer substrate in order of a process, respectively. （ａ）、（ｂ）はそれぞれ本発明のセラミック多層基板の他の実施形態を示す図で、（ａ）はその断面図、（ｂ）は（ａ）の要部を拡大して示す断面図ある。(A), (b) is a figure which shows other embodiment of the ceramic multilayer substrate of this invention, respectively, (a) is the sectional drawing, (b) is sectional drawing which expands and shows the principal part of (a) is there. 本発明のセラミック多層基板の更に他の実施形態の要部を拡大して示す断面図ある。It is sectional drawing which expands and shows the principal part of other embodiment of the ceramic multilayer substrate of this invention. 本発明のセラミック多層基板の更に他の実施形態の要部を拡大して示す断面図ある。It is sectional drawing which expands and shows the principal part of other embodiment of the ceramic multilayer substrate of this invention. 本発明のセラミック多層基板の更に他の実施形態の全体を下面側からの斜視である。The whole other embodiment of the ceramic multilayer substrate of this invention is a perspective view from the lower surface side. 本発明のセラミック多層基板の更に他の実施形態の全体を下面側からの斜視である。The whole other embodiment of the ceramic multilayer substrate of this invention is a perspective view from the lower surface side. （ａ）〜（ｃ）はそれぞれ本発明のセラミック多層基板の製造方法の他の実施形態の製造工程の要部を工程順に示す断面図である。(A)-(c) is sectional drawing which shows the principal part of the manufacturing process of other embodiment of the manufacturing method of the ceramic multilayer substrate of this invention in order of a process. 図９に示す製造方法で製造されたセラミック多層基板を製品としてテープ上に配置した状態の一部を示す斜視図である。It is a perspective view which shows a part of the state which has arrange | positioned the ceramic multilayer substrate manufactured with the manufacturing method shown in FIG. 9 on a tape as a product. 本発明のセラミック多層基板の製造方法の更に他の実施形態に用いられる平滑部材を示す斜視図である。It is a perspective view which shows the smooth member used for further another embodiment of the manufacturing method of the ceramic multilayer substrate of this invention. （ａ）〜（ｃ）はそれぞれ図１１に示す平滑部材を用い製造工程の要部を工程順に示す断面図である。(A)-(c) is sectional drawing which shows the principal part of a manufacturing process in order of a process using the smooth member shown in FIG. 11, respectively.

符号の説明Explanation of symbols

１０、１０Ａ、１０Ｂ、１０Ｃ、１０Ｄ、１０Ｅ、１０Ｆ セラミック多層基板
１１ セラミック積層体
１１Ａ セラミック層
１２ 内部導体パターン
１２Ｂ ビアホール導体
１３ 外部導体パターン
１３Ａ 第１の端子電極（端子電極）
１４ 導電性樹脂部
１５ めっき膜
１１４ 導電性樹脂層
２００、２０１ 平滑部材
２０１Ａ 凹部 10, 10A, 10B, 10C, 10D, 10E, 10F Ceramic multilayer substrate 11 Ceramic laminate 11A Ceramic layer 12 Internal conductor pattern 12B Via-hole conductor 13 External conductor pattern 13A First terminal electrode (terminal electrode)
14 Conductive resin portion 15 Plating film 114 Conductive resin layer 200, 201 Smooth member 201A Recess

Claims (12)

複数のセラミック層を積層してなるセラミック積層体の内部に内部導体パターンを有し、上記セラミック積層体の主面に露出する端子電極を有するセラミック多層基板であって、
上記端子電極は、上記内部導体パターンを構成するビアホール導体に接続されていると共に上記端子電極の面積が上記ビアホール導体の断面積より大きく形成され、また、
上記端子電極の表面及び上記端子電極と上記セラミック積層体との境界部を覆い且つ上記主面に対して凸状となる導電性樹脂部が設けられており、
上記端子電極の表面は、中央部が上記主面から上記導電性樹脂部内に突出して上記導電性樹脂部に接合されている
ことを特徴とするセラミック多層基板。 A ceramic multilayer substrate having an internal conductor pattern inside a ceramic laminate formed by laminating a plurality of ceramic layers and having a terminal electrode exposed on the main surface of the ceramic laminate,
The terminal electrode is connected to a via-hole conductor constituting the internal conductor pattern and has an area of the terminal electrode larger than a cross-sectional area of the via-hole conductor,
Surfaces and conductive resin portion that Do a convex shape with respect to the boundary portion of the covering decoction且one above SL main surface of the terminal electrode and the ceramic laminate of the terminal electrode is provided,
The ceramic multilayer substrate , wherein the surface of the terminal electrode has a central portion protruding from the main surface into the conductive resin portion and joined to the conductive resin portion . 上記内部導体パターン及び上記端子電極は、上記セラミック積層体との同時焼成によって得られる焼結金属であることを特徴とする請求項１に記載のセラミック多層基板。   2. The ceramic multilayer substrate according to claim 1, wherein the internal conductor pattern and the terminal electrode are a sintered metal obtained by simultaneous firing with the ceramic laminate. 上記導電性樹脂部の表面にはめっき膜が形成されていることを特徴とする請求項１または請求項２に記載のセラミック多層基板。 The ceramic multilayer substrate according to claim 1 or 2 , wherein a plating film is formed on a surface of the conductive resin portion. 上記導電性樹脂部の高さは、上記主面に対して５〜１０００μｍであることを特徴とする請求項１〜請求項３のいずれか１項に記載のセラミック多層基板。 The height of the said conductive resin part is 5-1000 micrometers with respect to the said main surface, The ceramic multilayer substrate of any one of Claims 1-3 characterized by the above-mentioned. 上記セラミック積層体の上記主面には、その周縁部に複数の端子電極が配列されており、これらの端子電極のうち、少なくとも四隅の端子電極はそれぞれの表面の中央部が上記主面から突出して上記導電性樹脂部によって被覆されていることを特徴とする請求項１〜請求項４のいずれか１項に記載のセラミック多層基板。 A plurality of terminal electrodes are arranged on the peripheral surface of the main surface of the ceramic laminate, and among these terminal electrodes, at least the four corner terminal electrodes protrude from the main surface at the center of each surface. ceramic multilayer substrate according to any one of claims 1 to 4, characterized in that it is covered by the conductive resin portion Te. 複数のセラミック層を積層してなるセラミック積層体の内部に内部導体パターンを有し、上記セラミック積層体の主面に露出する端子電極を有するセラミック多層基板を作製する際に、
上記内部導体パターンを構成するビアホール導体にこのビアホール導体の断面積より大きな面積を有する上記端子電極を接続すると共に上記端子電極の表面の中央部が上記主面から突出する上記セラミック積層体を作製する第１の工程と、
上記端子電極の表面及び上記端子電極と上記セラミック積層体との境界部を覆い且つ上記主面に対して凸状となる導電性樹脂部を上記主面に形成する第２の工程と、を備えた
ことを特徴とするセラミック多層基板の製造方法。 When producing a ceramic multilayer substrate having an internal conductor pattern inside a ceramic laminate formed by laminating a plurality of ceramic layers and having terminal electrodes exposed on the main surface of the ceramic laminate,
The ceramic laminate is produced by connecting the terminal electrode having an area larger than the cross-sectional area of the via-hole conductor to the via-hole conductor constituting the internal conductor pattern and projecting the central portion of the surface of the terminal electrode from the main surface. A first step;
A second step of forming a conductive resin portion serving as a convex with respect to the surface and and the main surface has covering the boundary between the terminal electrode and the ceramic laminate of the terminal electrodes on the main surface, the A method for producing a ceramic multilayer substrate, comprising: 上記内部導体パターン及び上記端子電極を、上記セラミック積層体と同時焼成することを特徴とする請求項６に記載のセラミック多層基板の製造方法。 The method for manufacturing a ceramic multilayer substrate according to claim 6 , wherein the internal conductor pattern and the terminal electrode are simultaneously fired with the ceramic laminate. 上記導電性樹脂部を形成する際に、上記主面に導電性樹脂層を形成した後、平滑面を有する平滑部材を、上記平滑面が上記導電性樹脂層の表面に接触するように上記導電性樹脂層上に載置することを特徴とする請求項６または請求項７に記載のセラミック多層基板の製造方法。 When forming the conductive resin portion, after forming the conductive resin layer on the main surface, the conductive member is formed so that the smooth member having a smooth surface is in contact with the surface of the conductive resin layer. method for producing a ceramic multilayer substrate according to claim 6 or claim 7, characterized in that placed on the sexual resin layer. 上記平滑部材の平滑面を複数の上記導電性樹脂層の表面に同時に接触させて、上記各導電性樹脂層それぞれの表面を同一高さに形成することを特徴とする請求項８に記載のセラミック多層基板の製造方法。 9. The ceramic according to claim 8 , wherein the smooth surface of the smooth member is simultaneously brought into contact with the surfaces of the plurality of conductive resin layers to form the surfaces of the respective conductive resin layers at the same height. A method for producing a multilayer substrate. 上記平滑部材として、上記導電性樹脂層に対応する凹部を有し且つこの凹部内に上記平滑面が形成された板状部材を用いることを特徴とする請求項８または請求項９に記載のセラミック多層基板の製造方法。 As the smooth member, ceramic according to claim 8 or claim 9, characterized by using a plate-like member the smooth surface is formed on and within this recess has a recess corresponding to the conductive resin layer A method for producing a multilayer substrate. 上記導電性樹脂部の表面にめっき膜を形成することを特徴とする請求項６〜請求項１０のいずれか１項に記載のセラミック多層基板の製造方法。 The method for producing a ceramic multilayer substrate according to any one of claims 6 to 10 , wherein a plating film is formed on a surface of the conductive resin portion. 上記内部導体パターンを有するセラミックグリーンシート及び上記端子電極を有するセラミックグリーンシートを積層して未焼成のセラミック積層体を作製し、これをその両主面が平坦化するように加圧することを特徴とする請求項６〜請求項１１のいずれか１項に記載のセラミック多層基板の製造方法。 A ceramic green sheet having the inner conductor pattern and a ceramic green sheet having the terminal electrode are laminated to produce an unfired ceramic laminate, which is pressurized so that both main surfaces thereof are flattened. The method for producing a ceramic multilayer substrate according to any one of claims 6 to 11 .
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