JP4800287B2 - レジスト下のフィーチャのファセット制御のための基板処理方法及び基板処理装置 - Google Patents
レジスト下のフィーチャのファセット制御のための基板処理方法及び基板処理装置 Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/26—Processing photosensitive materials; Apparatus therefor
- G03F7/42—Stripping or agents therefor
- G03F7/427—Stripping or agents therefor using plasma means only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32697—Electrostatic control
- H01J37/32706—Polarising the substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
- H01L21/67207—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67253—Process monitoring, e.g. flow or thickness monitoring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- Microelectronics & Electronic Packaging (AREA)
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- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
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Description
Claims (14)
- 誘電体フィーチャの縁部ファセット高さを制御しながら基板上の誘電体フィーチャを覆うレジスト層を除去するための基板処理方法であり、アンテナと第1及び第2処理電極を備える基板処理チャンバ内で行うこの方法が
(a)誘電体フィーチャを覆うレジスト層を有する基板をチャンバ内に配置し、
(b)その下の誘電体フィーチャの縁部ファセット高さを制御しながらレジスト層を除去することを含み、(b)は
(i)CO2を含む処理ガスをチャンバ内に導入し、
(ii)処理ガスにエネルギーを印加することで行われ、(ii)は
(1)電源電圧をアンテナに印加し、
(2)第1及び第2処理電極に少なくとも10MHzの第1周波数を有する第1バイアス電圧と、4MHz未満の第2周波数を有する第2バイアス電圧を印加することで行われ、ここで第1バイアス電圧の第2バイアス電圧に対する電力レベル比が1/9以上であり、エネルギー印加されたガスにより誘電体フィーチャの縁部ファセット高さが誘電体フィーチャの高さの少なくとも10%となり、この方法が更に
(c)チャンバから処理ガスを排気することを含む基板処理方法。 - 第1バイアス電圧の第2バイアス電圧に対する電力レベル比が11未満である請求項1記載の方法。
- 第1バイアス電圧の第2バイアス電圧に対する電力レベル比が11未満であり、エネルギー印加されたガスにより誘電体フィーチャの縁部ファセット高さが誘電体フィーチャの高さの少なくとも30%となる請求項1記載の方法。
- 第1又は第2バイアス電圧の少なくとも1つを電力レベル50〜1000ワットで印加する請求項1記載の方法。
- 第1バイアス周波数が13.6MHzであり、第2バイアス周波数が2MHzである請求項1記載の方法。
- 電源周波数が40〜200MHzであり、第1バイアス周波数が4〜20MHzであり、第2バイアス周波数が1〜4MHzである請求項1記載の方法。
- 処理ガスがCO、O2、N2、H2又はH2Oの少なくとも1つを更に含む請求項1記載の方法。
- 処理ガスにおけるCO2の比率が少なくとも10%である請求項7記載の方法。
- 処理ガスを300mT未満の圧力で維持する請求項1記載の方法。
- 基板処理装置であり、
(a)処理チャンバを備え、処理チャンバが
(1)誘電体フィーチャを覆うレジスト層を備える基板を受ける基板受面を備える基板支持体と、
(2)チャンバ内で処理ガスを分散させるガス分布装置と、
(3)(i)チャンバ付近のアンテナと、(ii)チャンバ内の第1及び第2処理電極を備える、処理ガスにエネルギーを印加するためのガス・エネルギー印加装置と、
(4)ガス排気口を備え、基板処理装置は
(b)処理チャンバ、ガス分布装置、ガス・エネルギー印加装置、ガス排気口に連動的に連結された制御装置を備え、制御装置が
(i)チャンバ内にCO2を含む処理ガスを導入するようガス分布装置を作動させ、
(ii)処理ガスにエネルギーを印加するようガス・エネルギー印加装置を作動させるためのプログラムコードを含み、プログラムコードは、
(1)アンテナに電源電圧を印加するよう作動させるための命令を含み、
(2)チャンバ内の第1及び第2処理電極に少なくとも10MHzの第1周波数を有する第1バイアス電圧と、4MHz未満の第2周波数を有する第2バイアス電圧を印加するようガス・エネルギー印加装置を作動させるための命令を含み、ここで第1バイアス電圧の第2バイアス電圧に対する電力レベル比が1/9以上であり、エネルギー印加されたガスによりレジスト下の誘電体フィーチャの縁部ファセット高さが誘電体フィーチャの高さの10%となり、制御装置が更に
(iii)チャンバから処理ガスを排気するようガス排気口を作動させるためのプログラムコードを含む基板処理装置。 - プログラムコードが、ガス・エネルギー印加装置が第1バイアス電圧の第2バイアス電圧に対する電力レベル比を11未満と設定するよう作動させるための命令を含む請求項10記載の装置。
- プログラムコードが、ガス・エネルギー印加装置が第1及び第2バイアス電圧の少なくとも1つの電力レベルを50〜1000ワットに設定するよう作動させるための命令を含む請求項10記載の装置。
- プログラムコードが、ガス・エネルギー印加装置が第1周波数を13.6MHz、第2周波数を2MHzに設定するよう作動させるための命令を含む請求項10記載の装置。
- プログラムコードが、ガス分布装置がCO、O2、N2、H2及びH2Oの1つ以上を含む処理ガスを供給するよう作動させるための命令を含む請求項10記載の装置。
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US11/555,017 | 2006-10-31 | ||
US11/555,017 US7758763B2 (en) | 2006-10-31 | 2006-10-31 | Plasma for resist removal and facet control of underlying features |
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JP2008124460A JP2008124460A (ja) | 2008-05-29 |
JP4800287B2 true JP4800287B2 (ja) | 2011-10-26 |
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US (1) | US7758763B2 (ja) |
EP (1) | EP1942377A3 (ja) |
JP (1) | JP4800287B2 (ja) |
KR (1) | KR100947678B1 (ja) |
CN (1) | CN101174108A (ja) |
TW (1) | TWI358767B (ja) |
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US7758763B2 (en) | 2006-10-31 | 2010-07-20 | Applied Materials, Inc. | Plasma for resist removal and facet control of underlying features |
US7968473B2 (en) * | 2006-11-03 | 2011-06-28 | Applied Materials, Inc. | Low temperature process for depositing a high extinction coefficient non-peeling optical absorber for a scanning laser surface anneal of implanted dopants |
US7777500B2 (en) * | 2007-10-05 | 2010-08-17 | Lam Research Corporation | Methods for characterizing dielectric properties of parts |
US7637269B1 (en) * | 2009-07-29 | 2009-12-29 | Tokyo Electron Limited | Low damage method for ashing a substrate using CO2/CO-based process |
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2006
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- 2007-09-27 KR KR1020070097353A patent/KR100947678B1/ko not_active IP Right Cessation
- 2007-09-29 CN CNA2007101615484A patent/CN101174108A/zh active Pending
- 2007-10-03 TW TW096137171A patent/TWI358767B/zh not_active IP Right Cessation
- 2007-10-22 EP EP07020636A patent/EP1942377A3/en not_active Withdrawn
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US20080102645A1 (en) | 2008-05-01 |
KR20080039215A (ko) | 2008-05-07 |
CN101174108A (zh) | 2008-05-07 |
EP1942377A2 (en) | 2008-07-09 |
US7758763B2 (en) | 2010-07-20 |
EP1942377A3 (en) | 2009-11-25 |
TW200836257A (en) | 2008-09-01 |
KR100947678B1 (ko) | 2010-03-16 |
TWI358767B (en) | 2012-02-21 |
JP2008124460A (ja) | 2008-05-29 |
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