JP4798849B2 - グラフィックスエンジンマスターモード動作の改良 - Google Patents

グラフィックスエンジンマスターモード動作の改良 Download PDF

Info

Publication number
JP4798849B2
JP4798849B2 JP2000614115A JP2000614115A JP4798849B2 JP 4798849 B2 JP4798849 B2 JP 4798849B2 JP 2000614115 A JP2000614115 A JP 2000614115A JP 2000614115 A JP2000614115 A JP 2000614115A JP 4798849 B2 JP4798849 B2 JP 4798849B2
Authority
JP
Japan
Prior art keywords
data
memory
command
header
data word
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2000614115A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002543489A5 (enExample
JP2002543489A (ja
Inventor
ナラシムハ ノーカラ，
プラーラド ベンカタプラム，
Original Assignee
エヌヴィディア コーポレイション
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by エヌヴィディア コーポレイション filed Critical エヌヴィディア コーポレイション
Publication of JP2002543489A publication Critical patent/JP2002543489A/ja
Publication of JP2002543489A5 publication Critical patent/JP2002543489A5/ja
Application granted granted Critical
Publication of JP4798849B2 publication Critical patent/JP4798849B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
    • G06F9/3879—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Image Generation (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Advance Control (AREA)
  • Multi Processors (AREA)
JP2000614115A 1999-04-26 2000-04-24 グラフィックスエンジンマスターモード動作の改良 Expired - Lifetime JP4798849B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/300,084 US6323867B1 (en) 1999-04-26 1999-04-26 Parsing graphics data structure into command and data queues
US09/300,084 1999-04-26
PCT/US2000/011107 WO2000065436A2 (en) 1999-04-26 2000-04-24 Computer system with graphics engine

Publications (3)

Publication Number Publication Date
JP2002543489A JP2002543489A (ja) 2002-12-17
JP2002543489A5 JP2002543489A5 (enExample) 2007-06-21
JP4798849B2 true JP4798849B2 (ja) 2011-10-19

Family

ID=23157639

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000614115A Expired - Lifetime JP4798849B2 (ja) 1999-04-26 2000-04-24 グラフィックスエンジンマスターモード動作の改良

Country Status (4)

Country Link
US (1) US6323867B1 (enExample)
JP (1) JP4798849B2 (enExample)
TW (1) TW477952B (enExample)
WO (1) WO2000065436A2 (enExample)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1186677C (zh) * 2000-03-30 2005-01-26 精工爱普生株式会社 显示装置
US6847366B2 (en) 2002-03-01 2005-01-25 Hewlett-Packard Development Company, L.P. System and method utilizing multiple processes to render graphical data
US7627585B2 (en) * 2002-12-02 2009-12-01 Sap Ag Data structure mapping and packaging
US6741257B1 (en) * 2003-01-20 2004-05-25 Neomagic Corp. Graphics engine command FIFO for programming multiple registers using a mapping index with register offsets
JP4460867B2 (ja) * 2003-09-26 2010-05-12 東芝ストレージデバイス株式会社 インターフェース装置及びパケット転送方法
US20050143843A1 (en) * 2003-11-25 2005-06-30 Zohar Bogin Command pacing
TWI237771B (en) 2004-03-22 2005-08-11 Via Tech Inc Media player control system and control method used therein
CN100454417C (zh) * 2004-04-16 2009-01-21 威盛电子股份有限公司 媒体播放控制系统及方法
US7916146B1 (en) * 2005-12-02 2011-03-29 Nvidia Corporation Halt context switching method and system
US8427493B2 (en) * 2009-10-13 2013-04-23 Nvidia Corporation Draw commands with built-in begin/end
JP5857735B2 (ja) * 2011-12-27 2016-02-10 株式会社リコー 画像処理方法、画像処理装置、及び制御プログラム
KR101932920B1 (ko) * 2012-09-14 2019-03-18 삼성전자 주식회사 비휘발성 메모리 카드를 제어하는 호스트, 이를 포함하는 시스템 및 이의 동작 방법
KR101988260B1 (ko) * 2012-09-14 2019-06-12 삼성전자주식회사 임베디드 멀티미디어 카드, 및 이의 동작 방법
KR101919903B1 (ko) * 2012-09-14 2018-11-19 삼성전자 주식회사 임베디드 멀티미디어 카드, 이를 제어하는 호스트, 및 이들의 동작 방법
US10235102B2 (en) * 2015-11-01 2019-03-19 Sandisk Technologies Llc Methods, systems and computer readable media for submission queue pointer management
US10372378B1 (en) * 2018-02-15 2019-08-06 Western Digital Technologies, Inc. Replacement data buffer pointers

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02278475A (ja) * 1989-04-20 1990-11-14 Hitachi Ltd 図形処理装置およびその使用方法ならびにマイクロプロセッサ
JPH03142775A (ja) * 1989-10-23 1991-06-18 Internatl Business Mach Corp <Ibm> スタツク制御装置及びスタツク制御方法
JPH0877366A (ja) * 1994-09-02 1996-03-22 Hitachi Ltd 画像処理プロセッサ及びそれを用いたデータ処理システム
JPH09251288A (ja) * 1995-12-19 1997-09-22 Cirrus Logic Inc コンピュータシステム、グラフィックスプロセッサ、インストラクションプリフェッチユニットおよびオペコードインストラクションをプリフェッチする方法
JPH09305789A (ja) * 1996-05-21 1997-11-28 Hitachi Ltd 演算方法およびグラフィックス表示装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8915137D0 (en) * 1989-06-30 1989-08-23 Inmos Ltd Message routing
US5321806A (en) * 1991-08-21 1994-06-14 Digital Equipment Corporation Method and apparatus for transmitting graphics command in a computer graphics system
US5539914A (en) * 1993-06-14 1996-07-23 International Business Machines Corporation Method and system for preprocessing data block headers during access of data in a data storage system
US5931920A (en) 1997-08-05 1999-08-03 Adaptec, Inc. Command interpreter system in an I/O controller
US6075546A (en) * 1997-11-10 2000-06-13 Silicon Grahphics, Inc. Packetized command interface to graphics processor
US6088701A (en) * 1997-11-14 2000-07-11 3Dfx Interactive, Incorporated Command data transport to a graphics processing device from a CPU performing write reordering operations
EP0935189B1 (en) 1998-02-04 2005-09-07 Texas Instruments Incorporated Reconfigurable co-processor with multiple multiply-accumulate units

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02278475A (ja) * 1989-04-20 1990-11-14 Hitachi Ltd 図形処理装置およびその使用方法ならびにマイクロプロセッサ
JPH03142775A (ja) * 1989-10-23 1991-06-18 Internatl Business Mach Corp <Ibm> スタツク制御装置及びスタツク制御方法
JPH0877366A (ja) * 1994-09-02 1996-03-22 Hitachi Ltd 画像処理プロセッサ及びそれを用いたデータ処理システム
US6091863A (en) * 1994-09-02 2000-07-18 Hitachi, Ltd. Image processor and data processing system using the same processor
JPH09251288A (ja) * 1995-12-19 1997-09-22 Cirrus Logic Inc コンピュータシステム、グラフィックスプロセッサ、インストラクションプリフェッチユニットおよびオペコードインストラクションをプリフェッチする方法
EP0780761B1 (en) * 1995-12-19 2001-08-08 Cirrus Logic, Inc. Method and apparatus for instruction prefetching in a graphics processor
JPH09305789A (ja) * 1996-05-21 1997-11-28 Hitachi Ltd 演算方法およびグラフィックス表示装置

Also Published As

Publication number Publication date
WO2000065436A3 (en) 2001-11-15
TW477952B (en) 2002-03-01
WO2000065436A2 (en) 2000-11-02
JP2002543489A (ja) 2002-12-17
US6323867B1 (en) 2001-11-27

Similar Documents

Publication Publication Date Title
JP4798849B2 (ja) グラフィックスエンジンマスターモード動作の改良
JP3431149B2 (ja) 仮想ｆｉｆｏによる周辺装置インタフェースのシステム並びに方法
JP2575596B2 (ja) バス・ブリッジを介してデータを通信する方法およびデータ処理システム
JP3271125B2 (ja) データを転送する方法と装置及びデータ転送をインタリーブする装置
KR19980025110A (ko) 데이타 프로세서 및 그래픽 프로세서
US5948082A (en) Computer system having a data buffering system which includes a main ring buffer comprised of a plurality of sub-ring buffers connected in a ring
US5682551A (en) System for checking the acceptance of I/O request to an interface using software visible instruction which provides a status signal and performs operations in response thereto
JPH06266649A (ja) 複数のデータチャネルを介してデータを転送する方法及びその回路アーキテクチャ
US7610451B2 (en) Data transfer mechanism using unidirectional pull bus and push bus
US6108722A (en) Direct memory access apparatus for transferring a block of data having discontinous addresses using an address calculating circuit
US7016984B2 (en) System controller using plural CPU&#39;s
JPH04230557A (ja) 直接メモリアクセス・コントローラ
JPH06215117A (ja) ビデオ・データ・フレーム伝送方法および装置
JP2001142842A (ja) Ｄｍａハンドシェークプロトコル
JPH0827773B2 (ja) データ経路を使用可能にする方法、装置およびデータ処理システム
JPH06103213A (ja) 入出力装置
US20230267079A1 (en) Processing apparatus, method and system for executing data processing on a plurality of channels
JP2004503859A (ja) メモリコントローラハブ
US20140085320A1 (en) Efficient processing of access requests for a shared resource
US8922571B2 (en) Display pipe request aggregation
US6141023A (en) Efficient display flip
US6957280B2 (en) Streamlining ATA device initialization
JPH1196072A (ja) メモリアクセス制御回路
US7774513B2 (en) DMA circuit and computer system
US9117299B2 (en) Inverse request aggregation

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070423

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070423

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20080313

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20080313

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100615

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100915

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20110705

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20110802

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140812

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Ref document number: 4798849

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

EXPY Cancellation because of completion of term