JP4798336B2 - Method for manufacturing circuit board device - Google Patents

Description

  The present invention relates to a method for manufacturing a circuit board device, and more particularly, to an image display device to which a multi-chip manufacturing method for manufacturing individual circuit boards by separating a plurality of circuit board regions formed on an original board is applied. In particular, the present invention relates to a method for manufacturing a circuit board device that is suitable for application to image reading devices, integrated circuit devices, and the like.

  2. Description of the Related Art In recent years, an image display device having a liquid crystal display panel, an organic electroluminescent panel (organic EL panel), or the like, or an image reading device having a sensor panel in which an image pickup element (CCD) or a light receiving element (photosensor) is two-dimensionally arranged. The spread of electronic devices equipped with devices is remarkable. For example, cellular phones, digital cameras, personal digital assistants (PDAs), notebook personal computers, and the like are equipped with various image display devices and image reading devices as described above.

  In such an image display device or image reading device, generally, a pixel array or a sensor array in which display pixels and light receiving elements are two-dimensionally arranged is formed on one side of an insulating substrate such as a glass substrate, and the array is driven. For example, the driver circuit for performing the configuration has a configuration in which the driver circuit is directly connected to the insulating substrate in the form of a driver chip, or a configuration in which the driver circuit is connected via a flexible printed circuit board (FPC) or a bonding wire.

  Here, in the image display device and the image reading device mounted on the portable device as described above, since it has a relatively small panel size, from the viewpoint of productivity and the like, as its manufacturing process, For example, as shown in Patent Document 1, after setting a plurality of circuit board regions (panel regions) on one large original substrate and forming the array, its peripheral circuit, wiring, etc. for each circuit board region A multi-cavity manufacturing technique is applied in which individual circuit boards (panel boards) are manufactured by cutting each circuit board region.

FIG. 9 is a schematic plan view showing an example of a multi-cavity manufacturing technique in a liquid crystal display device, and FIG. 10 is a schematic plan view showing another example of a multi-cavity manufacturing technique in a liquid crystal display device.
As a method for manufacturing such a large number of liquid crystal display devices, as shown in FIG. 9A, a plurality of circuit board regions 10P are set on the original substrate 200A, and each circuit board region 10P After forming a display pixel array 11P in which liquid crystal is sealed and a plurality of display pixels in which switching elements such as thin film transistors are formed are two-dimensionally arranged, scribe lines SLa to SLc provided between the circuit board regions 10P are formed. A technique for cutting and manufacturing individual panel substrates 10Q as shown in FIG. 9B is described.

  In such a manufacturing method, in order to prevent element destruction due to static electricity generated in the manufacturing process in the state of the original substrate 200A, for example, as shown in FIG. The conductive pattern (shunt) 22P provided in the scribe area SEP provided between SLb and SLc is extended to, for example, the external terminal 13P provided around the display pixel array 11P in each circuit board region 10P or the terminal 13P. A method of connecting and short-circuiting the existing wiring layer 12P is applied.

  9A shows a configuration in which individual conductive patterns 22P are provided in the scribe area SEP for each circuit board region 10P, for example, as shown in FIGS. 10A and 10B. In addition, the conductive substrate 22B has a configuration in which the conductive pattern 22Q extends and is arranged in a scribe area SEQ set in a grid pattern, or the conductive pattern 22Q is connected to a predetermined potential (for example, ground potential). Thus, there is also known one having a configuration in which static electricity generated in each circuit board region 10P is discharged. The conductive patterns 22P and 22Q for preventing electrostatic breakdown or electrostatic discharge provided in the scribe areas SEP and SEQ in the scribe process for dividing the above-described original substrates 200A and 200B into individual panel substrates 10Q are as follows. As shown in FIGS. 9B and 10B, each panel substrate 10Q is separated and removed.

  In the above-described prior art, only the method of manufacturing the liquid crystal display device has been described. However, the same applies to other image display devices including an organic EL panel or the like, and image reading devices including a sensor array. The same manufacturing method is applied to an integrated circuit device using a semiconductor substrate.

JP 2001-215891 A (page 3 to page 5, FIGS. 8 to 10)

FIG. 11 is a schematic view showing a configuration of an end portion of a panel substrate manufactured by a multi-cavity manufacturing technique in the prior art, and FIG. 12 is a panel substrate manufactured by a multi-cavity manufacturing technique in the prior art. It is a conceptual diagram for demonstrating the problem of.
As described above, in the multi-cavity manufacturing technology in the prior art, a conductive pattern for preventing electrostatic breakdown is provided in a scribe area provided between circuit board areas, and is formed in each circuit board area via a wiring layer. By electrically connecting the formed arrays, element breakdown (breakdown voltage breakdown) due to static electricity generated in the region can be prevented. This conductive pattern is separated from each panel substrate by forming the array in each circuit board region and then cutting it with a scribe line.

  However, in the multi-cavity manufacturing method as described above, by separating the panel substrates, as shown in FIGS. 11A and 11B, the conductive pattern of the scribe area is formed on the substrate end surface 10f. Since the cut sections of the connected external terminals 13P and wiring layer 12P are exposed, as shown in FIGS. 12A and 12B, the pollutant POL (specifically, generated on the substrate end face 10f in the factory). Specifically, a driver circuit (not shown) connected to the external terminal 13P by adhering sodium contained in a worker's sweat or the like, or a trace amount of heavy metal atoms contained in a chemical used in various processes. ) To drive the liquid crystal display array (or sensor array) by applying a predetermined signal voltage, if a potential difference occurs between each external terminal (each wiring layer), the pollutant POL As a result, the current path IR is formed, the signal voltage of each wiring layer is abnormal, the corrosion COR of the external terminals 13P and the wiring layer 12P proceeds, and the connection failure with the driver circuit increases. It was.

  This causes a malfunction of a liquid crystal display panel and a sensor panel (hereinafter collectively referred to as “circuit board device”), leading to a problem that the reliability and product life of the image display device and the image reading device are reduced. It was. In addition, the probability that such corrosion of the terminal and the wiring layer occurs is further increased as the potential difference between the wiring layers of the signal voltage transmitted to the driver circuit is larger, and as the humidity in the operating atmosphere is higher. Tends to become higher as the distance between the wiring layers 12P becomes shorter.

  Therefore, in view of the above problems, the present invention provides a circuit board device manufactured by applying a multi-cavity manufacturing technique, and an abnormal signal voltage or corrosion of a wiring layer due to contaminants attached to the end face of each circuit board. It is an object of the present invention to provide a method for manufacturing a circuit board device capable of suppressing the above and improving operational reliability and product life.

According to the first aspect of the present invention, a plurality of circuit units each including a functional element and a plurality of signals for inputting / outputting various signals for driving the circuit units are provided in each of a plurality of circuit board regions set on one side of the original substrate. And a terminal portion extending from the circuit portion, and each of the terminal portions is individually connected to a common conductive pattern provided outside the circuit board region. A step of forming a plurality of wiring layers;
Forming an insulating film covering a region including the wiring layer and the plurality of terminal portions;
The circuit board, the plurality of terminal portions, and the plurality of wiring layers are formed on the one surface side of the panel substrate obtained by cutting the original substrate for each circuit board region, and the wiring layer is formed. Manufacturing a separate circuit board having a side end face from which a cut surface of
A corner of the one side of the side end surface of the circuit board is chamfered at a predetermined inclination angle, and a cut surface of the panel substrate, a part of the insulating film and the wiring layer is cut and viewed in plan view. Te, there cutting surface of the wiring layer is inward from said lateral end surface, the step of the end portion of the lateral end surface of the cutting surface of the insulating film to form an inclined surface on the inside than the cutting surface of the wiring layer When,
Forming a protective insulating film on the inclined surface, and covering the entire inclined surface with the protective insulating film;
A frame member having a recess is prepared, and the circuit board is provided in such a manner that the side end surface and the other surface side of the circuit board are in contact with the inner surface side of the recess, and the circuit board is accommodated in the frame member. And a process of
Have
The step of forming the inclined surface includes a step of connecting an external device for inputting / outputting various signals to / from the circuit unit to the terminal unit through an opening formed in the insulating film,
The step of forming the protective insulating film includes a step of forming the protective insulating film also on the insulating film and the external device and simultaneously covering the entire inclined surface, the insulating film, and the external device. It is characterized by.

In the method of manufacturing a circuit board device, the external device may have a driver chip shape, and may be directly connected to the plurality of terminal portions and mounted on one surface side of the circuit board. Good.
Further, the circuit unit may be a pixel array for image display in which display pixels are two-dimensionally arranged, or may be a sensor array for image reading in which light receiving elements are two-dimensionally arranged.

  Here, the light receiving element includes a drain electrode and a source electrode made of a transparent electrode material formed across a channel region made of a semiconductor layer, and a transparent insulating film above the channel region. A first gate electrode made of a transparent electrode material, and a second gate electrode made of a light-shielding electrode material formed through a transparent insulating film below the channel region; And a double-gate thin film transistor structure having the above structure can be applied.

  In this case, the light receiving element initializes the light receiving element by applying a reset pulse to the first gate electrode, applies a precharge pulse to the drain electrode, and then applies a read pulse to the second gate electrode. By applying the voltage signal corresponding to the amount of charge accumulated according to the amount of light incident on the channel region from the drain electrode during the charge accumulation period from the end of initialization to the application of the readout pulse. A drive control method of taking out and reading the image of the subject can be applied.

  Further, when the light receiving element is applied, the wiring layer includes a first gate line connected to the first gate electrode and a second gate line connected to the second gate electrode. , And at least one of drain lines connected to the drain electrode, and the external device connects the first gate electrode of the light receiving element to the first gate electrode via the first gate line. A first gate driver for applying a reset pulse, a second gate driver for applying the read pulse to the second gate electrode of the light receiving element via the second gate line, and the drain line. And applying a precharge pulse to the drain electrode of the light receiving element, and applying a voltage signal corresponding to the amount of charge accumulated in the channel region. Of the drain driver begins to look, it may be at least one.

The method for manufacturing a circuit board device according to the present invention cuts an original board having a relatively large size in which a plurality of circuit board areas are set on one surface side for each circuit board area, and a circuit board having a relatively small size ( In the manufacturing process of circuit board devices that apply multi-cavity manufacturing technology that cuts out individual panel boards), the corners on one side of the side end face where the cut surface of the wiring layer of each circuit board is exposed are chamfered. Te, in plan view, the cutting surface of the wiring layer of the panel on the substrate is inside from the side end face, an end portion of the lateral end surface of the cutting surface of the insulating film is inside than the cutting surface of the wiring layer inclination A surface (processed surface) is formed, and the entire inclined surface and an external device mounted on one surface side of the circuit board are simultaneously covered with a protective insulating film, and the side end surface and the other surface side of the circuit board are covered with the frame member. Provided in contact with the inner surface of the recess, By accommodating the circuit board in the frame member, contaminants adhering to the end face of the board (particularly the wiring layer exposed on the end face of the board) after the individual panel board is cut out from the original board are removed to form an inclined surface. Since it is possible to completely prevent the contaminants from adhering to the exposed wiring layer, a current path is formed between the wiring layers when the circuit unit (functional circuit unit; pixel array, sensor array, etc.) is driven. Prevents the occurrence of signal voltage fluctuations and short-circuits between wires, and the protective surface is covered on the flat surface of the substrate by covering the inclined surface with the protective surface. Compared to the case where only the protective layer is provided, the length of the ingress route for moisture etc. from the outside via the interface between the protective insulating film and the circuit board is suppressed, and the moisture layer is prevented from entering from the outside, and the wiring layer And terminal (external electrode Since the corrosion of head) can be prevented, high reliability of operation, it is possible to realize a circuit board with improved product life apparatus (image display apparatus or an image reading apparatus).

Hereinafter, a method for manufacturing a circuit board device according to the present invention will be described in detail with reference to embodiments.
Here, the target circuit board device is not particularly limited, and may be a liquid crystal display panel as shown in the prior art or a sensor panel in which light receiving elements are two-dimensionally arranged. . A specific application example will be described later in detail.

<First Embodiment>
FIG. 1 is a plan view showing the concept of a multi-cavity manufacturing technique to which a method for manufacturing a circuit board device according to the present invention is applied. 2 and 3 are process block diagrams showing a first embodiment of a method for manufacturing a circuit board device according to the present invention.

  First, as shown in FIGS. 1A and 1B, a method for manufacturing a circuit board device according to the present embodiment includes a plurality of circuit boards on one side of an original substrate 100 made of an insulating substrate such as a glass substrate. An area 10X is set, and each circuit board area 10X is arranged in a functional circuit unit (circuit unit) 11 such as a pixel array or a sensor array or in the peripheral part of the functional circuit unit 11 to drive the functional circuit unit 11. A plurality of external terminal pads (terminal portions) 13 for inputting and outputting various signals are individually extended from the functional circuit portion 11, and a plurality of wiring layers 12 connected to the plurality of external terminal pads 13 are collectively collected. It is formed. The external terminal pad 13 and the plurality of wiring layers 12 may be the same layer or may be different layers.

  In addition, an insulating film (not shown) (FIG. 2B) is formed on one surface side of the original substrate 100 including at least the functional circuit portion 11, the wiring layer 12, and the external terminal pads 13 formed in each circuit board region 10X. An insulating film 14) shown in (c) is laminated so as to cover them, and is configured to prevent external electrical and physicochemical damage and erosion.

  Here, the circuit board region 10X of the original substrate 100 is defined by the scribe line SL. In addition, conductive patterns 21 for electrostatic discharge are arranged in a grid pattern in scribe areas SE formed between opposing scribe lines SL between adjacent circuit board regions 10X, as shown in FIG. As described above, the wiring layer 12 formed in each circuit board region 10X is connected in common to the conductive pattern 21 disposed in the scribe area SE from the functional circuit unit 11 via each external terminal pad 13. . The conductive pattern 21 is connected to a specific potential such as a ground potential, for example, and discharges static electricity generated on the original substrate 100 (circuit board region 10X) through the conductive pattern 21 during the manufacturing process.

  Next, by cutting the original substrate 100 along the scribe line SL, as shown in FIG. 1B, the scribe area SE is separated from the circuit board region 10X, and the wiring layer 12 is separated from the conductive pattern 21. Individual panel boards (circuit boards) 10A having the functional circuit portions 11 are obtained by being separated and electrically independent.

  Specifically, the panel substrate 10A cut out individually in this way covers the functional circuit section 11, the wiring layer 12, and the external terminal pad 13, as shown in FIGS. 2 (a) and 2 (b). Since the insulating film 14 is formed as described above, the cross section of the wiring layer 12 is exposed only to the side end face 10e of the panel substrate 10A by the scribing process of the original substrate 100 described above.

  Note that the functional circuit section 11, the wiring layer 12, and the external terminal pads 13 formed on the panel substrate 10A are formed over the entire area of the panel substrate 10A made of an insulating substrate, as shown in FIG. 2B. It may be laminated on the thin insulating film 15 serving as a base layer, or may be formed directly on the panel substrate 10A as shown in FIG. 2 (c), for example. .

  Next, as shown in FIG. 3A, in each panel substrate 10 </ b> A, the uppermost insulating film 14 is partially etched to expose the upper surfaces of the external terminal pads 13 arranged around the functional circuit portion 11. As shown in FIG. 3B, a driver circuit (external device, driver) is formed directly through the external terminal pad 13 or through a flexible printed circuit board (FPC) or a bonding wire. Chip) DCP is connected. FIG. 3B shows a configuration in which the bump electrodes BP of the driver chip DCP are directly connected via the external terminal pads 13.

  Next, as shown in FIG. 3C, one side of the side end face 10e where at least the cross section of the wiring layer 12 is exposed, among the board end portions of the panel board 10A (the functional circuit section 11 and the wiring of the panel board 10A). The inclined surface 16 having a predetermined inclination angle is formed by chamfering the corner of the surface on which the layer 12 is formed; Here, the inclination angle of the inclined surface 16 is set so that at least the cross section of the wiring layer 12 exposed to the side end face 10e is cut.

  Next, as shown in FIG. 3 (d), the driver chip DCP is mounted (directly connected), and the substrate end surface and back surface (lower side of the drawing) of the panel substrate 10A in which the corner portion of the substrate end portion is chamfered By mounting and fixing so as to contact the inner surface side of the frame member FR, a front frame member (not shown) is fitted to the rear frame member FR on the upper surface of the panel substrate 10A so that the inclined surface 16 is not exposed. A circuit board device such as a sensor panel is completed.

  Thereby, in the scribing process of the original substrate 100 or after the scribing process, contaminants generated in the factory are formed on the substrate end portion of the panel substrate 10A (particularly, the side end face 10e where the cross section of the wiring layer 12 is exposed). Even if it adheres, the corners on one surface side of the substrate end including at least the side end face 10e where the cross section of the wiring layer 12 is exposed are chamfered, so that the contaminants attached to the cross section of the wiring layer 12 Can be removed.

  In addition, contaminants attached to other than the substrate end of the panel substrate 10A (for example, one surface side of the panel substrate 10A) are covered with the insulating layer 14 after the functional circuit portion 11, the wiring layer 12, and the external terminal pad 13 are formed. Therefore, direct influence on the wiring layer 12 and the external terminal pad 13 by the contaminant can be prevented.

  Further, after cutting the original substrate 100 coated with the insulating layer 14 to cut out the individual panel substrates 10A, only the insulating film 14 on the external terminal pads 13 is removed, and the external terminal pads 13 are exposed. However, for example, the driver chip (driver circuit) DCP is directly connected, and the driver chip DCP is mounted so as to cover the connection portion with the external terminal pad 13. The adhesion of the pollutant to the connection portion can be suppressed as much as possible, and further, dust such as the insulating layer 14 cut when forming the inclined surface 16 adheres to the surface of the external terminal pad 13 and is connected. It is possible to prevent the occurrence of defects.

  Therefore, according to the method for manufacturing the circuit board device according to the present embodiment, in the manufacturing process of the circuit board device to which a multi-cavity manufacturing technology is applied to cut a relatively large original substrate and cut out individual panel substrates, By chamfering the corners of the edge of the individual panel substrate, contaminants attached to the substrate end surface (particularly the wiring layer exposed on the substrate end surface) are removed, and the functional circuit portion (pixel array, sensor array, etc.) ), It is possible to prevent current paths from being formed between the wiring layers on the substrate end face, and to prevent fluctuations in signal voltage and corrosion of the wiring layer and external electrode pads, resulting in high operational reliability. A circuit board device (display panel or sensor panel) with an improved product life can be realized.

<Second Embodiment>
Next, a second embodiment of the method for manufacturing a circuit board device according to the present invention will be described with reference to the drawings.
FIG. 4 is a process cross-sectional view illustrating a second embodiment of a method for manufacturing a circuit board device according to the present invention. Here, the description of the steps equivalent to those in the first embodiment will be simplified.

  The circuit board device manufacturing method according to the present embodiment is roughly the same as that shown in FIG. 4A in the first embodiment described above, except that the panel board 10A individually cut out from the original board 100 is connected to the external terminal. After a driver chip (driver circuit) DCP is connected through the pad 13 and a corner portion on one surface side of the substrate is chamfered to form the inclined surface 16, at least the substrate as shown in FIG. A protective insulating film 17 is formed on one surface side of the panel substrate 10A including the inclined surface 16 at the end.

  Next, as shown in FIG. 4C, the substrate end surface and the back surface (lower side in the drawing) of the panel substrate 10A having the protective insulating film 17 formed on one surface thereof are in contact with the inner surface side of the frame member FR. By mounting and fixing, circuit board devices such as a liquid crystal display panel and a sensor panel are completed.

  As a result, the inclined cross section of the wiring layer 12 exposed on the inclined surface 16 at the edge of the substrate is covered with the protective insulating film 17, so that the inclined surface 16 (particularly, the contaminants generated in the subsequent processes). Adhesion to the wiring layer 12) exposed on the inclined surface 16 can be completely prevented. Further, since the protective insulating film 17 is formed after the driver chip DCP is mounted on the panel substrate 10A, it is possible to completely prevent adhesion of contaminants to the connection portion between the transistor chip DCP and the external terminal pad 13. Can do.

  Therefore, according to the method for manufacturing the circuit board device according to the present embodiment, in the manufacturing process of the circuit board device to which the multi-cavity manufacturing technology is applied, the corners of the end portions of the individual panel substrates are chamfered. The substrate was chamfered by removing contaminants adhering to the end face of the substrate (particularly the wiring layer exposed on the end face of the substrate) and further covering at least the surface from which the contaminant was removed (inclined surface) with a protective insulating film. Since it is possible to completely prevent the contaminants from adhering again to the wiring layer exposed on the inclined surface, the fluctuation of the signal voltage caused by the contaminants and the corrosion of the wiring layer and the external electrode pad are prevented, It is possible to realize a circuit board device (display panel or sensor panel) with higher operational reliability and improved product life.

<Application example>
Next, a circuit board device to which the manufacturing methods according to the first and second embodiments described above can be applied will be described.
Here, an image reading apparatus is shown as an example to which the above-described method for manufacturing a circuit board device can be applied, and will be specifically described with reference to the drawings.

  The method for manufacturing a circuit board device as described above can be applied favorably to a display panel such as a liquid crystal display panel or an organic EL panel, a sensor panel for image reading, and the like. It has been found that the fluctuation of the signal voltage due to adhering contaminants and the degree of corrosion of the wiring layer depend on the magnitude of the difference in signal voltage (potential difference) applied between the wiring layers (or external terminal pads). Yes. Therefore, for example, a sensor array having a two-dimensional array of photosensors having a double-gate type thin film transistor structure (hereinafter referred to as “double-gate type photosensors”) having a relatively large change in signal voltage during driving is provided. By applying to an image reading apparatus, a remarkable effect can be obtained. This will be specifically described below.

FIG. 5 is a main part configuration diagram showing an example of an image reading apparatus (sensor array and its peripheral circuit) to which the circuit board device manufacturing method according to the present invention can be applied.
As shown in FIG. 5, the image reading apparatus according to this application example is roughly divided into a large number of photosensors (double-gate photosensors; light receiving elements) PS, for example, n rows × m columns (n and m are arbitrary). Sensor array 11S arranged in a matrix of a natural number), a top gate line Lt extending by connecting the top gate terminals TG of each photosensor PS in the row direction, and a bottom gate terminal BG of each photosensor PS in the row direction. A bottom gate line Lb extending to connect to the drain terminal, a drain line (data line) Ld extending to connect the drain terminal D of each photosensor PS in the column direction, and a source terminal S to a predetermined low potential voltage (for example, A source line (common line) Ls commonly connected to the ground potential (Vss) and a top line connected to each top gate line Lt via the external terminal pad 13t. A gate driver DCt, a bottom gate driver DCb connected to each bottom gate line Lb via an external terminal pad 13b, and a drain driver (read driver) DCd connected to each drain line LD via an external terminal pad 13d. And is configured.

  Here, in FIG. 5, the sensor array 11S, the top gate line Lt, the bottom gate line Lb, the drain line Ld, and the external terminal pads 13t, 13b, and 13d are formed on one surface side of the panel substrate 10A. Each of the gate driver DCt, the bottom gate driver DCb, and the drain driver DCd has a form of a driver chip (integrated circuit chip), for example, on one side of the panel substrate 10A on which the sensor array 11S is formed. It has a configuration in which it is directly connected (mounted) to the peripheral region of the array 11S.

  In FIG. 5, the top gate control signal is a signal φT1, φT2 that is selectively output to each top gate line Lt as either a reset voltage (reset pulse) or a carrier storage voltage described later in the top gate driver DCt. ,..., .Phi.Ti,..., .Phi.Tn, and the bottom gate control signal is selectively output to each bottom gate line Lb as either a read voltage or a non-read voltage described later in the bottom gate driver DCb. ...,..., .Phi.Bn are generated by the drain driver DCd. The drain control signal applies a precharge voltage Vpg, which will be described later, to each photosensor PS and each photosensor PS. Drain current corresponding to carriers stored in PS It is a control signal for controlling the reading of VD (data voltage Vrd). These control signals are generated and supplied by, for example, a system controller (not shown).

(Photo sensor PS)
FIG. 6 is a schematic cross-sectional view showing the element structure of a photosensor applicable to the image reading apparatus according to this application example.
A photosensor PS applicable to the sensor array 11S described above is roughly a semiconductor layer such as amorphous silicon in which electron-hole pairs are generated by the incidence of excitation light (here, visible light) as shown in FIG. (Channel region) 31 and both ends of the semiconductor layer 31 are formed through impurity layers (ohmic contact layers) 37 and 38 made of n ⁺ silicon, respectively, and are selected from chromium, chromium alloy, aluminum, aluminum alloy, etc. The drain electrode 32 (drain terminal D) and the source electrode 33 (source terminal S), which are made of a conductive material and opaque to visible light, and a block insulating film (stopper film) above the semiconductor layer 31 (upward in the drawing) 34 and the upper gate insulating film 35, and is formed of a transparent electrode layer such as a tin oxide film or an ITO film (indium-tin oxide film). A transparent top gate electrode TGx (first gate electrode; top gate terminal TG) and a lower gate insulating film 106 below the semiconductor layer 31 (downward in the drawing), and is formed of chromium, chromium alloy, aluminum And a bottom gate electrode BGx (second gate electrode; bottom gate terminal BG) made of a conductive material selected from aluminum alloy or the like and opaque to visible light.

  That is, the photosensor PS applied to the sensor array 11S according to the present embodiment has a so-called double gate type thin film transistor structure, and as shown in FIG. 6, a semiconductor manufacturing technique is applied to the panel substrate 10A. A thin film is formed. Further, a protective insulating film (corresponding to the insulating film 14 shown in FIG. 2) 39 is formed on the entire surface of the panel substrate 10A including the photosensor PS so as to cover the electrical, physicochemical, and the photosensor PS. It is configured to prevent damage and erosion.

  Further, the top gate electrode TGx, the bottom gate electrode BGx, the drain electrode Ld, and the source electrode Ls that constitute the photosensor PS are, for example, the top gate line Lt, the bottom gate line Lb, the drain line Ld, and the drain line Ld shown in FIG. It is formed integrally with the source line Ls and is electrically connected.

  In the photosensor PS shown in FIG. 6, the top gate insulating film 35, the block insulating film 34, the insulating film constituting the bottom gate insulating film 36, and the protective insulating film 39 provided on the top gate electrode TGx are as follows. Both are made of a material having a high transmittance with respect to visible light that excites the semiconductor layer 31, for example, silicon nitride, silicon oxide, etc., so that a light source (not shown) provided below the drawing is used. Is transmitted to the upper side of the drawing and is reflected by the subject (finger) placed on the detection surface DTC provided on the upper surface of the protective insulating film 39, so that the photo sensor PS (specifically, the semiconductor layer) is seen from the upper side of the drawing. 31) has a structure for detecting only light incident thereon.

(Top gate driver DCt / Bottom gate driver DCb)
The top gate driver DCt and the bottom gate driver DCb have substantially the same configuration. For example, the top gate driver DCt (or the bottom gate driver DCb) is generally a top gate supplied from a system controller or the like not shown. A shift register circuit that outputs a shift signal corresponding to each top gate line Lt (or bottom gate line Lb) while sequentially shifting the start signal at a predetermined timing based on the control signal (or bottom gate control signal). Then, the shift signal sequentially output from the shift register circuit is amplified to a predetermined signal level and output to each top gate line Lt (or bottom gate line Lb) as a reset pulse φTi (or read pulse φBi). And an output buffer to be configured The

(Drain driver DCd)
The drain driver DCd is a shift that outputs a shift signal corresponding to each source line Ls while sequentially shifting the start signal at a predetermined timing based on a drain control signal supplied from a system controller (not shown) schematically. A register circuit, a precharge circuit for simultaneously applying a predetermined precharge pulse (precharge voltage Vpg) to each drain line Ld during a precharge period based on a precharge signal φpg supplied as a drain control signal; During the reading period, the drain line voltage VD (data voltage Vrd) corresponding to the carriers accumulated in each photosensor PS is read in parallel via each drain line Ld, amplified to a predetermined signal level, and the shift register Timing based on shift signals sequentially output from the circuit Based on the grayed when it series taken out are configured to have a read circuit for outputting a read data signal (serial signal) Vdata.

(Drive control method)
Next, a drive control method for the above-described image reading apparatus (sensor array) will be briefly described with reference to the drawings.
FIG. 7 is a timing chart showing an example of a drive control method in the image reading apparatus according to this application example. FIG. 8 is an operation conceptual diagram showing a fingerprint image reading operation when the image reading apparatus according to this application example is applied to a fingerprint reading sensor. Here, in FIG. 8, for the convenience of illustration, a part of hatching that represents a cross-sectional portion of the sensor array 11S is omitted.

In the drive control method of the sensor array 11S described above, for example, as shown in FIG. 7, a reset period Trst, a charge accumulation period Ta, a precharge period Tprch, and a readout period Tread are set in a predetermined processing operation period (processing cycle). It is realized by doing.
As shown in FIG. 7, first, in the reset period Trst, the top of the photosensor PS in the i-th row (i is an arbitrary integer satisfying 1 ≦ i ≦ n) by the top gate driver DCt via the top gate line Lt. A reset pulse (for example, a high level of top gate voltage (= reset pulse voltage) Vtg = + 15 V) φTi is applied to the gate terminal TG to release carriers (here, holes) accumulated in the semiconductor layer 31. Perform a reset operation (initialization operation).

  Next, in the charge accumulation period Ta, the top gate driver DCt applies a low level (for example, top gate voltage Vtg = −15V) bias voltage φTi to the top gate terminal TG, thereby terminating the reset operation. The accumulation operation (carrier accumulation operation) is started.

  Here, in the charge accumulation period Ta, as shown in FIG. 8, the back provided on the back side (lower side of FIG. 8) of the transparent panel substrate 10A on which the photosensor PS shown in FIGS. 5 and 6 is formed. The light BL is irradiated from the light BL to the subject (finger FG) placed in close contact with the detection surface DTC on the upper surface of the sensor array 11S, and the reflected light Ly is a top gate electrode TGx made of a transparent electrode layer. And enters the semiconductor layer 31. Thereby, electron-hole pairs are generated in the incident effective region (carrier generation region) of the semiconductor layer 31 according to the amount of light incident on the semiconductor layer 31 during the charge accumulation period Ta, and the semiconductor layer 31 and the block insulating film 34 are generated. Holes are accumulated in the vicinity of the interface (around the channel region).

  In the precharge period Tprch, a precharge pulse (for example, precharge) is applied to the drain terminal D by the drain driver DCd based on the precharge signal φpg supplied as a drain control signal in parallel with the charge accumulation period Ta. Voltage Vpg = + 5 V) is applied, and a precharge operation for holding the charge in the drain electrode 32 is executed.

  Next, in the read period Tread, after the precharge period Tprch has elapsed, a read pulse (for example, bottom gate voltage (= read pulse voltage)) is applied to the bottom gate terminal BG via the bottom gate line Lb by the bottom gate driver DCb. By applying (Vbg = + 10V high level) φBi, the drain voltage VD (data voltage Vrd; voltage signal) corresponding to the carriers (holes) accumulated in the channel region during the charge accumulation period Ta is applied to the drain line Ld. Thus, a read operation for reading by the drain driver DCd is performed.

  Here, the change tendency of the drain voltage VD (data voltage Vrd) during the application period (readout period) of the read pulse φBi is such that the voltage is steep when there are many carriers accumulated in the charge accumulation period Ta (bright state). On the other hand, when the number of accumulated carriers is small (dark state), it tends to decrease gradually. For example, the data voltage Vrd after a predetermined time has elapsed after the start of the read period Tread is detected. Accordingly, it is possible to detect the amount of light incident on the photosensor PS, that is, lightness data (lightness / darkness information) corresponding to the light / dark pattern of the subject.

  Then, a series of brightness data detection operations for such a specific row (i-th row) is regarded as one cycle, and each row (i = 1, 2,... N) of the sensor array 11S described above is equivalent. An image reading device that reads a two-dimensional image (fingerprint image) of a subject as lightness data from a sensor array 11S to which a photosensor (double-gate photosensor) PS having a double-gate thin film transistor structure is applied by repeating operation processing Can be operated as

  That is, in the above-described image reading device, in the subject image reading operation, the top gate driver DCt, the bottom gate driver DCb, and the drain driver DCd, which are external devices (driver chips) mounted on one side of the panel substrate 10A, Via the external terminal pads 13t, 13b, and 13d, the top gate line Lt, the bottom gate line Lb, and the drain line (data line) Ld, which are wiring layers disposed on one surface side of the panel substrate 10A, are each 30V. A signal voltage having a voltage difference of about 10V and 5V is applied.

  In this case, in the image reading apparatus manufactured by applying the multi-cavity manufacturing technique shown in the prior art, the top gate line, the bottom gate line, and the drain line formed together with the sensor array are in the state of the original substrate. , Each extending from the sensor array via an external terminal pad so as to be connected to a conductive pattern for electrostatic discharge provided in the scribe area. In the state of being cut out, the substrate end face remains in a cut state (cut face), so that the cut cross sections of the top gate line, the bottom gate line, and the drain line are exposed at the substrate end face.

  Here, as described in the above drive control method, the difference in the signal voltage of the top gate pulse φT applied to the top gate line Lt during the reset operation and the non-reset operation is as large as about 30 V, and the read operation The difference between the signal voltages of the bottom gate pulse φB applied to the bottom gate line Lb during the non-reading operation and the non-reading operation is relatively large, about 10 V, and is applied to the drain line Ld during the precharging operation and the non-precharging operation. The difference in signal voltage of the precharge voltage (drain voltage VD) is about 5 V. Therefore, if contaminants generated in the manufacturing process or the like adhere to the end face of the substrate, especially between the top gate lines Lt or the bottom A large current flows through the current path formed through the contaminant between the gate lines Lb. As a result, the malfunction due to the fluctuation of the signal voltage of the top gate pulse φT and the bottom gate pulse φB and the progress of corrosion of the top gate line Lt, the bottom gate line Lb, and the external terminal pads 13t and 13b become prominent. Have. In addition, since the drain voltage VD (data voltage Vrd) fluctuates between the drain lines Ld, an accurate read data signal Vdata cannot be obtained, and the subject image (fingerprint image) can be read appropriately. Has the problem of disappearing.

  In contrast, in the image reading apparatus to which the circuit board device manufacturing method according to the first embodiment described above is applied, at least after cutting out individual panel substrates from the original substrate, the top gate line Lt and the bottom gate By chamfering the corners of the end face of the substrate where the cut surfaces of the line Lb and drain line Ld are exposed, contaminants adhering between the wiring layers can be removed, so that the top gate pulse φT and bottom gate as described above can be removed. Prevents pulse φB, signal voltage fluctuation of drain voltage VD (data voltage Vrd) and corrosion of top gate line Lt, bottom gate line Lb, and external terminal pads 13t, 13b, thereby improving operation reliability and product life An image reading apparatus can be provided.

  Further, when the circuit board device manufacturing method according to the second embodiment is applied, individual panel substrates are cut out from the original substrate, and cut surfaces of the top gate line Lt, the bottom gate line Lb, and the drain line Ld. Since the protective insulating film is formed so as to cover at least the processed surface (inclined surface) after chamfering the corner of the substrate end surface where the substrate is exposed, contaminants are again present in the wiring layer exposed on the inclined surface. Adhesion can be completely prevented, signal voltage fluctuation of top gate pulse φT, bottom gate pulse φB, drain voltage VD (data voltage Vrd), top gate line Lt, bottom gate line Lb, external terminal pad It is possible to provide an image reading apparatus in which the corrosion of 13t and 13b is completely prevented, and the operation reliability and product life are further improved.

  In the application example described above, an image reading device including a sensor array in which a double gate type photosensor is two-dimensionally arranged is shown as a circuit board device to which the manufacturing method according to the present invention can be applied. However, the present invention is not limited to this, and an image display device such as a liquid crystal display panel or an organic EL panel as shown in the prior art, an image reading device comprising another photosensor panel, and further formed on a semiconductor substrate. Even an integrated circuit device can be applied satisfactorily. In short, it is a circuit board device manufactured by applying a multi-chip manufacturing technology, and a conductive pattern for discharging static electricity generated in the manufacturing process is provided outside the circuit board area (scribe area), and individually. If the wiring layer connected to the internal functional circuit (pixel array, sensor array, integrated circuit, etc.) is inevitably exposed on the end surface of the substrate by cutting it into the panel substrate, it should be applied well. Can do.

It is a plane block diagram which shows the concept of the multi-cavity manufacturing technique to which the manufacturing method of the circuit board apparatus which concerns on this invention is applied. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a process configuration diagram (part 1) illustrating a first embodiment of a method for manufacturing a circuit board device according to the present invention; FIG. 3 is a process configuration diagram (No. 2) illustrating the first embodiment of the method for manufacturing the circuit board device according to the present invention. It is process sectional drawing which shows 2nd Embodiment of the manufacturing method of the circuit board apparatus which concerns on this invention. It is a principal part block diagram which shows an example of the image reading apparatus (sensor array and its peripheral circuit) which can apply the manufacturing method of the circuit board apparatus based on this invention. It is a schematic sectional drawing which shows the element structure of the photosensor applicable to the image reading apparatus which concerns on this application example. 12 is a timing chart illustrating an example of a drive control method in the image reading apparatus according to the application example. It is an operation | movement conceptual diagram which shows the reading operation | movement of a fingerprint image at the time of applying the image reading apparatus which concerns on this application example to a fingerprint reading sensor. It is a schematic plan view which shows an example of the manufacturing technique of multi-cavity in a liquid crystal display device. It is a schematic plan view which shows the other example of the manufacturing technique of the multi-cavity in a liquid crystal display device. It is the schematic which shows the structure of the edge part of the panel substrate manufactured by the manufacturing technique of multi-cavity in a prior art. It is a conceptual diagram for demonstrating the problem of the panel board | substrate manufactured by the manufacturing technique of multi-cavity in a prior art.

Explanation of symbols

10X Circuit board region 10A Panel board 10e Board end face 11 Functional circuit part 11S Sensor array 12 Wiring layer 13 External terminal pad 14, 15 Insulating film 16 Inclined surface DCP Driver chip PS Photo sensor Lt Top gate line Lb Bottom gate line Ld Drain line

Claims (4)

In each of a plurality of circuit board regions set on one surface side of the original board, a circuit unit composed of functional elements, a plurality of terminal units for inputting / outputting various signals for driving the circuit unit, and the circuit Forming a plurality of wiring layers extending from the portion and individually connected to the common conductive pattern provided outside the circuit board region via each of the terminal portions. Process,
Forming an insulating film covering a region including the wiring layer and the plurality of terminal portions;
The circuit board, the plurality of terminal portions, and the plurality of wiring layers are formed on the one surface side of the panel substrate obtained by cutting the original substrate for each circuit board region, and the wiring layer is formed. Manufacturing a separate circuit board having a side end face from which a cut surface of
A corner of the one side of the side end surface of the circuit board is chamfered at a predetermined inclination angle, and a cut surface of the panel substrate, a part of the insulating film and the wiring layer is cut and viewed in plan view. Te, there cutting surface of the wiring layer is inward from said lateral end surface, the step of the end portion of the lateral end surface of the cutting surface of the insulating film to form an inclined surface on the inside than the cutting surface of the wiring layer When,
Forming a protective insulating film on the inclined surface, and covering the entire inclined surface with the protective insulating film;
A frame member having a recess is prepared, and the circuit board is provided in such a manner that the side end surface and the other surface side of the circuit board are in contact with the inner surface side of the recess, and the circuit board is accommodated in the frame member. And a process of
Have
The step of forming the inclined surface includes a step of connecting an external device for inputting / outputting various signals to / from the circuit unit to the terminal unit through an opening formed in the insulating film,
The step of forming the protective insulating film includes a step of forming the protective insulating film also on the insulating film and the external device and simultaneously covering the entire inclined surface, the insulating film, and the external device. A method for manufacturing a circuit board device.   2. The method of manufacturing a circuit board device according to claim 1, wherein the external device has a form of a driver chip, and is directly connected to the plurality of terminal portions and mounted on one surface side of the circuit board. .   The method of manufacturing a circuit board device according to claim 1, wherein the circuit unit is a pixel array for image display in which display pixels are two-dimensionally arranged. 3. The method of manufacturing a circuit board device according to claim 1, wherein the circuit unit is a sensor array for image reading in which light receiving elements are two-dimensionally arranged.

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