JP4792713B2 - Lead wire, manufacturing method thereof, and solar cell assembly - Google Patents

Lead wire, manufacturing method thereof, and solar cell assembly Download PDF

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JP4792713B2
JP4792713B2 JP2004176114A JP2004176114A JP4792713B2 JP 4792713 B2 JP4792713 B2 JP 4792713B2 JP 2004176114 A JP2004176114 A JP 2004176114A JP 2004176114 A JP2004176114 A JP 2004176114A JP 4792713 B2 JP4792713 B2 JP 4792713B2
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lead wire
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JP2005353549A (en
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裕寿 遠藤
正義 青山
孝 根本
敦志 大竹
修慈 川崎
宙 坂東
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Hitachi Cable Ltd
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Description

本発明は、太陽電池のシリコン結晶ウェハと接続されるリード線及びその製造方法並びに太陽電池アセンブリに関するものである。   The present invention relates to a lead wire connected to a silicon crystal wafer of a solar cell, a manufacturing method thereof, and a solar cell assembly.

太陽電池として、基板上にシリコン結晶を成長させた半導体チップが使用されている。図4に示すように、この半導体チップを切断、分割してなるシリコン結晶ウェハ(以下、シリコンセルと記す)41の所定の領域(接点領域)に、はんだ付けなどにより接続用リード線42が接合され、この接続用リード線42を通じて電力が伝送(出力)される。   As a solar cell, a semiconductor chip in which a silicon crystal is grown on a substrate is used. As shown in FIG. 4, a connecting lead wire 42 is joined to a predetermined region (contact region) of a silicon crystal wafer (hereinafter referred to as a silicon cell) 41 obtained by cutting and dividing the semiconductor chip by soldering or the like. Then, power is transmitted (output) through the connecting lead wire 42.

通常、接続用リード線として、導体の表面に、シリコンセルとの接続のためのはんだめっき膜が形成される。例えば、図5に示すように、導体としては、タフピッチ銅や無酸素銅などの純銅の平角導体51を用い、はんだめっき膜55としては、Sn−Pb共晶はんだを用いた接続用リード線50がある(例えば、特許文献1参照)。   Usually, as a lead wire for connection, a solder plating film for connection to a silicon cell is formed on the surface of a conductor. For example, as shown in FIG. 5, a connecting lead wire 50 using a pure copper flat conductor 51 such as tough pitch copper or oxygen-free copper as the conductor, and Sn—Pb eutectic solder as the solder plating film 55. (For example, refer to Patent Document 1).

また、近年、環境への配慮から、はんだめっき膜の構成材として、Pbを含まないはんだ(Pbフリーはんだ)への切り替えが検討されている(例えば、特許文献2参照)。   In recent years, switching to a solder containing no Pb (Pb-free solder) as a constituent material of a solder plating film has been studied in consideration of the environment (for example, see Patent Document 2).

ところで、太陽電池を構成する部材の内、シリコンセルが材料コストの大半を占めていることから、製造コストの低減を図るべく、シリコンセルの薄板化が検討されている。しかし、シリコンセルを薄板化すると、接続用リード線のはんだ接合時における加熱プロセスや、太陽電池使用時における温度変化により、シリコンセルに反りが生じたり、破損が生じたりするという不具合が生ずる。例えば、図6(a)に示すように、はんだ接合前は平面状であったシリコンセル61及びリード線62をはんだ接合することにより、はんだ接合後の熱収縮により、図6(b)に矢印65で示すように反りが生じてしまう。   By the way, since the silicon cell occupies most of the material cost among the members constituting the solar battery, it is considered to reduce the thickness of the silicon cell in order to reduce the manufacturing cost. However, when the silicon cell is thinned, there is a problem that the silicon cell is warped or damaged due to a heating process at the time of soldering the connecting lead wire or a temperature change at the time of using the solar cell. For example, as shown in FIG. 6 (a), the silicon cell 61 and the lead wire 62, which were flat before soldering, are joined by soldering, and heat shrinkage after soldering causes the arrow in FIG. 6 (b). As shown by 65, warping occurs.

特開平11−21660号公報Japanese Patent Laid-Open No. 11-21660 特開2002−263880号公報JP 2002-263880 A

この問題に対処すべく、接続用リード線として、熱膨張が小さいもののニーズが高まっている。例えば、熱膨張が小さいリード線の一例として、図7に示すように、銅材72a−インバー(登録商標)材73−銅材72bのクラッド材である平角導体71をはんだ膜75で被覆したリード線70がある。   In order to cope with this problem, there is an increasing need for a connection lead wire that has a small thermal expansion. For example, as an example of a lead wire with small thermal expansion, as shown in FIG. 7, a lead in which a flat conductor 71, which is a clad material of a copper material 72 a -Invar (registered trademark) material 73 -copper material 72 b, is covered with a solder film 75. There is a line 70.

ところで、図7に示したリード線70は、インバー(登録商標)が低熱膨張であるため、シリコンセルを構成するSiとの熱膨張整合が可能である。しかしながら、インバー(登録商標)はCuと比べて導電率が低いことから、リード線全体としての導電率が低下してしまう。その結果、太陽電池としての発電効率が低下するという問題があった。   By the way, since Invar (registered trademark) has low thermal expansion, the lead wire 70 shown in FIG. 7 is capable of thermal expansion matching with Si constituting the silicon cell. However, since Invar (registered trademark) has a lower conductivity than Cu, the conductivity of the entire lead wire is lowered. As a result, there has been a problem that power generation efficiency as a solar cell is lowered.

以上の事情を考慮して創案された本発明の目的は、はんだ接合後の熱収縮が少なく、導電率が良好なリード線及びその製造方法並びに太陽電池アセンブリを提供することにある。   An object of the present invention, which was created in view of the above circumstances, is to provide a lead wire with a small electrical shrinkage after solder bonding and good conductivity, a method for manufacturing the lead wire, and a solar cell assembly.

上記目的を達成すべく本発明に係るリード線は、Cu素線からなる複数本の編組線を束ねた複合体を断面矩形状に変形させた矩形体の外周の少なくとも一部を、はんだ膜で被覆したものである。 In order to achieve the above object, the lead wire according to the present invention comprises a solder film on at least a part of the outer periphery of a rectangular body obtained by deforming a composite of a plurality of braided wires made of Cu strands into a rectangular cross section. It is coated.

本発明に係るリード線は、平角導体の外周の少なくとも一部をはんだ膜で被覆したリード線において、上記平角導体を、Cu素線からなる複数本の編組線を束ねた複合体を偏平させてなる偏平体で構成したものである。 A lead wire according to the present invention is a lead wire in which at least a part of the outer periphery of a flat conductor is covered with a solder film, and the flat conductor is flattened with a composite of a plurality of braided wires made of Cu strands. It is comprised with the flat body which becomes.

また、矩形体及び平角導体の0.5%耐力は70MPa以下が好ましい。はんだ膜はSn-Ag-Cu系Pbフリーはんだ合金で構成することが好ましい。矩形体及び平角導体の導電率は60%IACS以上が好ましい。   The 0.5% proof stress of the rectangular body and the rectangular conductor is preferably 70 MPa or less. The solder film is preferably composed of a Sn—Ag—Cu Pb-free solder alloy. The conductivity of the rectangular body and the rectangular conductor is preferably 60% IACS or more.

また、本発明に係るリード線の製造方法は、Cu素線からなる複数本の編組線を束ねた複合体に圧延加工を施して断面偏平状の偏平体を形成し、その偏平体を平角導体とし、平角導体の外周の少なくとも一部にはんだめっきを行い、はんだ膜を形成するものである。 The lead wire manufacturing method according to the present invention also includes forming a flat body having a flat cross section by rolling a composite body in which a plurality of braided wires made of Cu wire are bundled, and forming the flat body into a flat conductor. And solder plating is performed on at least a part of the outer periphery of the rectangular conductor to form a solder film.

一方、本発明に係る太陽電池アセンブリは、上述した本発明に係るリード線とシリコンセルとをはんだ接合したものである。   On the other hand, the solar cell assembly according to the present invention is obtained by soldering the lead wire and the silicon cell according to the present invention described above.

本発明によれば、はんだ接合後の熱収縮が少ないリード線を得ることができるという優れた効果を発揮する。   According to the present invention, it is possible to obtain an excellent effect that a lead wire with less heat shrinkage after soldering can be obtained.

以下、本発明の参考例となる実施の形態を添付図面に基づいて説明する。 DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments serving as reference examples of the present invention will be described below with reference to the accompanying drawings.

本発明の参考例となる実施の形態に係るリード線の横断面図を図1に示す。 FIG. 1 shows a cross-sectional view of a lead wire according to an embodiment as a reference example of the present invention.

発明の参考例となる実施の形態に係るリード線は、撚線を断面矩形状に変形させた矩形体の外周の少なくとも一部をはんだ膜15で被覆したものである。より具体的には、図1に示すように、本発明の参考例となる実施の形態に係るリード線10は、複数本の素線12(図1中では7本の場合を図示)を撚り合わせた撚線を偏平させて偏平体とし、この偏平体(平角導体11)の外周全体をはんだ膜15で被覆したものである。 A lead wire according to an embodiment serving as a reference example of the present invention is one in which at least a part of the outer periphery of a rectangular body obtained by deforming a stranded wire into a rectangular cross section is covered with a solder film 15. More specifically, as shown in FIG. 1, a lead wire 10 according to an embodiment serving as a reference example of the present invention is formed by twisting a plurality of strands 12 (seven cases are shown in FIG. 1). The combined twisted wires are flattened to form a flat body, and the entire outer periphery of the flat body (flat conductor 11) is covered with the solder film 15.

撚線は、Cu素線、Al素線、Ag素線、Au素線、Fe-Ni合金素線、又はそれらを組み合わせたもので構成され、素線12間の間隔が大きい(空隙率が高い)ものが好ましい。ここで言うCu素線、Al素線、Ag素線、Au素線とは、Cu又はCu合金、Al又はAl合金、Ag又はAg合金、Au又はAu合金で構成された素線である。Fe-Ni合金素線の構成材としては、好ましくはインバー(登録商標)が挙げられる。   The stranded wire is composed of a Cu strand, an Al strand, an Ag strand, an Au strand, an Fe—Ni alloy strand, or a combination thereof, and has a large interval between the strands 12 (high porosity). ) Is preferred. The Cu strand, the Al strand, the Ag strand, and the Au strand referred to here are strands made of Cu or Cu alloy, Al or Al alloy, Ag or Ag alloy, Au or Au alloy. As a constituent material of the Fe—Ni alloy strand, Invar (registered trademark) is preferable.

この時、コストパフォーマンスを重視する場合はCu素線を用いるのが好ましい。また、低体積抵抗率(高導電性)を重視する場合はAg素線を用いるのが好ましい。さらに、軽量性を重視する場合はAl素線を用いるのが好ましい。また、はんだ接合後の低熱収縮性(熱収縮が少ないこと)を重視する場合は、異種素線を複合させることが好ましく、特にCu素線(又はAl素線、Ag素線、Au素線のいずれか)とFe-Ni合金素線とを組み合わせたものが好ましい。Cu素線及びFe-Ni合金素線の各断面積の比(Cu/Fe-Ni)は、3.0〜5.0、好ましくは4.0前後となるように調整される。この調整は、Cu素線及びFe-Ni合金素線の本数を調整することによってなされる。   At this time, when importance is attached to cost performance, it is preferable to use a Cu strand. Further, when importance is attached to low volume resistivity (high conductivity), it is preferable to use an Ag strand. Furthermore, when importance is attached to lightness, it is preferable to use an Al strand. In addition, when importance is attached to low heat shrinkability (less heat shrinkage) after soldering, it is preferable to combine different kinds of strands, particularly Cu strands (or Al strands, Ag strands, Au strands). Any one) and a Fe—Ni alloy wire are preferable. The ratio (Cu / Fe-Ni) of the cross-sectional areas of the Cu strand and the Fe—Ni alloy strand is adjusted to be 3.0 to 5.0, preferably around 4.0. This adjustment is made by adjusting the number of Cu strands and Fe—Ni alloy strands.

はんだ膜15は、Sn-Pb共晶はんだや、Pbフリーはんだで構成され、好ましくはSn-Ag-Cu系のPbフリーはんだが挙げられる。また、Sn-Ag-Cu系のPbフリーはんだは、更にIn及び/又はPを含んでいてもよい。Inの含有量は1〜10重量%、Pの含有量は0.005〜0.015重量%が好ましい。例えば、Sn-Ag-Cu系のPbフリーはんだとしては、
Sn-3(又は4)Ag-0.5Cu-0.01P、
Sn-3(又は4)Ag-0.5Cu-3In、
Sn-3(又は4)Ag-0.5Cu-3In-0.01P、
Sn-3(又は4)Ag-0.5Cu-5In、
Sn-3(又は4)Ag-0.5Cu-5In-0.01P、
Sn-3(又は4)Ag-0.5Cu-8In、
Sn-3(又は4)Ag-0.5Cu-8In-0.01P、
等が挙げられる(単位はいずれも重量%)。ここで、Inの含有量を1〜10重量%としたのは、10重量%を超えて含有させると、溶融はんだの粘性が高くなり、はんだ付け作業性が低下するためである。また、Pの含有量を0.005〜0.015重量%とすることで、はんだ付け作業時におけるはんだの酸化変色を防止することができるため、接続(はんだ付け)の信頼性を向上させることができる。
The solder film 15 is made of Sn—Pb eutectic solder or Pb free solder, and preferably Sn—Ag—Cu Pb free solder. The Sn—Ag—Cu-based Pb-free solder may further contain In and / or P. The In content is preferably 1 to 10% by weight, and the P content is preferably 0.005 to 0.015% by weight. For example, Sn-Ag-Cu Pb-free solder
Sn-3 (or 4) Ag-0.5Cu-0.01P,
Sn-3 (or 4) Ag-0.5Cu-3In,
Sn-3 (or 4) Ag-0.5Cu-3In-0.01P,
Sn-3 (or 4) Ag-0.5Cu-5In,
Sn-3 (or 4) Ag-0.5Cu-5In-0.01P,
Sn-3 (or 4) Ag-0.5Cu-8In,
Sn-3 (or 4) Ag-0.5Cu-8In-0.01P,
(The unit is weight%). Here, the reason why the content of In is set to 1 to 10% by weight is that when the content exceeds 10% by weight, the viscosity of the molten solder becomes high and the soldering workability decreases. Further, by setting the P content to 0.005 to 0.015% by weight, it is possible to prevent oxidative discoloration of the solder during the soldering operation, so that the reliability of connection (soldering) can be improved.

はんだ膜15の膜厚は、平角導体11の厚さの1/30〜1/3、好ましくは1/10〜1/3、特に好ましくは1/5とされる。   The film thickness of the solder film 15 is 1/30 to 1/3, preferably 1/10 to 1/3, particularly preferably 1/5 of the thickness of the flat conductor 11.

矩形体、すなわち平角導体11の0.5%耐力は70MPa以下、好ましくは60MPa以下、より好ましくは50MPa以下、特に好ましくは40MPa以下とされる。ここで言う0.5%耐力とは、0.5%の伸びを生ずる時の応力値を示している。また、矩形体、すなわち平角導体11の導電率は60%IACS以上が好ましい。   The 0.5% proof stress of the rectangular body, that is, the flat conductor 11, is 70 MPa or less, preferably 60 MPa or less, more preferably 50 MPa or less, and particularly preferably 40 MPa or less. The 0.5% proof stress mentioned here indicates the stress value when 0.5% elongation occurs. The conductivity of the rectangular body, that is, the rectangular conductor 11, is preferably 60% IACS or more.

はんだ膜15による平角導体11の被覆は、平角導体11の外周の一部(例えば、平角導体11の上面及び/又は下面)だけであってもよい。このリード線10を、シリコンセル(太陽電池モジュール(図示せず))におけるセル面の所定の接点領域(例えば、Agめっき領域)及びフレーム部材(例えば、リードフレーム)の所定の接点領域に接続することで、太陽電池アセンブリが得られる。セル面及びリードフレームの所定の接点領域にも、接合用のはんだ膜を設けていてもよい。   The covering of the flat conductor 11 with the solder film 15 may be only a part of the outer periphery of the flat conductor 11 (for example, the upper surface and / or the lower surface of the flat conductor 11). The lead wire 10 is connected to a predetermined contact region (for example, an Ag plating region) on a cell surface in a silicon cell (solar cell module (not shown)) and a predetermined contact region on a frame member (for example, a lead frame). Thus, a solar cell assembly is obtained. Solder films for bonding may also be provided in predetermined contact areas of the cell surface and the lead frame.

次に、本発明の参考例となる実施の形態に係るリード線10の製造方法を、添付図面に基づいて説明する。 Next, the manufacturing method of the lead wire 10 which concerns on embodiment used as the reference example of this invention is demonstrated based on an accompanying drawing.

平角導体11を構成する偏平体の製造は、図2に示すロール圧延機20や、通常の圧延機を用いて行う。具体的には、撚線をロール圧延機20の圧延ロール21a,21b間に通すことで、撚線が偏平されて偏平体が得られる。この時、幅方向(図2中では左右方向)の中央部に位置する撚線の素線22aは圧縮率が高く、幅方向の両側部に位置する撚線の素線22bは圧縮率が低くなる。また、撚線が異種素線の複合線で構成される場合、熱収縮が少ない素線(例えば、インバー(登録商標)素線)を撚線の外側に配置することが好ましい。これは、はんだ接合時、平角導体11の外周部が最も熱的影響を受ける(高温となる)ためである。   The flat body constituting the flat conductor 11 is manufactured using the roll mill 20 shown in FIG. 2 or a normal rolling mill. Specifically, the stranded wire is flattened by passing the stranded wire between the rolling rolls 21a and 21b of the roll mill 20, and a flat body is obtained. At this time, the strand 22a of the stranded wire located at the center in the width direction (left and right in FIG. 2) has a high compression rate, and the strand 22b of the stranded wire located at both sides in the width direction has a low compression rate. Become. Moreover, when a twisted wire is comprised with the composite wire of a dissimilar strand, it is preferable to arrange | position a strand (for example, an Invar (trademark) strand) with few heat shrinks on the outer side of a twisted wire. This is because the outer peripheral portion of the rectangular conductor 11 is most thermally affected (high temperature) during solder joining.

この偏平体を平角導体11とし、平角導体11の外周の少なくとも一部にはんだめっきを行うことではんだ膜15が形成され、図1に示した本発明の参考例となる実施の形態に係るリード線10が得られる。この時、はんだ膜15の形成方法は、特に限定するものではなく、導体に対する慣用のめっき方法が全て適用可能である。 The flat body is used as a flat conductor 11, and solder film 15 is formed by performing solder plating on at least a part of the outer periphery of the flat conductor 11, and the lead according to the embodiment serving as a reference example of the present invention shown in FIG. Line 10 is obtained. At this time, the method for forming the solder film 15 is not particularly limited, and all conventional plating methods for conductors can be applied.

得られたリード線10は、シリコンセルの所定の接点領域に接合され、太陽電池アセンブリとされる。   The obtained lead wire 10 is joined to a predetermined contact region of the silicon cell to form a solar cell assembly.

次に、本発明の参考例となる実施の形態に係るリード線10の作用を説明する。 Next, the operation of the lead wire 10 according to the embodiment serving as a reference example of the present invention will be described.

リード線とシリコンセルとのはんだ接合時、熱付与によってリード線の平角導体が熱膨張する。例えば、Cu導体の熱膨張率は0.3%程度である。リード線は、平角導体が熱膨張した状態でシリコンセルとはんだ接合される。その後、熱付与を止めることではんだが冷却され、凝固するが、この冷却時に平角導体が熱収縮するため、シリコンセルに反りが生じる。ここで、平角導体にテンションを付与して0.5%程度の伸びを生じさせた時の0.5%耐力がゼロに近い程、熱収縮がシリコンセルに与える影響が小くなる。 When soldering the lead wire and the silicon cell, the rectangular conductor of the lead wire is thermally expanded by heat application. For example, the coefficient of thermal expansion of the Cu conductor is about 0.3%. The lead wire is soldered to the silicon cell in a state where the flat conductor is thermally expanded. Thereafter, the solder is cooled and solidified by stopping the application of heat, but the flat conductor is thermally shrunk during this cooling, so that the silicon cell is warped. Here, flat as close to zero 0.5% yield strength when causing elongation of about 0.5% by applying a tension to the conductor, the effect of thermal shrinkage has on the silicon cell is small Kunar.

同じ材料を用いて同じ断面積の中実導体及び撚線導体を作製した場合、ある温度における熱膨張量は同じである。しかし、中実導体を平角導体として用いたリード線(図5参照)及び撚線導体を平角導体として用いたリード線(図1参照)を、それぞれシリコンセルとはんだ接合させた場合、熱付与後の各リード線に残留する応力はそれぞれ異なっている。この残留した応力値が、シリコンセルの反り量を決定する要因となる。   When a solid conductor and a stranded wire conductor having the same cross-sectional area are manufactured using the same material, the thermal expansion amount at a certain temperature is the same. However, when a lead wire using a solid conductor as a flat conductor (see FIG. 5) and a lead wire using a twisted conductor as a flat conductor (see FIG. 1) are soldered to a silicon cell, respectively, after heat application The residual stress in each lead wire is different. This residual stress value is a factor that determines the amount of warpage of the silicon cell.

ここで、本発明の参考例となる実施の形態に係るリード線10では、平角導体11を撚線の偏平体で構成すると共に、平角導体11の0.5%耐力を70MPa以下に調整している。0.5%耐力値は、平角導体11を構成する撚線の素線12の間隔を調整することで自在に調整可能であり、素線間隔が大きいほど、0.5%耐力値は小さくなる。撚線は、素線間に空間を有しているため、撚線を偏平させてなる偏平体においても、素線間に僅かながら空間を有している。このため、平角導体11に外力(テンション)が作用しても、素線間の空間を利用して各素線が移動することで、外力が緩和、緩衝される。 Here, in the lead wire 10 according to the embodiment which is a reference example of the present invention , the flat conductor 11 is formed of a stranded wire flat body, and the 0.5% proof stress of the flat conductor 11 is adjusted to 70 MPa or less. The 0.5% proof stress value can be freely adjusted by adjusting the distance between the strands 12 of the stranded wire constituting the flat conductor 11, and the 0.5% proof stress value decreases as the strand distance increases. Since the stranded wire has a space between the strands, even a flat body obtained by flattening the stranded wire has a slight space between the strands. For this reason, even if an external force (tension) acts on the flat conductor 11, the external force is relaxed and buffered by moving each strand using the space between the strands.

よって、本発明の参考例となる実施の形態に係るリード線10とシリコンセルとをはんだ接合すると、熱付与時に平角導体11が熱膨張するが、各素線が移動することで、平角導体11に生じる応力は小さくなる(平角導体11の0.5%耐力値は小さくなる)。その結果、平角導体11に残留される応力も小さくなることから、熱付与後の熱収縮時において、平角導体11の熱収縮がシリコンセルに及ぼす影響が小さくなる。 Therefore, when the lead wire 10 and the silicon cell according to the embodiment which is a reference example of the present invention are solder-bonded, the flat conductor 11 is thermally expanded when heat is applied, but the flat conductor 11 is moved by moving each strand. (5% proof stress value of the rectangular conductor 11 is reduced). As a result, since the stress remaining in the flat conductor 11 is also reduced, the influence of the heat shrinkage of the flat conductor 11 on the silicon cell is reduced during heat shrinkage after heat application.

これに対して、中実導体を平角導体として用いたリード線においては、中実導体に外力(テンション)を作用させても、外力が緩和、緩衝されることはない。よって、このリード線とシリコンセルとをはんだ接合すると、熱付与時に平角導体が熱膨張し、そのまま平角導体に応力として残留する。その結果、熱付与後の熱収縮時に、平角導体の熱収縮によってシリコンセルに大きな反りが生じる。   On the other hand, in a lead wire using a solid conductor as a flat conductor, even if an external force (tension) is applied to the solid conductor, the external force is not relaxed or buffered. Therefore, when this lead wire and the silicon cell are soldered together, the rectangular conductor is thermally expanded when heat is applied, and remains in the rectangular conductor as stress as it is. As a result, during the heat shrinkage after heat application, the silicon cell is greatly warped by the heat shrinkage of the flat conductor.

以上より、本発明の参考例となる実施の形態に係るリード線10を太陽電池の接続用リード線として用いることで、はんだ接合後のシリコンセルにおいて反りはほとんど生じなくなる。シリコンセルの反り量は2.5mm未満が好ましく、より好ましくは2.0mm以下、特に好ましくは1.5mm以下とされる。また、本発明の参考例となる実施の形態に係るリード線10は、シリコンセルとのはんだ付け後にセル反りが殆ど生じないことから、太陽電池アセンブリの生産性向上を図ることができる。 As described above, by using the lead wire 10 according to the embodiment serving as a reference example of the present invention as the connecting lead wire of the solar battery, warpage hardly occurs in the silicon cell after soldering. The warpage amount of the silicon cell is preferably less than 2.5 mm, more preferably 2.0 mm or less, and particularly preferably 1.5 mm or less. In addition, since the lead wire 10 according to the embodiment serving as a reference example of the present invention hardly causes cell warping after soldering with a silicon cell, the productivity of the solar cell assembly can be improved.

また、これまでは、リード線とシリコンセルとのはんだ接合時における熱膨張量を少なくすることを重視した場合、はんだ膜15を構成するはんだとして、低融点のSn-Pb共晶はんだが多用されていた。このことが、Pbフリー化を阻む要因となっていた。ところが、本発明の参考例となる実施の形態に係るリード線10は、はんだ接合後の熱収縮が少ないことから、Sn-Pb共晶はんだよりも融点が高いPbフリーはんだを用いることが可能となる。 In the past, Sn-Pb eutectic solder having a low melting point has been frequently used as the solder constituting the solder film 15 when importance is attached to reducing the amount of thermal expansion at the time of solder joining between the lead wire and the silicon cell. It was. This was a factor that hindered Pb-free. However, since the lead wire 10 according to the embodiment serving as a reference example of the present invention has less thermal shrinkage after solder bonding, it is possible to use Pb-free solder having a higher melting point than Sn—Pb eutectic solder. Become.

一般に、Pbフリーはんだは、Sn-Pb共晶はんだに比べて溶融温度が高いため、はんだ接合により、接続部材(セル面及びリードフレームの接点領域)へのダメージが懸念される。しかし、Pbフリーはんだの中で、Sn-3Ag-0.5Cu系はんだ及びSn-4Ag-0.5Cu系はんだ(単位はいずれも重量%)は、溶融温度が低いという特長を有している。また、これらのはんだに更にIn及び/又はPを含ませることによって、はんだの溶融温度を更に低くすることができる。これらの組成のSn-Ag-Cu系Pbフリーはんだを用いることで、はんだ接合時におけるシリコンセルの変形や破損のおそれを更に低減させることができる。   In general, Pb-free solder has a higher melting temperature than Sn—Pb eutectic solder, so there is a concern about damage to the connection member (cell surface and lead frame contact area) due to solder bonding. However, among Pb-free solders, Sn-3Ag-0.5Cu solder and Sn-4Ag-0.5Cu solder (both units are weight%) have a feature that the melting temperature is low. Moreover, by further including In and / or P in these solders, the melting temperature of the solder can be further lowered. By using Sn—Ag—Cu-based Pb-free solder having these compositions, it is possible to further reduce the risk of deformation or breakage of the silicon cell during solder joining.

発明の参考例となる実施の形態に係るリード線10を用いてシリコンセルとはんだ接合を行う際に、図5や図7に示したリード線50,70を用いた場合とセル反り量が同じであってよい場合、リード線10の導電率を向上させることができる。また、本発明の参考例となる実施の形態に係るリード線10を用いてシリコンセルとはんだ接合を行う際に、図5や図7に示したリード線50,70を用いた場合と導電率が同じであってよい場合、リード線10のセル反りをより小さくすることができる。 When the lead wire 10 according to the embodiment which is a reference example of the present invention is used for solder bonding with a silicon cell, the amount of warpage of the cell is the same as when the lead wires 50 and 70 shown in FIGS. 5 and 7 are used. When it may be the same, the electrical conductivity of the lead wire 10 can be improved. Further, when the lead wire 10 according to the embodiment serving as a reference example of the present invention is used for solder bonding with a silicon cell, the case where the lead wires 50 and 70 shown in FIGS. Can be the same, the cell warpage of the lead wire 10 can be further reduced.

発明の参考例となる実施の形態に係るリード線10は、太陽電池アセンブリのリード線として適用することができる他に、はんだ接合後の反りが問題となる全ての部品のリード線として使用することが可能である。 The lead wire 10 according to the embodiment serving as a reference example of the present invention can be used as a lead wire of a solar cell assembly, and also used as a lead wire for all components in which warpage after soldering is a problem. It is possible.

次に、本発明の実施の形態を添付図面に基づいて説明する。 It will now be described with reference to the implementation of the present invention in the accompanying drawings.

本発明の好適一実施の形態に係るリード線の横断面図を図3に示す。尚、図1と同じ部材であるはんだ膜については、図3においても同じ符号を付しており、この部材については説明を省略する。 A cross-sectional view of the lead according to good proper one embodiment of the present invention shown in FIG. In addition, about the solder film which is the same member as FIG. 1, the same code | symbol is attached | subjected also in FIG. 3, and description is abbreviate | omitted about this member.

本実施の形態に係るリード線は、複数本の編組線を束ねた複合体を断面矩形状に変形させた矩形体の外周の少なくとも一部をはんだ膜15で被覆したものである。より具体的には、図3に示すように、複数本の編組線32を束ね(図3中では4本束ねの場合を図示)たものが複合体33とされる。この複合体33を複数本(図3中では18本の場合を図示)束ねたものが偏平体とされ、この偏平体(平角導体31)の外周全体をはんだ膜15で被覆したものが、本実施の形態に係るリード線30とされる。複合体33は、複数本の編組線32を撚り合わせたものであってもよい。   In the lead wire according to the present embodiment, at least a part of the outer periphery of a rectangular body obtained by deforming a composite body in which a plurality of braided wires are bundled into a rectangular cross section is covered with a solder film 15. More specifically, as shown in FIG. 3, a composite 33 is formed by bundling a plurality of braided wires 32 (in FIG. 3, the case of four bundles is shown). A bundle of a plurality of the composite bodies 33 (in the case of 18 in FIG. 3) is a flat body, and the entire outer periphery of the flat body (flat conductor 31) is covered with the solder film 15. The lead wire 30 according to the embodiment is used. The composite 33 may be one in which a plurality of braided wires 32 are twisted together.

編組線32は、Cu素線から構成される。編組線32は小径になるほど、平角導体31の中実率が高くなる。
Braided wire 32 is comprised of C u wire. The smaller the diameter of the braided wire 32, the higher the solid ratio of the flat conductor 31.

次に、本実施の形態に係るリード線30の製造方法を、添付図面に基づいて説明する。   Next, a method for manufacturing the lead wire 30 according to the present embodiment will be described with reference to the accompanying drawings.

平角導体31を構成する偏平体の製造は、図3に示した複合体33を平行に複数本(図3中では9本の場合を図示)配列して複合体群とし、この複合体群を複層(図3中では2層の場合を図示)に重ねることで、偏平体が形成される。ここで、複数本の複合体33を撚り合わせた撚線を、図2に示したロール圧延機20を用いて圧延、偏平させて偏平体としてもよい。   The flat body constituting the rectangular conductor 31 is manufactured by arranging a plurality of composite bodies 33 shown in FIG. 3 in parallel (9 cases shown in FIG. 3) to form a composite group. A flat body is formed by overlapping a plurality of layers (in the case of two layers in FIG. 3). Here, a stranded wire obtained by twisting a plurality of composite bodies 33 may be rolled and flattened using the roll rolling machine 20 shown in FIG.

この偏平体を平角導体31とし、平角導体31の外周の少なくとも一部にはんだめっきを行うことではんだ膜15が形成され、図3に示した本実施の形態に係るリード線30が得られる。   This flat body is used as a flat conductor 31, and solder plating is performed on at least a part of the outer periphery of the flat conductor 31 to form the solder film 15, and the lead wire 30 according to the present embodiment shown in FIG. 3 is obtained.

本実施の形態に係るリード線30においても、前実施の形態に係るリード線10と同様の作用効果が期待される。また、本実施の形態に係るリード線30の平角導体31を構成する編組線32は、図1に示した撚線12と比べて、線全体に占める空間の割合が大きい。このため、リード線30は、リード線10と比較して、応力緩和効果が更に高くなり、その結果、シリコンセルの反り量がより小さくなる。   Also in the lead wire 30 according to the present embodiment, the same effect as the lead wire 10 according to the previous embodiment is expected. Moreover, the braided wire 32 which comprises the flat conductor 31 of the lead wire 30 which concerns on this Embodiment has a large ratio of the space which occupies for the whole wire compared with the twisted wire 12 shown in FIG. For this reason, the lead wire 30 has a higher stress relaxation effect than the lead wire 10, and as a result, the amount of warpage of the silicon cell becomes smaller.

以上、本発明は、上述した実施の形態に限定されるものではなく、他にも種々のものが想定されることは言うまでもない。   As described above, the present invention is not limited to the above-described embodiment, and it goes without saying that various other things are assumed.

次に、本発明について、参考実施例に基づいて説明するが、本発明はこの参考実施例に限定されるものではない。 Next, although this invention is demonstrated based on a reference example, this invention is not limited to this reference example.

参考実施例1)
外径が0.26mmのタフピッチ銅(TPC)素線を7本撚りあわせ、撚線を作製した(断面積は約0.37mm2)。この撚線の素線間隔は0.003mmとし、その0.5%耐力は50MPaとした。
( Reference Example 1)
Seven tough pitch copper (TPC) wires having an outer diameter of 0.26 mm were twisted to produce a stranded wire (cross-sectional area of about 0.37 mm 2 ). The strand spacing of the stranded wires was 0.003 mm, and the 0.5% proof stress was 50 MPa.

この撚線を図2に示したロール圧延機を用いて圧延し、平角状の偏平体(平角導体)を作製した。この平角導体の周囲に、Sn-3Ag-0.5CuのPbフリーはんだめっき膜を0.02mmの膜厚で形成し、図1に示した構造のリード線を作製した。   This stranded wire was rolled using the roll mill shown in FIG. 2 to produce a flat rectangular body (flat conductor). A Sn-3Ag-0.5Cu Pb-free solder plating film with a thickness of 0.02 mm was formed around the flat conductor to produce a lead having the structure shown in FIG.

参考実施例2)
撚線の素線間隔が0.010mm、その0.5%耐力が0MPaである以外は、参考実施例1と同様にしてリード線を作製した。
( Reference Example 2)
A lead wire was produced in the same manner as in Reference Example 1 except that the strand spacing of the stranded wires was 0.010 mm and the 0.5% proof stress was 0 MPa.

(従来例1)
インバー(登録商標)製で、幅が2.0mm、板厚が0.037mmの板材を、Cu製で、幅が2.0mm、板厚が0.074mm板材で挟んでなる幅2.0mm、板厚0.185mmのクラッド材(平角導体)を作製した(断面積は0.37mm2)。
(Conventional example 1)
Invar (registered trademark) made of Cu with a width of 2.0 mm and a thickness of 0.037 mm, made of Cu, with a width of 2.0 mm and a thickness of 0.074 mm sandwiched between the plates, a width of 2.0 mm and a thickness of 0.185 mm A clad material (flat rectangular conductor) was produced (cross-sectional area was 0.37 mm 2 ).

この平角導体の周囲に、Sn-3Ag-0.5CuのPbフリーはんだめっき膜を0.02mmの膜厚で形成し、図7に示した構造のリード線を作製した。   A Sn-3Ag-0.5Cu Pb-free solder plating film with a thickness of 0.02 mm was formed around the flat conductor to produce a lead having the structure shown in FIG.

参考実施例1,2及び従来例1の各リード線と200μm厚のシリコンセルとをそれぞれはんだ接続し、接続後におけるシリコンセルの反り量(セル反り:mm)を評価した。参考実施例1,2及び従来例1の各リード線の構造及び評価結果を表1に示す。 Each lead wire of Reference Examples 1 and 2 and Conventional Example 1 and a 200 μm thick silicon cell were connected by soldering, and the warpage amount (cell warpage: mm) of the silicon cell after connection was evaluated. Table 1 shows the structures and evaluation results of the lead wires of Reference Examples 1 and 2 and Conventional Example 1.

Figure 0004792713
Figure 0004792713

表1に示すように、従来例1のリード線を用いた場合、セル反りが2.5mmと大きかった。 As shown in Table 1, when the lead wire of Conventional Example 1 was used, the cell warpage was as large as 2.5 mm.

これに対して、参考実施例1,2の各リード線を用いた場合、セル反りは1.6mm、0.3mmであり、いずれも規定値(2.5mm未満)を満足していた。このことから、0.5%耐力を50MPa以下とすることで、セル反りを1.6mm以下に小さくすることができ、太陽電池用のリード線として好適であることが確認できた。 On the other hand, when each lead wire of Reference Examples 1 and 2 was used, the cell warpage was 1.6 mm and 0.3 mm, and both satisfied the specified value (less than 2.5 mm). From this, it was confirmed that by setting the 0.5% proof stress to 50 MPa or less, the cell warpage can be reduced to 1.6 mm or less, which is suitable as a lead wire for a solar cell.

本発明の参考例となる実施の形態に係るリード線の横断面図である。It is a cross-sectional view of a lead wire according to an embodiment as a reference example of the present invention. 平角導体の製造方法を説明するための模式図である。It is a schematic diagram for demonstrating the manufacturing method of a flat conductor. 本発明の好適一実施の形態に係るリード線の横断面図である。It is a cross-sectional view of the lead according to good proper one embodiment of the present invention. シリコンセルとリード線との接続状態を示す図である。It is a figure which shows the connection state of a silicon cell and a lead wire. 従来のリード線の横断面図である。It is a cross-sectional view of a conventional lead wire. シリコンセルとリード線とのはんだ接合前後の状態を示す模式図である。It is a schematic diagram which shows the state before and behind the solder joint of a silicon cell and a lead wire. 低熱膨張型の平角導体を用いたリード線の横断面図である。It is a cross-sectional view of a lead wire using a low thermal expansion type flat conductor.

10 リード線
11 平角導体
12 素線
15 はんだ膜
10 Lead wire 11 Flat conductor 12 Wire 15 Solder film

Claims (7)

Cu素線からなる複数本の編組線を束ねた複合体を断面矩形状に変形させた矩形体の外周の少なくとも一部を、はんだ膜で被覆したことを特徴とするリード線。   A lead wire characterized by covering at least a part of the outer periphery of a rectangular body obtained by deforming a composite body in which a plurality of braided wires made of Cu strands are bundled into a rectangular cross section with a solder film. 平角導体の外周の少なくとも一部をはんだ膜で被覆したリード線において、上記平角導体を、Cu素線からなる複数本の編組線を束ねた複合体を偏平させてなる偏平体で構成したことを特徴とするリード線。   In a lead wire in which at least a part of the outer periphery of a flat conductor is covered with a solder film, the flat conductor is composed of a flat body obtained by flattening a composite of a plurality of braided wires made of Cu strands. Characteristic lead wire. 上記矩形体及び上記平角導体の0.5%耐力が70MPa以下である請求項1又は2記載のリード線。   The lead wire according to claim 1 or 2, wherein 0.5% proof stress of the rectangular body and the rectangular conductor is 70 MPa or less. 上記はんだ膜がSn−Ag−Cu系Pbフリーはんだ合金で構成される請求項1から3いずれかに記載のリード線。   The lead wire according to any one of claims 1 to 3, wherein the solder film is made of a Sn-Ag-Cu-based Pb-free solder alloy. 上記矩形体及び上記平角導体の導電率が60%IACS以上である請求項1から4いずれかに記載のリード線。   The lead wire according to any one of claims 1 to 4, wherein conductivity of the rectangular body and the rectangular conductor is 60% IACS or more. Cu素線からなる複数本の編組線を束ねた複合体に圧延加工を施して断面偏平状の偏平体を形成し、その偏平体を平各導体とし、平各導体の外周の少なくとも一部にはんだめっきを行い、はんだ膜を形成することを特徴とするリード線の製造方法。   A composite body in which a plurality of braided wires made of Cu strands are bundled is rolled to form a flat body having a flat cross section, and the flat body is a flat conductor, and at least part of the outer periphery of each flat conductor A method for producing a lead wire, comprising performing solder plating to form a solder film. 請求項1からいずれかに記載のリード線とシリコンセルとをはんだ接合したことを特徴とする太陽電池アセンブリ。

Solar cell assembly, characterized in that the soldered a lead wire and a silicon cell according to claims 1 to 5 or.

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