JP4777227B2 - パラメータ抽出方法及び回路動作検証方法並びに当該パラメータ抽出方法を実行させるためのプログラムを具備する記憶媒体 - Google Patents

パラメータ抽出方法及び回路動作検証方法並びに当該パラメータ抽出方法を実行させるためのプログラムを具備する記憶媒体 Download PDF

Info

Publication number
JP4777227B2
JP4777227B2 JP2006340954A JP2006340954A JP4777227B2 JP 4777227 B2 JP4777227 B2 JP 4777227B2 JP 2006340954 A JP2006340954 A JP 2006340954A JP 2006340954 A JP2006340954 A JP 2006340954A JP 4777227 B2 JP4777227 B2 JP 4777227B2
Authority
JP
Japan
Prior art keywords
value
calculated value
actual measurement
computer
calculated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2006340954A
Other languages
English (en)
Japanese (ja)
Other versions
JP2007200290A (ja
JP2007200290A5 (https=
Inventor
充朗 關
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP2006340954A priority Critical patent/JP4777227B2/ja
Publication of JP2007200290A publication Critical patent/JP2007200290A/ja
Publication of JP2007200290A5 publication Critical patent/JP2007200290A5/ja
Application granted granted Critical
Publication of JP4777227B2 publication Critical patent/JP4777227B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Design And Manufacture Of Integrated Circuits (AREA)
JP2006340954A 2005-12-27 2006-12-19 パラメータ抽出方法及び回路動作検証方法並びに当該パラメータ抽出方法を実行させるためのプログラムを具備する記憶媒体 Expired - Fee Related JP4777227B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006340954A JP4777227B2 (ja) 2005-12-27 2006-12-19 パラメータ抽出方法及び回路動作検証方法並びに当該パラメータ抽出方法を実行させるためのプログラムを具備する記憶媒体

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2005376630 2005-12-27
JP2005376630 2005-12-27
JP2006340954A JP4777227B2 (ja) 2005-12-27 2006-12-19 パラメータ抽出方法及び回路動作検証方法並びに当該パラメータ抽出方法を実行させるためのプログラムを具備する記憶媒体

Publications (3)

Publication Number Publication Date
JP2007200290A JP2007200290A (ja) 2007-08-09
JP2007200290A5 JP2007200290A5 (https=) 2009-12-03
JP4777227B2 true JP4777227B2 (ja) 2011-09-21

Family

ID=38454795

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006340954A Expired - Fee Related JP4777227B2 (ja) 2005-12-27 2006-12-19 パラメータ抽出方法及び回路動作検証方法並びに当該パラメータ抽出方法を実行させるためのプログラムを具備する記憶媒体

Country Status (1)

Country Link
JP (1) JP4777227B2 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5463856B2 (ja) * 2009-11-02 2014-04-09 富士通株式会社 入力パラメータ値セット特定プログラム、方法及び装置
US8515714B2 (en) * 2010-06-02 2013-08-20 Livermore Software Technology Corp. Curve matching for parameter identification
CN108894120B (zh) * 2018-02-09 2021-07-02 广西交通科学研究院有限公司 拱上建筑拆装过程中拱圈变形安全判断方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006012114A (ja) * 2004-05-25 2006-01-12 Oki Electric Ind Co Ltd 適応評価器、遺伝的アルゴリズムマシン及び適応度計算方法

Also Published As

Publication number Publication date
JP2007200290A (ja) 2007-08-09

Similar Documents

Publication Publication Date Title
McConaghy et al. Variation-aware design of custom integrated circuits: a hands-on field guide
US8302046B1 (en) Compact modeling of circuit stages for static timing analysis of integrated circuit designs
US8555236B2 (en) Non-invasive leakage power device characterization of integrated circuits using device grouping and compressive sensing
JP2004200461A (ja) 半導体装置特性シミュレーション方法及び半導体装置特性シミュレータ
CN103646114B (zh) 硬盘smart数据中特征数据提取方法和装置
Harrell Jr Resampling, validating, describing, and simplifying the model
JP4500338B2 (ja) テストパターン評価方法及びテストパターン評価装置
US10867115B2 (en) System and method for calculating cell edge leakage
TW201602819A (zh) 調整用於靜態時序分析的時序降額的方法
US9471732B2 (en) Equivalent device statistical modeling for bitline leakage modeling
JP4651620B2 (ja) 電力算出装置、電力算出方法、耐タンパ性評価装置及び耐タンパ性評価方法
CN107688694A (zh) 使用多个选通点的单元感知缺陷表征和波形分析
KR20170087354A (ko) 시뮬레이션 시간을 단축할 수 있는 반도체 집적 회로의 신뢰성 불량률 예측 방법 및 그 장치
JP4777227B2 (ja) パラメータ抽出方法及び回路動作検証方法並びに当該パラメータ抽出方法を実行させるためのプログラムを具備する記憶媒体
JPWO2012081158A1 (ja) 回路シミュレーション方法及び半導体集積回路
US8667442B1 (en) Circuit simulation methodology to calculate leakage current during any mode of circuit operation
CN117952039A (zh) 一种模型建立方法、装置、电子设备和计算机存储介质
JP4871194B2 (ja) パラメータ抽出方法及び当該パラメータ抽出方法を実行させるプログラムを具備するコンピュータ読み取り可能な記憶媒体
US7617056B2 (en) Parameter extraction method, method for inspecting circuit operation, and storage medium having program to perform the parameter extraction method
US20240249049A1 (en) Generation method for energy storage device model, generation device for energy storage device model, and program
US8380479B2 (en) Model parameter extracting apparatus and model parameter extracting program for semiconductor device model
JP5560700B2 (ja) 設計支援装置、設計支援方法及び設計支援プログラム
WO2014077671A1 (en) A method of generating spice-compatible isfet model
US20080141189A1 (en) Method for robust statistical semiconductor device modeling
CN116746930B (zh) 一种基于深度学习的老年人认知功能评估预警方法及系统

Legal Events

Date Code Title Description
A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20091021

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20091021

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20091021

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110222

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110406

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20110628

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20110629

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140708

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140708

Year of fee payment: 3

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees