JP4769484B2 - 仮想計算機をマイグレーションするための方法およびシステム - Google Patents
仮想計算機をマイグレーションするための方法およびシステム Download PDFInfo
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- JP4769484B2 JP4769484B2 JP2005130300A JP2005130300A JP4769484B2 JP 4769484 B2 JP4769484 B2 JP 4769484B2 JP 2005130300 A JP2005130300 A JP 2005130300A JP 2005130300 A JP2005130300 A JP 2005130300A JP 4769484 B2 JP4769484 B2 JP 4769484B2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45533—Hypervisors; Virtual machine monitors
- G06F9/45558—Hypervisor-specific management and integration aspects
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
- G06F9/485—Task life-cycle, e.g. stopping, restarting, resuming execution
- G06F9/4856—Task life-cycle, e.g. stopping, restarting, resuming execution resumption being on a different machine, e.g. task migration, virtual machine migration
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5061—Partitioning or combining of resources
- G06F9/5077—Logical partitioning of resources; Management or configuration of virtualized resources
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45533—Hypervisors; Virtual machine monitors
- G06F9/45558—Hypervisor-specific management and integration aspects
- G06F2009/4557—Distribution of virtual machine instances; Migration and load balancing
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- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Multi Processors (AREA)
- Stored Programmes (AREA)
Description
23:CPU
24:RAM
25:ロジカル・パーティション・プログラム
26:ストレージ
27:コンソール
30:ロジカル・パーティション(LPAR)
31:ロジカル・パーティション(LPAR)
33:仮想計算機
33M:仮想計算機
34:仮想計算機
34M:仮想計算機
35:仮想計算機
35M:仮想計算機
36:仮想計算機
37:仮想計算機
40:ハイパバイザ
41:ハイパバイザ
43:オペレーティング・システム
44:オペレーティング・システム
45:オペレーティング・システム
45M:仮想専用メモリ(VPM)
46:オペレーティング・システム
47:オペレーティング・システム
50:共用メモリ
51:共用メモリ
52:通信キュー
52−1:通信キュー
53:アプリケーション
54:アプリケーション
54:ブロック・メモリ
54−1:ブロック・メモリ
55:アプリケーション
56:アプリケーション
57:アプリケーション
80:作業メモリ
81:作業メモリ
110:コンピュータ・システム
Claims (2)
- 実コンピュータ内の第1のロジカル・パーティション(「LPAR」)から第2のロジカル・パーティションに、第1の仮想計算機および通信キューをマイグレーションするための方法において、マイグレーションの前に、前記第1の仮想計算機が前記第1の仮想計算機に専用の第1の専用メモリ内に前記第1の仮想計算機のオペレーティング・システムおよびアプリケーションを有し、マイグレーションの前に、前記通信キューが前記第1のLPAR内の前記第1の仮想計算機および第2の仮想計算機によって共用されアクセス可能な第1の共用メモリに常駐し、前記方法が、
前記第1の仮想計算機および前記第2の仮想計算機が前記第1のLPAR内の前記通信キューを更新するのを防止するために、前記第1のLPAR内で前記第1の仮想計算機および前記第2の仮想計算機を停止するステップと、
前記第1の仮想計算機および前記第2の仮想計算機が停止されている間に、前記第1のLPARが前記第2のLPARに前記第1の仮想計算機の前記オペレーティング・システムおよび前記アプリケーション、ならびに前記通信キューを伝達し、前記第2のLPARが前記第2のLPAR内の第2の専用メモリに前記第1の仮想計算機の前記オペレーティング・システムおよび前記アプリケーションを書き込み、前記第2のLPARが前記第2のLPAR内の第2の共用メモリに前記通信キューを書き込むステップと、
前記第1の仮想計算機に対応するマイグレーションされた仮想計算機のために前記第2のLPAR内の前記第2の専用メモリおよびプロセッサのシェアを割り振り、前記第2の共用メモリ内で前記通信キューへのアクセスを前記マイグレーションされた仮想計算機に許可するステップと、
前記第1の仮想計算機および前記第2の仮想計算機を停止する前記ステップの前に、前記第2の仮想計算機が前記通信キューに作業項目を供給するステップと、
前記第1の仮想計算機および前記第2の仮想計算機が停止されている間に、前記第1のLPARが前記第2のLPARに前記第2の仮想計算機のオペレーティング・システムおよびアプリケーションを伝達し、前記第2のLPARが前記第2のLPAR内の第3の専用メモリに前記第2の仮想計算機の前記オペレーティング・システムおよび前記アプリケーションを書き込むステップと、
前記第2の仮想計算機に対応するマイグレーションされた他の仮想計算機のために前記第2のLPAR内の前記第3の専用メモリおよびプロセッサのシェアを割り振り、前記第2の共用メモリ内で前記通信キューへのアクセスを前記マイグレーションされた他の仮想計算機に許可するステップと、
を有する、方法。 - 実コンピュータ内の第1のロジカル・パーティション(「LPAR」)から第2のLPARに、第1の仮想計算機および通信キューをマイグレーションするためのシステムにおいて、マイグレーションの前に、前記第1の仮想計算機が前記第1の仮想計算機に専用の第1の専用メモリ内に前記第1の仮想計算機のオペレーティング・システムおよびアプリケーションを有し、マイグレーションの前に、前記通信キューが前記第1のLPAR内の前記第1の仮想計算機および第2の仮想計算機によって共用されアクセス可能な第1の共用メモリに常駐し、前記システムが、
前記第1の仮想計算機および前記第2の仮想計算機が前記第1のLPAR内の前記通信キューを更新するのを防止するために、前記第1のLPAR内で前記第1の仮想計算機および前記第2の仮想計算機を停止する手段と、
前記第1の仮想計算機および前記第2の仮想計算機が停止されている間に動作可能で、前記第2のLPARに前記第1の仮想計算機の前記オペレーティング・システムおよび前記アプリケーション、ならびに前記通信キューを伝達する、前記第1のLPAR内の手段と、前記第2のLPAR内の第2の専用メモリに前記第1の仮想計算機の前記オペレーティング・システムおよび前記アプリケーションを書き込む、前記第2のLPAR内の手段と、前記第2のLPAR内の第2の共用メモリに前記通信キューを書き込む、前記第2のLPAR内の手段と、
前記第1の仮想計算機に対応するマイグレーションされた仮想計算機のために前記第2のLPAR内の前記第2の専用メモリおよびプロセッサのシェアを割り振り、前記第2の共用メモリ内で前記通信キューへのアクセスを前記マイグレーションされた仮想計算機に許可する手段と、
前記第1の仮想計算機および前記第2の仮想計算機を停止する前に、前記通信キューに作業項目を供給する、前記第2の仮想計算機内の手段と、
前記第1の仮想計算機および前記第2の仮想計算機が停止されている間に動作可能で、前記第2のLPARに前記第2の仮想計算機のオペレーティング・システムおよびアプリケーションを伝達する、前記第1のLPAR内の手段と、前記第2のLPAR内の第3の専用メモリに前記第2の仮想計算機の前記オペレーティング・システムおよび前記アプリケーションを書き込む、前記第2のLPAR内の手段と、
前記第2の仮想計算機に対応するマイグレーションされた他の仮想計算機のために前記第2のLPAR内の前記第3の専用メモリおよびプロセッサのシェアを割り振り、前記第2の共用メモリ内で前記通信キューへのアクセスを前記マイグレーションされた他の仮想計算機に許可する手段と、
を有する、システム。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US10/843931 | 2004-05-11 | ||
US10/843,931 US7257811B2 (en) | 2004-05-11 | 2004-05-11 | System, method and program to migrate a virtual machine |
Publications (3)
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JP2005327279A JP2005327279A (ja) | 2005-11-24 |
JP2005327279A5 JP2005327279A5 (ja) | 2008-06-19 |
JP4769484B2 true JP4769484B2 (ja) | 2011-09-07 |
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Country Status (4)
Country | Link |
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US (2) | US7257811B2 (ja) |
JP (1) | JP4769484B2 (ja) |
CN (1) | CN1333341C (ja) |
TW (1) | TWI370974B (ja) |
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JP2005327279A (ja) | 2005-11-24 |
US7257811B2 (en) | 2007-08-14 |
TWI370974B (en) | 2012-08-21 |
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