JP4757715B2 - Game machine - Google Patents

Description

  The present invention saves the register value to the stack area when the power supply is cut off, and restores the saved register value when the power supply is restored to restore the control state to the state before the power cut off. The present invention relates to a gaming machine that performs processing.

  Conventionally, as this type of gaming machine, for example, there is a gaming machine disclosed in Patent Document 1 below. In this conventional gaming machine, the voltage of the VSL power supply, which is the power supply, is monitored by the power monitoring IC provided on the power supply board. When the voltage of the VSL power supply drops to a predetermined voltage, it is provided on the main board and the payout control board. A power-off signal is output to the non-maskable interrupt (NMI) terminal of each CPU. By the output of the power-off signal, a power-off process for saving stored contents such as a register in the backup RAM is performed on the main board and the payout control board. Further, access to the backup RAM is prohibited in the power-off process so that the stored contents stored in the backup RAM are not destroyed when the power supply voltage is lowered and the power supply is unstable.

In addition, the system reset to the CPU is canceled by stopping the output of the system reset signal output from the reset IC on condition that the power supply is restored and the voltage of the VSL power supply in the system reset circuit becomes a certain value or more. Then, the program is executed, and access to the backup RAM is permitted accordingly. At this time, a restoration process for restoring the value of the register saved in the stack area is performed, and the control by each CPU is restored to the state before the power-off.
Japanese Patent Application Laid-Open No. 2002-085655

  In the conventional gaming machine described above, since the voltage of the VSL power supply that enters the system reset state because the system reset signal is at a low level is lower than the voltage of the VSL power supply from which the power cut-off signal is output. A system reset signal is output from the reset IC to enter a system reset state after the power-off process is reliably performed and completed according to the signal output. When power is restored, the reset IC is turned on by a delay circuit such as a capacitor connected to the reset IC and the system reset signal is output to the main board. After a certain delay time has elapsed, the system reset signal is output. Since the activation of the main board is delayed and the effect control board and the payout control board that have been activated first receive and execute control commands from the main board without fail, recovery processing is performed when the power is restored. It is configured not to run.

  However, for example, immediately after the power supply is started, the system reset is released and the program starts. There is a possibility that a power-off signal is output to the NMI terminal due to an accident or noise, the voltage of the power supply is not sufficient, or an illegal action, etc., and the process at the time of power-off is executed.

  If an event such as that described above occurs while the system reset is released and access to the backup RAM is permitted, the power interruption process may be executed in a state where the register values in the stack area are not restored by the recovery process. is there. In this case, in the state where the saved register value is in the stack area, the register value is further stacked, and the stack capacity is exceeded (stack overflow). When this stack overflow occurs, the contents stored in the backup RAM are destroyed, and not only normal backup recovery is not performed, but also control of the gaming machine itself is destroyed.

The present invention has been made to solve such a problem, and includes a control means for controlling game processing, a storage means having a stack area in which a register value used for control of the control means is saved, and supply Even when the power supply from the power supply is cut off, the operating power supply to the storage means is supplied to maintain the stored contents of the storage means, and the voltage of the supply power supply is monitored. Power supply monitoring means for outputting a detection signal to the control means when the voltage drops, and when the detection signal is output from the power supply monitoring means, the control means saves the register value to the stack area of the storage means and Power-off processing for performing processing for prohibiting access to the storage means after storing the data necessary to restore the state when the detection signal is detected in the storage means The value of the register saved in the stack area of the storage means is restored to the register when a predetermined return condition is satisfied, and the control state detection signal is detected based on the data saved in the storage means In gaming machines that perform recovery processing to restore to the current state, the control means ensures that the power supply voltage has not dropped to a predetermined voltage after the power supply is started from the power supply and, have a permission control means for permitting access to the storage means, the gaming machine includes a sub CPU for controlling the control command from the control means, the sub-CPU is provided to the sub control board The sub-control board includes a device including a graphic accelerator, and the access permission control means supplies power from the supply power by the control means. After the start and control is started, the control means waits until a predetermined time elapses, and access to the storage means is permitted on the condition that the predetermined time elapses. the control unit performs access after the end initialization process of the sub-CPU to said memory means and Rukoto to start the control.

According to this configuration, after the power supply from the power supply is started and the control means starts control, the power supply voltage is ensured not to be lowered to the predetermined voltage even when the power-off process is executed. Until this is done, access to the storage means is not permitted. For this reason, in a state where the value of the register saved in the stack area of the storage means is not restored, multiple stacks may occur in which the register value is saved again for the stack area that already contains saved data. Can be prevented. As a result, stack overflow does not occur, and contents stored in the storage means are not destroyed. In addition, since the contents stored in the storage means cannot be rewritten at the start of power supply, if the power supply is restored after the power-off process is executed, it is saved in the storage means by the power-off process. Based on the stored data, the control state can be restored to the state when the detection signal is detected.
Further, the control unit waits for control until a predetermined time elapses. For this reason, since access to the storage means is permitted after securing the time until the voltage of the power supply does not drop to the predetermined voltage, access to the storage means in an unstable voltage state Is reliably prevented. In addition, when applied to a gaming machine having other control means that performs control according to a control command from the control means, it takes an initialization process of other control means that controls the device as the function of the device increases. Even if the time is long, the control means that outputs the control command can start the control by accessing the storage means after the initialization process of the other control means that takes a long time to complete the initialization process. It becomes. Therefore, the communication process between the control means is surely performed. In addition, since the activation of the control means can be delayed by control, the control start of the control means can be delayed beyond the limit of the performance of the delay circuit, and no hardware change is required. Therefore, the manufacturing cost of the gaming machine can be kept low.

  Further, according to the present invention, when the control means detects again the output of the power monitoring means in the power-off process, and when the detection signal is output, the power-off process is continued, and when the detection signal is not output. It returns to the process before a process at the time of power-off is performed, It is characterized by the above-mentioned.

  According to this configuration, it is possible to prevent a malfunction in which the detection signal is input to the control unit due to noise or the like and the process when the power is cut off is performed even though the voltage of the power supply is not reduced to a predetermined voltage. .

  According to the present invention, in a state where the value of the register saved in the stack area of the storage means has not been restored, there is a multiple stack in which the register value is saved again in the stack area where there is already saved data. It can be prevented from happening. As a result, stack overflow does not occur, and contents stored in the storage means are not destroyed. In addition, since the contents stored in the storage means cannot be rewritten at the start of power supply, if the power supply is restored after the power-off process is executed, it is saved in the storage means by the power-off process. The control state can be restored to the state when the detection signal is detected based on the data.

  Next, the best mode for carrying out the present invention will be described.

  FIG. 1 is a front view of a pachinko machine 1 according to the present embodiment.

  A game board 2 is provided in front of the pachinko machine 1 to allow the pachinko balls, which are game balls, to flow down. On the surface of the game board 2, a large number of nails for changing the flow direction of the pachinko balls flowing down are implanted. In the figure, only some nails are shown. An upper plate 3 is provided below the game board 2, and a launch handle 5 that is operated when a pachinko ball is driven into the game board 2 via the rail 4 is provided on the lower right side of the upper plate 3. Yes. Further, an upper frame decoration lamp 6 is provided above the game board 2.

  In the center of the game board 2 is provided a special symbol display device 10 composed of a liquid crystal display device that displays the special symbols as identification information in three rows. Above the special symbol display device 10 is provided a normal symbol display device 11 in which green LEDs (light emitting diodes) and red LEDs constituting the normal symbol are arranged side by side. On the left and right of the normal symbol display device 11, there are provided normal symbol start memorized number display units 13 made up of four LEDs. Also, a special symbol start memorized number display section 12 made up of four LEDs is provided on the lower side of the special symbol display device 10, and a passage gate that constitutes a normal symbol start passage on the left and right of the special symbol display device 10. 14 is provided. Also, below the special symbol display device 10, a normal electric accessory 15 constituting a special symbol start winning opening is provided.

  Above the upper plate 3, a ball lending button 7a, a return button 7b, a selection button 7c, and a decision button 7d are provided. The ball lending button 7a is operated when lending a pachinko ball within the range of the balance of the prepaid card inserted in the card unit 65 (see FIG. 2) provided side by side. The return button 7b is operated when the card inserted in the card unit 65 is returned. The selection button 7c is operated when an information item displayed on the special symbol display device 10 is selected. The determination button 7d is operated when determining an information item to be displayed on the special symbol display device 10.

  FIG. 2 is a block diagram illustrating a main configuration of an electronic circuit that controls the gaming operation of the pachinko machine 1 according to the present embodiment.

  The electronic circuit includes a main control circuit provided on the main control board 30, a sub control circuit provided on the sub control board 40, a launch control circuit provided on the launch control board 60, and a payout provided on the payout control board 61. It consists of a control circuit. The main control board 30 is a game control board that performs electrical control related to the progress of the pachinko game on the game board 2, and the sub control board 40 is based on control signals and game information from the main control board 30, and various effect devices It is an effect control board which performs electrical control of the game effect by. The launch control circuit of the launch control board 60 and the payout control circuit of the payout control board 61 control the launch of pachinko balls and the payout of prize balls and rental balls based on control signals and game information from the main control board 30.

  A main CPU 31 is mounted on the main control board 30 as control means for controlling game processing. The main CPU 31 has a main ROM (read only memory) 33 in which a program for controlling the game operation of the pachinko machine 1 is stored and a stack area in which register values used for the control of the main CPU 31 are saved. A main RAM (random access memory) 34 is incorporated as a storage means. As will be described later, when a power interruption detection signal is output from the power supply monitoring IC 71, the main CPU 31 saves the register value to the stack area of the main RAM 34, and the control state is detected when the power interruption detection signal is detected. After the data necessary for recovering to the above state is stored in the main RAM 34, a power-off process for performing a process for prohibiting access to the main RAM 34, and a stack area of the main RAM 34 when a predetermined return condition is satisfied. Then, the value of the register saved in is restored to the register, and the control process is restored based on the data saved in the main RAM 34 to restore the state when the power failure detection signal is detected.

  In the present embodiment, the above-described predetermined return condition for performing this recovery process is that the input voltage Vcc of a reset IC 32 (to be described later) exceeds 4.3 [V] and a predetermined time (3300 [msec]) elapses. After the reset signal R changes from the low level (L) to the high level (H) and the system reset state is released and the main CPU 31 starts control, access to the main RAM 34 is permitted (see S109 in FIG. 7). This is established when there is no input from the backup clear switch 19 (see S110), the power interruption detection flag is present (see S111), and the work area data in the main RAM 34 is not damaged (see S113).

  Further, the pachinko machine 1 is provided with a power supply circuit as a power supply for the power supply board 70. This power supply circuit inputs AC 24V and supplies DC power to each of the substrates 30, 40, 60, 61 and the like. A large capacity capacitor as a backup power source (not shown) is mounted on the power supply board 70, and this capacitor is connected to a backup terminal VBB (not shown) of the main CPU 31. This capacitor is charged when power is supplied, and when the power supply is cut off, 5 [V] power is supplied from the charged capacitor to the main CPU 31, so that the content stored in the main RAM 34 built in the main CPU 31 is stored. Retained. The main RAM 34 has a stack area. Register values are saved in the stack area, and the contents are retained even when the power supply is shut off.

  The power supply board 70 monitors the voltage of the power supply output from the power supply circuit, and when the voltage of the power supply drops to a predetermined voltage, the payout control of the main CPU 31 and the payout control board 61 of the main control board 30. A power monitoring IC 71 is mounted as power monitoring means for outputting a detection signal to the CPU 68. This power supply monitoring IC 71 is shown in FIG. 3, and has the VSB terminal and the RESET terminal. This RESET terminal is connected to each NMI terminal of the main CPU 31 of the main control board 30 and the payout control CPU 68 of the payout control board 61. When the voltage 33 [V] of the power supply generated based on AC24V falls below 17.2 [V], the power supply voltage V input to the VSB terminal of the power supply monitoring IC 71 is changed as shown in FIG. The voltage drops from 33 [V] to 17.2 [V]. The power supply monitoring IC 71 detects a drop in the power supply voltage 33 [V] due to the drop in the power supply voltage V input to the VSB terminal, and the voltage of the power interruption detection signal D as shown in FIG. The level is lowered from (H) to (L), and this is output to each NMI terminal as the detection signal. When the main CPU 31 and the payout control CPU 68 detect the falling edge of the power interruption detection signal D at the NMI terminal, the main CPU 31 and the payout control CPU 68 execute the above-described power-off process.

  Further, when the value of the power supply voltage V exceeds 17.2 [V] at the time of turning on or returning the power, charging of the capacitor connected to the CT terminal of the power supply monitoring IC 71 is started. When the capacitor is charged and the voltage applied to the CT terminal rises to a predetermined voltage, the power interruption detection signal D has a value of the power supply voltage V of 17.2 [V] as shown in FIG. The voltage level rises from (L) to (H) after a predetermined time delay. The main CPU 31 constitutes an access permission control means. After power supply is started from the power supply circuit and control is started, the falling edge of the power interruption detection signal D is input to the NMI terminal from the RESET terminal of the power supply monitoring IC 71. By monitoring whether or not the voltage 33 [V] of the power supply is not reduced to a predetermined voltage, that is, 17.2 [V], access to the main RAM 34 is permitted (FIG. 7, (See S108 and S109).

The reason why the threshold value for detecting a decrease in the voltage 33 [V] of the power supply is set to 17.2 [V] is as follows. That is, the voltage input to the main CPU 31 from switches 14s, 15s, and 16s, which will be described later, used for detecting the game ball is 12 [V], and the input voltage of 12 [V] is from (H) to (L). , The detection of the game ball by each of the switches 14s, 15s, 16s is detected. For this reason, if the voltage 33 [V] of the power supply falls below 12 [V], there is a problem of erroneously detecting that there is a switch input even though there is no switch input. This problem is prevented by setting the detected threshold V _SH to 17.2 [V] higher than 12 [V].

  As shown in FIG. 2, the main CPU 31 has an SRST terminal, and this SRST terminal is connected to the RESET terminal of the reset IC 32 mounted on the main control board 30.

  The reset IC 32 is shown in FIG. 5, the VCC terminal to which the input voltage Vcc shown in FIG. 6A is applied, the CK terminal to which the watchdog clear signal C shown in FIG. When the capacitor [μF] is charged, it has a TC terminal to which the watchdog timer signal T shown in FIG. 6C is input, and a RESET terminal for outputting the system reset signal R to the main CPU 31.

  The input voltage Vcc applied to the VCC terminal from the power supply circuit of the power supply substrate 70 is constantly supplied with a voltage of 5 [V] from the power supply circuit. When the input voltage Vcc applied to the VCC terminal exceeds 4.3 [V], the capacitor connected to the TC terminal starts to be charged as shown in FIG. The watchdog timer signal T applied to the TC terminal reaches a predetermined voltage when a delay time of 3300 [msec], which is 1000 times the capacitance 3.3 [μF] of the capacitor, has elapsed. When the watchdog timer signal T reaches the predetermined voltage, the reset IC 32 sets the system reset signal R output from the RESET terminal shown in FIG. When the voltage level change of the system reset signal R is applied to the SRST terminal of the main CPU 31, the system reset state of the main CPU 31 is released, and the main CPU 31 performs main processing (to be described later) according to a program stored in the main ROM 33 (see FIG. 7). Start controlling.

  The time 3300 [msec] until the system reset state is released is longer than the time until the power failure detection signal D shown in FIG. 4B rises from (L) to (H), and is normal. In the state, when the main processing by the main CPU 31 is executed, the power interruption detection signal D is reliably (H).

  In the present embodiment, the system reset release time of the main CPU 31 is 3300 [msec] as described above, whereas the system reset release time of the payout control CPU 68 in the payout control board 61 is set as short as 280 [msec]. Has been. For this reason, the command transmitted from the main CPU 31 is sent after the dispensing control board 61 is ready to receive the command, and is reliably received by the dispensing control board 61.

  When the control is started, the main CPU 31 outputs a watchdog clear signal C shown in FIG. 5B to the CK terminal of the reset IC 32 by a timer interrupt process (see FIG. 10) described later every 2 [msec]. To do. The voltage level of the watchdog clear signal C alternately changes between (H) and (L) every 2 [msec] by the timer interrupt process. The watchdog timer signal T is reset when the falling edge of the watchdog clear signal C input to the CK terminal changes, and its voltage level drops to zero. Then, the voltage level is raised again with the charge of the capacitor connected to the TC terminal again, but the reset is applied again by the watchdog clear signal C inputted next, and the voltage level is reduced to zero. Thereafter, the voltage level is increased again with the charging of the capacitor.

  Therefore, as long as the watchdog clear signal C is output to the CK terminal of the reset IC 32 by the main CPU 31, the watchdog timer signal T does not reach a predetermined voltage, so that the system reset is performed from the RESET terminal of the reset IC 32 to the SRST terminal of the main CPU 31. No signal is output. However, if the control of the main CPU 31 runs away for some reason, the watchdog clear signal C is not output from the main CPU 31 to the CK terminal of the reset IC 32. For this reason, the watchdog timer signal T reaches a predetermined voltage as shown in FIG. 6C, and the voltage level of the system reset signal R changes from (H) to (L) as shown in FIG. To do. When this voltage change of the system reset signal R is input to the SRST terminal of the main CPU 31, a system reset is applied to the main CPU 31 for a predetermined time, and the main CPU 31 returns the process to the beginning of the program and resumes the main process. That is, when the main CPU 31 runs out of control, the system is automatically reset and the processing of the main CPU 31 is resumed.

  Further, as shown in FIG. 2, the main CPU 31 has an I / O port (input / output port) 35 for transmitting / receiving signals to / from peripheral devices such as various switches and solenoids described later, and a sub-control of the sub-control board 40. A command output port 36 for outputting a command including a control signal and game information is connected to the circuit and the launch control circuit of the launch control board 60 and the payout control circuit of the payout control board 61. From the I / O port 35 and the command output port 36, control signals and game information sent from the main CPU 31 are serially transmitted to the peripheral devices and the control boards 40, 60, 61.

  Further, the main control board 30 is provided with a passing gate switch 14 s that is provided inside the passing gate 14 described above and detects that the pachinko ball passes through the passing gate 14, and a pachinko ball that has won the ordinary electric accessory 15. A start winning port switch 15s to be detected is connected. Further, a count switch 16 s that detects a pachinko ball that has won a prize winning opening 16 and a general prize opening switch 17 s that detects a pachinko ball that has won a prize in the general winning opening 17 are connected. Further, the main control board 30 is connected with an actuating winning port solenoid 15v for expanding the ball receiving port of the ordinary electric accessory 15 and a large winning port solenoid 16v for opening and closing the door of the large winning port 16 as actuators. . In addition, a backup clear switch board is connected to the main control board 30. A backup clear switch 19 is mounted on the backup clear switch board. The backup clear switch 19 is a backup that instructs to clear the backup contents of the main RAM 34 provided in the main CPU 31 constituting the main control circuit of the main control board 30 and the RAM (not shown) constituting the payout control circuit of the payout control board 61. Output a clear signal.

  The switches 14 s, 16 s, 17 s and the actuators 15 v, 16 v are connected to the main control board 30 via the panel relay board 80. When the switches 14s, 15s, 16s, and 17s detect pachinko balls, the detection signals are input to the main CPU 31 of the main control board 30, and the main CPU 31 controls the actuators 15v and 16v according to the input detection signals. Each drive is controlled.

  The sub control board 40 is connected to a special symbol display device (LCD) 10 and performs image display control for displaying an image on the LCD 10. In addition, the sub-control board 40 is connected to the lamp / LED 48 and the speaker 49, and the lighting control for controlling the light emission of the lamp / LED 48 according to the gaming state and the sound control for emitting the sound effect from the speaker 49. I do. The lamp / LED 48 represents a frame upper decoration lamp 6, a normal symbol display device 11, a special symbol start memory number display unit 12, a normal symbol start memory number display unit 13, and the like. A sub CPU 41, a program ROM 42, and a work RAM 43 are mounted on the sub control board 40. The sub CPU 41 interprets commands received from the main control board 30 via the relay board 37 and the command input port 47 and issues control commands to the image control circuit 44, the lamp control circuit 45, and the sound control circuit 46. The program ROM 42 stores a control program for the sub CPU 41 to control the operations of the LCD 10, the lamp / LED 48, and the speaker 49. The work RAM 43 serves as a temporary storage unit when the sub CPU 41 performs processing control according to the control program.

  The image control circuit 44 generates image data to be displayed on the LCD 10 in accordance with a control command from the sub CPU 41. The main CPU 31 performs a jackpot determination when a pachinko ball wins the normal electric accessory 15 and a start win occurs. The sub control circuit sequentially stops and displays the special symbols on the LCD 10 in a manner corresponding to the result of the big hit determination, and when the left symbol and the right symbol are stopped together and displayed in the same design, the special symbol is displayed on the LCD 10. Reach production is performed using production images. The lamp control circuit 45 controls the light emission of the lamp / LED 48 according to the gaming state of the pachinko machine 1 according to the drive signal from the sub CPU 41. The sound control circuit 46 controls the speaker 49 by a drive signal from the sub CPU 41.

  The program ROM 42 constitutes an effect storage means that stores a plurality of effect modes in a pattern, and stores the main CPU 31, main ROM 33, and main RAM 34 on the main control board 30, and the sub CPU 41, program ROM 42 on the sub control board 40, and The work RAM 43 constitutes an effect determining unit that determines an effect mode corresponding to the effect to be executed from the effect modes stored in the effect storage unit. The LCD 10, the image control circuit 44, the lamp / LED 48, the lamp control circuit 45, the speaker 49, and the audio control circuit 46 constitute an effect unit that executes an effect corresponding to the effect mode determined by the effect determination unit. Yes.

  A launch device 64 that is driven in response to an operation of the launch handle 5 is connected to the launch control board 60. The launch control circuit configured on the launch control board 60 drives and controls the launch device 64 according to the operation of the launch handle 5 by the player, and launches the pachinko ball to the game board 2.

  The payout control board 61 is mounted with a CPU 68 as a control means for controlling game processing related to payout control, and is connected to a payout device 63 for paying out winning balls and rental balls. The payout control circuit configured on the payout control board 61 drives and controls the payout device 63 in accordance with a payout command output from the main control board 30 via the frame relay board 62 according to various winnings, and pays out a prize ball. Let it come out. The payout control board 61 is connected to a card unit 65 for requesting the lending of a pachinko ball, and the card lending operation panel having the above-described ball lending button 7a and the return button 7b is connected to the card unit 65. 66 is connected. The card unit 65 communicates with the payout control circuit of the payout control board 61 according to the operation of the ball lending button 7a and the return button 7b. The payout control circuit drives and controls the payout device 63 in accordance with a signal output from the card unit 65 in response to a ball rental request for a pachinko ball, thereby paying out a ball.

  Next, the game operation process of the pachinko machine 1 according to the present embodiment will be described.

  FIG. 7 is a flowchart of main processing performed by the main CPU 31.

  In the main process, first, the watchdog timer initial setting process is performed by the main CPU 31 (see FIG. 7, step (hereinafter referred to as S) 101), and then the chip select initial setting process is performed (S102). Thereafter, the clear data (01H) is set in the watchdog clear signal C output from the main CPU 31 to the reset IC 32, and the voltage level of the watchdog clear signal C is set to (H) (S103). Next, a wait time (500 [msec]) is set in the main RAM 34 (S104). This wait time is for waiting for the substantial control of the main CPU 31 until the initial setting process in the sub-control board 40 is completed. Next, the voltage level of the watchdog clear signal C is inverted (S105), and then the watchdog clear signal C is output to the CK terminal of the reset IC 32 (S106).

  Next, it is determined whether or not the wait time of 500 [msec] set in S104 has elapsed (S105). If the set wait time has not elapsed, the processes of S105 to S107 are repeated. By this process, the voltage level of the watchdog clear signal C is alternately changed to (H), (L), (H), and (L), and is output to the CK terminal of the reset IC 32. This prevents an unexpected system reset from being applied to the main CPU 31. Further, by repeating the processes of S105 to S107, the main process by the main CPU 31 is made to wait until the wait time elapses.

  Next, if it is determined in S107 that the wait time has elapsed, it is determined whether or not the voltage level of the power interruption detection signal D input to the NMI terminal of the main CPU 31 is (H) ( S108). If the power interruption detection signal D is not (H), the process of S108 is repeated until the power interruption detection signal D becomes (H). When the main CPU 31 detects that the power interruption detection signal D has become (H), the main CPU 31 permits access to the main RAM 34 (S109).

  Next, it is determined whether or not there is an input from the backup clear switch 19 (S110). If there is no input from the backup clear switch 19, it is determined whether or not there is a power interruption detection flag (S111). The power interruption detection flag is set when a power interruption process (see FIG. 11) described later is normally performed. If there is a power failure detection flag, a work area damage check process of the main RAM 34 is performed (S112). Subsequently, whether or not the work area of the main RAM 34 has been damaged by this check process. Is discriminated (S113). If the work area of the main RAM 34 is not damaged, the stack pointer saved in the main RAM 34 in the power-off process described later (see FIG. 11) is restored (see S114 in FIG. 8).

  Next, a clear process of the switch input buffer is performed (S115), and then a CTC operation setting process for setting the operation of the internal clock that generates an interrupt at 2 [msec] is performed (S116). Next, an SIO operation setting process is performed for setting the serial in / out operation so that serial communication to the sub-control board 40 and the like can be performed normally (S117). Next, an LED output port refresh process is performed (S118), and a state notification LED (not shown) is turned on according to the gaming state before power-off (S119). Thereafter, a power failure recovery command is transmitted to the sub control board 40 (S120).

  Next, it is determined whether or not the interrupt flag is in a prohibited state (S121). If the interrupt flag is not in a prohibited state, the prohibited state is released and an interrupt is permitted (S122). When the interrupt flag is disabled in S121, or when the process of S122 ends, the value of the register that has been saved in the stack area of the main RAM 34 in the power-off process (see FIG. 11) described later is stored in the register. (S123). Thereafter, the processing of the main CPU 31 returns to the program address indicated by the value of the program counter corresponding to the value of the AF register included in the restored register, that is, the processing when the power interruption detection signal D is detected. Processing before the interruption is resumed.

  If the backup clear switch 19 is input in the determination of S110, or if there is no power interruption detection flag in the determination of S111, or if the work area of the main RAM 34 is damaged in the determination of S113, The stack pointer stored in the main RAM 34 is initialized (FIG. 9, S124), and the start address of the work area of the main RAM 34 is set (S125). Thereafter, clear data is set (S126), and it is determined whether or not the data at the address set in S125 has been cleared (S127). If the data at the set address has not been cleared, the processes of S124 to S126 are performed again. On the other hand, if the data at the set address has been cleared, the next address after the cleared address is set (S128). Then, it is determined whether or not the set address is the final address of the work area of the main RAM 34 (129). If it is not the final address, the processing of S126 to S128 is performed again, and all the work area of the main RAM 34 is cleared.

  When the clearing process of the work area of the main RAM 34 is finished in this way, next, the initialization process of data relating to special symbols is performed (S130). Subsequently, the above-described CTC operation setting process is performed (S131), and then the above-described SIO operation setting process is performed (S132). Then, an LED output port refresh process (S133) and a status notification LED clear data output process (S134) are performed, and an initialization command is transmitted to the sub-control board 40 (S135).

  Next, an interrupt is permitted (S136), and a timer interrupt process (see FIG. 10) described later becomes executable. Next, an interrupt prohibition process is performed so as to mask execution of the interrupt process (S137), the initial value random number is updated (S138), and an interrupt is permitted again (S139). Therefore, in the initial value random number update process (S138) of S138, the random number update process (FIG. 10, S4) by the timer interrupt process described later is not performed simultaneously.

  Next, it is determined whether or not the value of the system timer monitoring timer is 3 (S140). If the value of the system timer monitoring timer is not 3, the processes of S137 to S139 are repeated. On the other hand, when the value of the system timer monitoring timer becomes 3, that is, when 6 [msec], which is three times 2 [msec], has elapsed, the system timer monitoring timer is reset (S141). Subsequently, the main CPU 31 performs update processing of various timers such as a waiting time timer for synchronizing the main control circuit of the main control board 30 and the sub control circuit of the sub control board 40, and a prize opening opening time timer. Is executed (S142). Next, a special symbol control process is performed by the main CPU 31 (S143), and then a normal symbol control process is performed (S144).

  When each symbol control process of S143 and S144 is completed, a game information data generation process (S145) is subsequently performed, and then a port output process (S146) is performed. Then, a winning opening related command control process is performed in which the control of the big winning opening 16 and the general winning opening 17 is performed (S147), and then a storage / game state command control process is performed (S148). Next, command output control processing (S149) and payout processing (S150) are performed. When this process ends, the process returns to S137, and the processes of S137 to S150 are repeatedly executed.

  FIG. 10 is a flowchart showing the flow of the timer interrupt process performed by the main CPU 31 interrupting every 2 [msec] while the main process described above is executed.

  In this timer interrupt process, first, the main CPU 31 saves the value of each register when an interrupt occurs in the stack area of the main RAM 34 (see S1 in FIG. 10). Next, 1 is added to the system timer monitoring timer (S2), and then the voltage level of the watchdog clear signal C is inverted and output to the CK terminal of the reset IC 32 (S3). As a result, as shown in FIG. 6C, the watchdog timer signal T is reset before reaching a predetermined voltage.

  Next, a random number update process for updating the big hit determination random number value used for the big hit determination and the initial value random value described above is executed (S4). This random number for jackpot determination is referred to by the main CPU 31 when determining whether or not to perform a big hit game in the special symbol control process (see S143 in FIG. 9). Next, switch input processing is performed by the main CPU 31 (S5). In this switch input process, based on the detection signals output from the switches 14s to 17s described above, whether or not the pachinko ball has passed through the passage gate 14, the ordinary electric accessory 15, the big prize opening 16, and the general prize. A process for detecting whether or not a pachinko ball has won a prize in the mouth 17 or the like is performed.

  Thereafter, in order to return to the state at the time of the occurrence of the interrupt, a register return process for returning the register value saved in the stack area of the main RAM 34 to the register is performed (S6), and the timer interrupt process ends. . When this timer interrupt process ends, this subroutine ends, and the main process by the main CPU 31 is executed again from the state at the time of occurrence of the interrupt.

  Next, with reference to the flowchart of FIG. 11, the power-off process performed by the main CPU 31 will be described.

  As described above, the power-off process is executed when the power-off detection signal D input from the RESET terminal of the power supply monitoring IC 71 to the NMI terminal of the main CPU 31 falls from (H) to (L).

  In this power-off process, first, the value of the AF register indicating the value of the program counter at the time of power interruption is saved in the stack area of the main RAM 34 (see S11 in FIG. 11). Next, the detection of the power interruption detection signal D input to the NMI terminal performed in the above-described FIG. 7, S108 is performed again (S12). When the power interruption detection signal is (H), the value of the AF register saved in S11 is restored (S13), and the game process is resumed from the state immediately before the power interruption process occurs.

  If it is determined in S12 that the power interruption detection signal is (L), the values of registers other than the previously saved AF register are saved in the stack area of the main RAM 34 (S14), and an interrupt is generated. The state is reflected in the interrupt flag (S15), and the stack pointer is saved in the main RAM 34 (S16). Then, after data necessary for restoring the control state to the state when the power interruption detection signal D is detected is stored in the main RAM 34, a work area damage check data generation process is performed (S17). A disconnection detection flag is set (S18). Next, access to the main RAM 34 is prohibited (S19), and thereafter, a halt state in which the process continues to be waited while the access to the main RAM 34 is prohibited.

  In such a pachinko machine 1 according to the present embodiment, power supply monitoring is performed even when the power-off process shown in FIG. 11 is executed after power supply is started from the power supply circuit of the power supply board 70 and the main CPU 31 starts control. Until the power supply voltage V input to the VSB terminal of the IC 71 is not reduced to a predetermined voltage (17.2 [V]), the processing to the main RAM 34 is performed by the processing of FIGS. Access is not allowed. For this reason, in a state where the value of the register saved in the stack area of the main RAM 34 is not restored, a multiple stack in which the register value is saved again for the stack area where the saved data already exists may occur. Can be prevented. As a result, stack overflow does not occur, and the contents stored in the main RAM 34 are not destroyed. Further, at the start of power supply, the contents stored in the main RAM 34 are not rewritten until the processing of FIG. 7, S109 is performed. Therefore, when the power supply is restored after the power-off process is executed, the power-off detection signal D detects the control state based on the data stored in the main RAM 34 by the power-off process. It can be restored to the state when it was done.

  In the pachinko machine 1 according to the present embodiment, the main CPU 31 waits for control while the power failure detection signal D is output from the power monitoring IC 71, and the power failure detection signal D is not output from the power monitoring IC 71. By permitting access to the main RAM 34 (see S108 and S109 in FIG. 7), it is ensured that the power supply voltage V input to the VSB terminal of the power supply monitoring IC 71 has not dropped to 17.2 [V]. ing. For this reason, it is possible to reliably detect a state in which the power supply voltage V has not decreased to 17.2 [V]. For this reason, it is reliably prevented that the main RAM 34 is accessed in an unstable voltage state.

  Further, in the pachinko machine 1 according to the present embodiment, the main CPU 31 detects again the output of the power monitoring IC 71 in the power-off process (see S12 in FIG. 11), and when the power-off detection signal D is output, When the power interruption detection signal D is not output, the interruption process is continued, and the process returns to the process before the power interruption process is executed (see S13 in FIG. 11). For this reason, even though the power supply voltage V has not decreased to 17.2 [V], a malfunction in which the power failure detection signal D is input to the main CPU 31 due to noise or the like and the power failure processing is performed. Can be prevented.

  In addition, devices such as graphic accelerators used in the production control board have been advanced in functionality in recent years, and initial settings thereof can take a lot of time. For this reason, there is a limit in delaying the activation of the main CPU 31 in the main control board 30 with a hardware configuration such as a delay circuit using a capacitor or the like. Therefore, in the pachinko machine 1 according to the present embodiment, the main CPU 31 waits for control until a wait time of 500 [msec] elapses after power supply is started from the power supply circuit of the power supply board 70 and control is started. (Refer to FIG. 7, S107) By permitting access to the main RAM 34 on condition that the wait time has elapsed (see FIG. 7, S109), the power supply voltage V has not decreased to 17.2 [V]. Ensure state. For this reason, since the time until the power supply voltage V is not lowered to 17.2 [V] is secured by the wait time, access to the main RAM 34 is permitted, so that the power supply voltage V is in an unstable voltage state. Access to the main RAM 34 is reliably prevented. Further, when applied to a pachinko machine 1 having a sub CPU 41 that performs control according to a control command from the main CPU 31, a sub-control that controls the device as the graphic accelerator or the like on the sub-control board 40 becomes more sophisticated. Even if the time required for the initialization process of the CPU 41 becomes long, the main CPU 31 that outputs the control command accesses the main RAM 34 after the initialization process of the sub CPU 41 that takes a long time for the initialization process is completed, and performs control. It becomes possible to start. Therefore, the communication process between the main CPU 31 and the sub CPU 41 is surely performed. In addition, since the activation of the main CPU 31 can be delayed by control, the start of control of the main CPU 31 can be delayed beyond the limit of the performance of the delay circuit, and no hardware change is required. Therefore, the manufacturing cost of the pachinko machine 1 can be kept low.

  In this embodiment, the power supply voltage V is reduced to 17.2 [V] by setting a wait time in S107 or S108 in FIG. 7 or detecting the (H) input of the power interruption detection signal D. In this case, the power supply voltage V is reduced to 17.2 [V] when access to the main RAM 34 is permitted. It is sufficient if the configuration is such that no state is ensured. In this embodiment, the wait time is set to 500 [msec] in S104. However, the present invention is not limited to this setting, and the wait time can be set arbitrarily.

  In the power-off process (see FIG. 11), the reconfirmation process (S12 in FIG. 11) of the power interruption detection signal D is performed. However, this process need not necessarily be executed.

  In addition, the reset IC 32 having the watchdog function is mounted on the main control board 30, but it may be mounted on the power supply board 70, and the power supply voltage V is 4.3 [ It is good also as a structure provided only with the function which monitors that it falls to V].

  Further, the execution start time of the main processing is configured to be delayed by 3300 [msec] by the watchdog timer signal T (see FIG. 6C), but not only the watchdog circuit but also a delay circuit such as a gate circuit is further provided. May be implemented. Alternatively, only a delay circuit such as a gate circuit may be mounted to delay the execution start time of the main process.

  In the above embodiment, the case where the gaming machine according to the present invention is applied to the pachinko machine 1 has been described. However, when the power supply is cut off, the register value is saved to the stack area, and when the power supply is restored, the value is saved. The present invention can also be applied to other gaming machines such as a slot machine that performs processing to restore the value of the registered register and restore the control state to the state before power-off. Even when the present invention is applied to such a gaming machine, the same effects as the above-described embodiment can be obtained.

It is a front view which shows the external appearance of the pachinko machine by one Embodiment of this invention. It is a block diagram which shows the main structures of the electronic circuit which carries out process control of the game operation | movement of the pachinko machine shown in FIG. It is a figure which shows the input / output terminal of power supply monitoring IC. It is the figure which showed operation | movement of the power supply monitoring IC. It is a figure which shows the input / output terminal of reset IC. It is the figure which showed the operation | movement of reset IC. It is a 1st flowchart of the main process of the pachinko machine shown in FIG. It is a 2nd flowchart of the main process of the pachinko machine shown in FIG. It is a 3rd flowchart of the main process of the pachinko machine shown in FIG. It is a flowchart of the timer interruption process of the pachinko machine shown in FIG. It is a flowchart of the power-off process of the pachinko machine shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Pachinko machine 2 ... Game board 10 ... Special symbol display device 11 ... Normal symbol display device 15 ... Normal electric accessory (special symbol start winning opening)
30 ... main control board 31 ... main CPU (central processing unit)
32 ... Reset IC
33 ... Main ROM (read only memory)
34 ... Main RAM (read-write memory)
40 ... Sub-control board 61 ... Discharge control board 70 ... Power supply board 71 ... Power supply monitoring IC

Claims (2)

Control means for controlling game processing;
A storage unit having a stack area in which a register value used for control of the control unit is saved;
A backup power supply for supplying the operating power to the storage means and retaining the storage contents of the storage means even when the power supply from the supply power supply is interrupted;
Power supply monitoring means for monitoring the voltage of the power supply and outputting a detection signal to the control means when the voltage of the power supply drops to a predetermined voltage;
The control means includes
When the detection signal is output from the power supply monitoring unit, the value of the register is saved in the stack area of the storage unit, and the data necessary for restoring the control state to the state when the detection signal is detected Power off processing for performing processing for prohibiting access to the storage means after storing the storage means in the storage means;
The value of the register saved in the stack area of the storage means when the predetermined return condition is satisfied is returned to the register, and the control state is detected based on the data saved in the storage means In a gaming machine that performs recovery processing to restore the state when the signal was detected,
The control means have a permission control means for permitting access to pre-term memory unit,
The gaming machine has a sub CPU that performs control according to a control command from a control means,
The sub CPU is provided on a sub control board, and the sub control board includes a device including a graphic accelerator,
The access permission control means waits for the control means to wait until a predetermined time elapses after the control means starts supplying power from the power supply and starts control, and the predetermined time elapsed to allow access to the storage means on condition that, thereby, the control means performs access after completing initialization process of the sub-CPU to said memory means, to start the control Rukoto A gaming machine characterized by The control means detects again the output of the power monitoring means in the power-off process, and continues the power-off process when the detection signal is output, and when the detection signal is not output. The gaming machine according to claim 1, wherein the game machine returns to the process before the power-off process is executed.

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