JP4754715B2 - Clock signal selective output method and selective output circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a clock signal selection output method and a selection output circuit, and more specifically, even when there is a difference in the input timing of two or more clock signals having different frequencies, a high or low frequency is desired. The present invention relates to a selective output method and a selective output circuit for a clock signal for automatically selecting and outputting a clock signal.
[0002]
[Prior art]
In various electronic circuits, a clock signal is often used as a base of operation, and a high-frequency clock signal and a low-frequency clock signal are selectively switched as appropriate depending on the application. Such switching of the clock signal is conventionally performed manually by hand or controlled by software.
[0003]
For example, a DRAM (memory) in which data is stored holds data stored by the refresh process, but a predetermined clock signal needs to be supplied to the memory controller of the DRAM for the refresh process. The clock signal for the refresh process may be a low frequency clock signal, but in order to improve the access speed to the DRAM, it is necessary to supply a higher frequency clock signal to the memory controller. On the other hand, when the clock frequency of the clock signal is increased, power consumption increases and there are problems such as heat generation. Therefore, when the clock signal is simply used for refresh processing, it is sufficient to supply a low-frequency clock signal.
[0004]
Therefore, a low-frequency clock signal is supplied while the peripheral device is not operating, and a high-frequency clock is supplied when the peripheral device is up and operating for accessing the DRAM. Switching by an operator manually or automatically by software of the peripheral device is performed.
[0005]
[Problems to be solved by the invention]
However, the method of manual switching by the operator may be erroneously selected due to the operator's misunderstanding or the like, and reliable switching may not be performed.
[0006]
In addition, switching by software cannot be performed appropriately when the device incorporating the software is not operating. For example, when the device is built in a peripheral device as described above, the peripheral device When the power is turned off, the software processing is stopped, and the clock signal cannot be switched to the original slow frequency, and the data stored in the DRAM is lost.
[0007]
As described above, in various electronic devices that are operated by appropriately switching the clock signal, it is a very important issue to appropriately switch the clock signal. In particular, when a clock signal having a desired frequency is input later, another clock signal that has already been input is output before the desired clock signal is input. After the clock signal is input, it is desired that the clock signal is appropriately switched and output.
[0008]
In view of the above circumstances, an object of the present invention is to appropriately select and output a clock signal having a desired frequency, either high or low, even when there is a difference in input timing of two or more clock signals having different frequencies. Another object is to provide a selection output circuit and a selection output circuit for a clock signal.
[0009]
[Means for Solving the Problems]
In the first aspect, the present invention separately counts the number of clocks of two or more clock signals input at different frequencies, and according to the counted number of clocks, among the two or more clock signals, There is provided a method for selecting and outputting a clock signal, wherein a clock signal having the highest clock frequency or a clock signal having the lowest clock frequency is selected and output.
[0010]
According to the clock signal selection output method of the present invention configured as described above, the clock frequency level can be easily determined by counting the number of clocks of the input clock signal separately. Based on the counted number of clocks, the clock signal with the highest clock frequency or the clock signal with the lowest clock frequency is selected and output, so that the clock signal with the highest frequency or the clock with the lowest frequency that is currently input is output. The signal can be reliably selected and output.
[0011]
Note that when the clock signal having the lowest frequency is selected and output from among the input clock signals, the operation speed of the external device can be suppressed to save energy. For example, a notebook personal computer, a PDA, or the like can be used. Helps extend operating time. On the other hand, when the clock signal having the highest frequency among the input clock signals is selectively output, it is useful for increasing the operation speed of the external device and improving the processing speed.
[0012]
In a second aspect, the present invention separately counts the number of clocks of two or more clock signals input at different frequencies, and among the two or more clock signals, a count value of the number of clocks is preset. A clock signal selection is characterized in that the clock signal on the side that has reached the predetermined value the fastest is selected and output, and when any count value reaches the predetermined value, all count values are reset. Provide an output method.
[0013]
According to the clock signal selection and output method of the present invention thus configured, the count value for a clock signal having a high clock frequency is obtained by counting the number of clocks of the input clock signal separately. Since the predetermined value is reached faster than the count value for the low clock signal, the clock signal on the side where the count value has reached the predetermined value the fastest is the highest frequency clock signal among the input clock signals. By selecting and outputting the clock signal, it is possible to reliably select and output the clock signal having the highest frequency inputted at that time.
[0014]
Moreover, once the count value for the clock signal with the highest frequency reaches a predetermined value, all counts are reset, and counting of the number of clocks starts again from the beginning. If it is input later, the high-frequency clock signal input after that is selected and output at least once after reset. Therefore, the highest-frequency clock signal is always output among the input clock signals. Can do.
[0015]
In addition, a stable clock signal can be output by setting the predetermined value as a value corresponding to the time required for the clock frequency of the clock signal to become stable after being input.
[0016]
In a third aspect, the present invention provides the clock signal according to the second aspect, wherein at least one of the second and lower clock signals from the higher clock frequency is always input. Provides a selective output method.
[0017]
According to the clock signal selection output method of the present invention configured as described above, at least one of the second and lower clock signals from the highest clock frequency is always input, so that at least the clock signal is input. Since the clock signal having the highest frequency among the existing clock signals is output, the output of any one of the clock signals can always be maintained.
[0018]
According to a fourth aspect, the present invention provides a method for selecting and outputting a clock signal according to the second or third aspect of the invention, characterized in that the clock signal to be inputted changes in its clock frequency. provide.
[0019]
According to the clock signal selection and output method of the present invention thus configured, even if the clock frequency changes, the clock signal having the highest frequency can be output at that time.
[0020]
In a fifth aspect, the present invention relates to two or more counters that separately count the number of clocks of two or more clock signals input at different frequencies, and the number of clocks counted by the counter according to the number of clocks counted by the counter. A clock signal selection output circuit comprising: a selector that selects and outputs a clock signal having the highest clock frequency or a clock signal having the lowest clock frequency among the above clock signals.
[0021]
According to the clock signal selection output circuit of the present invention configured as described above, each counter can easily determine the level of the clock frequency by counting the number of clocks of the input clock signal separately. Therefore, based on the counted number of clocks, the selector selects and outputs the clock signal having the highest clock frequency or the clock signal having the lowest clock frequency. The clock signal or the clock signal having the lowest frequency can be reliably selected and output.
[0022]
Note that when the clock signal having the lowest frequency is selected and output from among the input clock signals, the operation speed of the external device can be suppressed to save energy. For example, a notebook personal computer, a PDA, or the like can be used. Helps extend operating time. On the other hand, when the clock signal having the highest frequency among the input clock signals is selectively output, it is useful for increasing the operation speed of the external device and improving the processing speed.
[0023]
In a sixth aspect, the present invention relates to two or more counters that individually count the number of clocks of two or more clock signals that are input at different frequencies, and a count value of the counter among the two or more clock signals. The selector that selects and outputs the clock signal input to the counter on the side that has reached the preset predetermined value the fastest, and when the count value of any counter reaches the predetermined value, There is provided a clock signal selection output circuit comprising a reset circuit for resetting a count value.
[0024]
According to the clock signal selection output circuit of the present invention configured as described above, each counter counts the number of clocks of the input clock signal, so that the count value for the clock signal having a high clock frequency is obtained. Since the clock signal having a lower clock frequency reaches the predetermined value faster than the count value, the clock signal on the side where the count value has reached the predetermined value the fastest is the clock signal having the highest frequency among the input clock signals. The selector selects and outputs the clock signal having the highest frequency, so that the clock signal having the highest frequency inputted at that time can be reliably selected and output.
[0025]
Moreover, once the count value for the clock signal with the highest frequency reaches a predetermined value, the reset circuit resets all counts and the counter starts counting the number of clocks from the beginning again. If a high-frequency clock signal is input later, the high-frequency clock signal input after that is selected and output at least once after reset, so the clock with the highest frequency among the input clock signals A signal can always be output.
[0026]
In addition, a stable clock signal can be output by setting the predetermined value as a value corresponding to the time required for the clock frequency of the clock signal to become stable after being input.
[0027]
In a seventh aspect, the present invention is the invention according to the sixth aspect, further comprising two or more buffers to which two or more clock signals are separately input, wherein the selector reaches the predetermined value fastest There is provided a clock signal selection output circuit characterized by switching a buffer to which a clock signal inputted to a counter on the side is inputted so that the inputted clock signal is outputted.
[0028]
According to the clock signal selection output circuit of the present invention configured as described above, since the output of the clock signal is switched using the buffer, this switching can be performed instantaneously and reliably.
[0029]
In an eighth aspect, in the present invention based on the sixth or seventh aspect, at least one of the two or more counters includes one of the second and lower clock signals from the highest clock frequency. A clock signal selection output circuit characterized by being always input is provided.
[0030]
According to the clock signal selection output circuit of the present invention configured as described above, at least one of the second and lower clock signals from the highest clock frequency is always input, so that at least the clock signal is input. Since the clock signal having the highest frequency among the existing clock signals is output, the output of any one of the clock signals can always be maintained.
[0031]
In a ninth aspect, the present invention provides the clock signal selection output circuit according to any of the fifth to eighth aspects of the invention, wherein the input clock signal has a clock frequency that changes. provide.
[0032]
According to the clock signal selection output circuit of the present invention configured as described above, even if the clock frequency changes, the clock signal having the highest frequency can be output at that time.
[0033]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of a clock signal selection output method and a selection output circuit according to the present invention will be described with reference to the drawings. Each invention is not limited by these embodiments.
[0034]
Here, FIG. 1 is a diagram showing an embodiment of a clock signal selection output circuit according to the present invention, and FIG. 2 is a flowchart showing the operation of the circuit shown in FIG. The clock signal selection output circuit 10 shown in the figure includes two counters 11a and 11b and buffers 12a and 12b for counting the number of clocks of the two input clock signals Sin1 and Sin2, respectively, and these two clock signals Sin1 and Sin2. Among them, the clock signal Sin1 or Sin2 input to the counter 11a or 11b on the side where the count value of the counters 11a and 11b has reached the preset predetermined value N fastest is selected, and the selected clock signal Sin1 is selected. Alternatively, the selector 13 that switches the buffer 12a or 12b to which the Sin2 is input to output the input clock signal Sin1 or Sin2 and the count value of one of the counters 11a or 11b has reached a predetermined value N When all counters 11a and 11b are reset to zero That a reset circuit 14, a configuration in which a.
[0035]
Here, the counters 11a and 11b output a high level (H level) signal when the count value reaches a predetermined value N, and output a low level (L level) signal before the count value reaches the predetermined value N. Is done. Further, the count value is reset to zero by the L level signal output from the reset circuit 14.
[0036]
The reset circuit 14 is a logic gate NOR circuit. When an H level signal is input from at least one of the counters 11a and 11b (when the count value reaches a predetermined value N), an L level signal is input. While the L level signal is input from both (during counting before the count value reaches the predetermined value N), the H level signal is output.
[0037]
The selector 13 outputs an L level signal to the buffer 12a or 12b on the side connected to the counter 11a or 11b on the side to which the H level signal is input, and to the other buffer 12b or 12a. An H level signal is output.
[0038]
The clock signals Sin1 and Sin2 are input to the buffers 12a and 12b, respectively. However, when an H level signal is input from the selector 13, the clock signals Sin1 and Sin2 are not output and an L level signal is output. Is input, the clock signals Sin1 and Sin2 are output.
[0039]
Next, the operation of the clock signal selection output circuit 10 will be described with reference to a flowchart (see FIG. 2). The clock signal Sin1 is a signal having a clock frequency of 20 MHz and is always input. On the other hand, the clock signal Sin2 is a signal having a clock frequency of 40 MHz, and is not input at the beginning but is input later.
[0040]
First, the counters 11a and 11b operate to count the number of clocks of the clock signals Sin1 and Sin2 input to the counters 11a and 11b, respectively (step 1 (S1)). Here, since only the clock signal Sin1 is input, the count value of the counter 11a increases as time passes, but the count value of the counter 11b remains zero even if time passes. In parallel, the clock signal Sin1 is input to the buffer 12a (S2).
[0041]
The selector 13 waits until the count value of the counter 11a or the counter 11b reaches a predetermined value N and an H level signal is input as time passes (S3, S4). Initially, since only the clock signal Sin1 is input, the count value of the counter 11a reaches a predetermined value N with the passage of time, and an H level signal is output. The H level signal output from the counter 11a Is input to the selector 13.
[0042]
Accordingly, the selector 13 selects the buffer 12a on the side corresponding to the counter 11a, and outputs an L level signal to the buffer 12a (S5). The selector 13 initially outputs an H level signal to both the buffers 12a and 12b. Therefore, even when an L level signal is output to the buffer 12a, the selector 13 outputs an H level signal to the buffer 12b. The signal is maintained as it is.
[0043]
The buffer 12a to which the L level signal is input from the selector 13 outputs the input clock signal Sin1, while the buffer 12b in which the H level signal is maintained does not output a signal. The clock signal selection output circuit 10 outputs the clock signal Sin1 having a clock frequency of 20 MHz as the output clock signal Sout (S7).
[0044]
The H level signal output from the counter 11a is input to the reset circuit 14. The reset circuit 14 outputs an L level signal to both the counters 11a and 11b in response to the input of the H level signal. The counters 11a and 11b reset their count values to zero (S6). While only the clock signal Sin1 is being input, the processing of Step 1 (S1) to Step 7 (S7) described above is repeated, and the output of the clock signal Sin1 is continued.
[0045]
Next, the operation when the clock signal Sin2 having a clock frequency of 40 MHz is input from the middle will be described.
[0046]
Before the clock signal Sin2 is input, the clock signal Sin1 is output as the output clock signal Sout by the above-described operation. However, when the clock signal Sin2 is input, the count value of the counter 11b also increases with time. The counter 11b to which the clock signal Sin2 having a clock frequency higher than that of the clock signal Sin1 is input precedes, and the count value reaches the predetermined value N. The clock signals Sin1 and Sin2 are input to the buffers 12a and 12b, respectively (S2).
[0047]
The selector 13 waits until the count value of the counter 11a or the counter 11b reaches a predetermined value N and an H level signal is input as time elapses (S3, S4), but the count value of the counter 11b is predetermined. The value N is reached and an H level signal is output, and the H level signal output from the counter 11 b is input to the selector 13. Accordingly, the selector 13 selects the buffer 12b on the side corresponding to the counter 11b, and outputs an L level signal to the buffer 12b (S8).
[0048]
The buffer 12b to which the L level signal is input from the selector 13 outputs the input clock signal Sin2, while the buffer 12a does not output the signal. Therefore, the clock signal selection output circuit 10 does not output the clock signal Sin2. A clock signal Sin2 having a clock frequency of 40 MHz is output as the output clock signal Sout (S9).
[0049]
The H level signal output from the counter 11b is input to the reset circuit 14, and the reset circuit 14 outputs an L level signal to both counters 11a and 11b in response to the input of the H level signal. The counters 11a and 11b reset their count values to zero (S6).
[0050]
As a result, while both the clock signals Sin1 and Sin2 are being input, the above-described steps 1 (S1) to 4 (S4), 6 (S6), 8 (S8) to 9 (S9) are performed. The process is repeated and the output of the clock signal Sin2 is continued. Further, when the input of the clock signal Sin2 is stopped halfway, the process returns to the process before the clock signal Sin2 is input, and the output of the clock signal Sin1 is continued.
[0051]
Thus, according to the clock signal selection output circuit 10 of the present embodiment, the counters 11a and 11b count the number of clocks of the input clock signals Sin1 and Sin2, respectively, so that the selector 13 Of the input clock signals Sin1 and Sin2, the clock signal Sin2 having a higher clock frequency (when Sin2 is input) or the clock signal Sin1 (when Sin2 is not input) is always selected and output. Therefore, while maintaining the output of the output clock signal Sout, the clock signal Sin2 having the highest frequency input at that time (when Sin2 is input) or the clock signal Sin1 (when Sin2 is not input) is ensured. Can be selected and output.
[0052]
Moreover, once the count value for the clock signal with the highest frequency reaches the predetermined value N, the reset circuit 14 resets the count values of both counters 11a and 11b to zero, and the counters 11a and 11b again In order to start counting the number of clocks from the beginning, when a higher frequency clock signal Sin2 is input later, after the reset is performed at least once, the higher frequency clock signal Sin2 input thereafter is selectively output. Therefore, the clock signal having the highest frequency among the input clock signals can always be output.
[0053]
In the embodiment described above, the clock signal Sin2 is input halfway, but the count value N is set as a value corresponding to the time required for the clock frequency of the clock signal Sin2 to be stabilized. Therefore, a stable output clock signal Sout can be obtained.
[0054]
The clock signal Sin2 has been described as being input midway. However, the clock signal Sin2 may be a signal that is input from the beginning in the same manner as the clock signal Sin1, and the clock frequency is switched between 10 MHz and 40 MHz in the middle. In this case, when the clock signal Sin2 is 10 MHz, the 20 MHz clock signal Sin1 is output as the output clock signal Sout, and after the clock signal Sin2 is switched to 40 MHz, the clock signal Sin2 is output as the output clock signal Sout. .
[0055]
FIG. 3 is a diagram showing another embodiment of the clock signal selection output circuit of the present invention. In the illustrated clock signal selection output circuit 10, a counter 11c to which another clock signal Sin3 is input is further connected in parallel to the counters 11a and 11b in addition to the clock signal selection output circuit shown in FIG. 12c is connected in parallel to the buffers 12a and 12b, and the selector 13 sets the count values of the counters 11a, 11b, and 11c among the three clock signals Sin1, Sin2, and Sin3 to the preset predetermined value N. The clock signal Sin1, Sin2 or Sin3 input to the counter 11a, 11b or 11c on the side that has reached fast is selected and the selected clock signal Sin1, Sin2 or Sin3 is input to the buffer 12a, 12b or 12c. So that the input clock signal Sin1, Sin2 or Sin3 is output. Rikae, reset circuit 14, the count value of either counter 11a or 11b is formed as to reset all when it reaches a predetermined value N of the counter 11a, 11b, the count value of 11c to zero.
[0056]
In other words, the embodiment described above is a clock signal selection output circuit in which one clock signal Sin1 is always input and another clock signal Sin2 is input or input is stopped. In the form, one clock signal Sin1 is always input, and the other two clock signals Sin2 (clock frequency: Sin1 <Sin2) and Sin3 (clock frequency: Sin2 <Sin3) different from the clock signal Sin1. Is a clock signal selection output circuit that is input separately or stopped for each input.
[0057]
According to the clock signal selection output circuit 10 configured as described above, during the period in which only the clock signal Sin1 is input, the clock signal Sin1 is output as the output clock signal Sout, and Sin2 is input without input of Sin3. During this period, the clock signal Sin2 is output as the output clock signal Sout, and during the period during which Sin3 is input, the clock signal Sin3 is output as the output clock signal Sout. While maintaining, it is possible to reliably select and output the clock signal having the highest frequency inputted at that time.
[0058]
【The invention's effect】
According to the clock signal selection output method and clock signal selection output circuit of the present invention, the following effects can be obtained.
[0059]
First, since the number of clocks of the input clock signal is counted separately, the level of the clock frequency can be easily determined. Therefore, based on the counted number of clocks, the clock having the highest clock frequency is used. By selecting and outputting the clock signal having the lowest signal or clock frequency, it is possible to reliably select and output the clock signal having the highest frequency or the clock signal having the lowest frequency that is input at that time.
[0060]
Second, by counting the number of clocks of the input clock signal separately, the count value for a clock signal with a high clock frequency reaches a predetermined value faster than the count value for a clock signal with a low clock frequency. The clock signal on the side where the count value reaches the predetermined value the fastest is the clock signal with the highest frequency among the input clock signals. By selecting and outputting this clock signal, it is input at that time. It is possible to reliably select and output the clock signal having the highest frequency.
[0061]
Moreover, once the count value for the clock signal with the highest frequency reaches a predetermined value, all counts are reset, and counting of the number of clocks starts again from the beginning. If it is input later, the high-frequency clock signal input after that is selected and output at least once after reset. Therefore, the highest-frequency clock signal is always output among the input clock signals. Can do.
[0062]
In addition, a stable clock signal can be output by setting the predetermined value as a value corresponding to the time required for the clock frequency of the clock signal to become stable after being input.
[0063]
Third, since at least one of the second and lower clock signals having the highest clock frequency is always input, a clock signal having the highest frequency among the input clock signals is output. Therefore, the output of any clock signal can always be maintained.
[Brief description of the drawings]
FIG. 1 is a diagram showing a clock signal selection output circuit according to an embodiment of the present invention;
FIG. 2 is a flowchart showing an operation of the clock signal selection output circuit shown in FIG. 1;
FIG. 3 is a diagram showing a clock signal selection output circuit according to another embodiment of the present invention;
[Explanation of symbols]
10 Clock signal selection output circuit
11a, 11b counter
12a, 12b buffer
13 Selector
14 Reset circuit
Sin1, Sin2 Input clock signal
Sout Output clock signal

Claims (7)

The number of clocks of two or more clock signals input at different frequencies is counted separately, and the count value of the number of clocks of the two or more clock signals is preset according to the counted number of clocks. A clock signal selection output method that selects and outputs the clock signal that has reached the predetermined value the fastest, and resets all count values when any of the count values reaches the predetermined value. ,
The first clock signal of the two or more clock signals is input after the second clock signal,
The clock signal selective output method, wherein the predetermined value is set as a value corresponding to a time required for the clock frequency of the first clock signal to be stabilized.   2. The method for selecting and outputting a clock signal according to claim 1, wherein at least one of the second and lower clock signals from the higher clock frequency is always input.   The clock signal selection output method according to claim 1 or 2, wherein the clock frequency of the input clock signal changes. Two or more counters each counting the number of clocks of two or more clock signals input at different frequencies;
According to the number of clocks counted by the counter, the clock signal input to the counter on the side where the count value of the counter has reached the preset predetermined value the fastest among the two or more clock signals is selected. A selector,
A reset circuit that resets the count values of all the counters when the count value of any one of the two or more counters reaches the predetermined value;
With
The first clock signal of the two or more clock signals is input after the second clock signal,
The clock signal selection output circuit, wherein the predetermined value is set as a value corresponding to a time required for the clock frequency of the first clock signal to stabilize.   The buffer further includes two or more buffers to which the two or more clock signals are individually input, and the selector has a clock signal input to the counter that has reached the predetermined value the fastest, 5. The clock signal selection output circuit according to claim 4, wherein switching is performed so that an input clock signal is output.   6. The clock signal according to claim 4, wherein at least one of the two or more counters is constantly input with one of the second and lower clock signals from the highest clock frequency. Selective output circuit.   7. The clock signal selection output circuit according to claim 4, wherein the input clock signal has a clock frequency that changes.

Images