JPH06204990A - Clock generation circuit with redundant constitution - Google Patents

Abstract

PURPOSE:To make the phases of clocks coincide at all times and to eliminate the phase fluctuation of output signals at the time of switching between an existent counter and a reserve counter by simultaneously resetting the counters of reference clock signals inside plural clock generation circuits by the output of a block during selecting the existent counter. CONSTITUTION:When a switching control signal by which the clock generation circuit 1 is selected is at an H level, the counter 4 is operated based on the reference clock signal and when a count value becomes a prescribed decoding value, decoding output is generated. At a selector 8, when its own block is selected, the output of a decoder 5 is selected and the counter 4 is reset. In such a manner, while repeating counting-up and resetting, the counter shapes the decoded output to rectangular waves whose pulse duty cycle is 50% to output as clock signals. On the other hand, at an unselected block, when the switching control signal is at an L level, first and second 3-state gates are in an OFF state in the clock generation circuit 2, clock signals are not outputted and clear output from the other selected circuit only is supplied through the selector 8 to the reset terminal of the counter 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generation circuit, and more particularly to a switching control circuit in a clock generation device having a working / standby redundant configuration.

[0002]

2. Description of the Related Art Conventionally, in an important communication system, a plurality of identical functional blocks are provided to improve reliability,
When the working block fails, the operation is continued by switching to the spare block.
In particular, a clock signal generator for network synchronization or the like in a transmission system is an important block and often has a redundant configuration.

FIG. 3 is a block diagram showing an example of a conventional clock generating device having a redundant configuration. This device includes clock generating circuits 1 and 2, and one circuit 1 is switched with a reference clock signal SC. The control signal CONT and the other circuit 2 are supplied with the reference clock signal SC and the switching control signal logically inverted by the inverter 3, respectively.
Both clock outputs are wired-ORed and supplied to necessary blocks. One of the outputs of these two clock generation circuits is selected by the state value of the switching control signal CONT.

FIG. 4 is a block diagram showing an internal configuration example of the clock generation circuit. The counter 4 counts the number of pulses of the reference clock, the decoder 5 which decodes the counter output, and the decoder output. Waveform shaping circuit 6 for shaping the waveform
And 3 state gates 7, and the switching control signal C
The ON / OFF of the 3-state gate 7 is controlled by the ONT, and the counter 4 is reset by the output of the decoder 5. According to this structure, a pulse is generated from the decoder 5 every time the reference clock SC is counted by a predetermined number, and is output as a clock signal via the waveform shaping circuit 6 and the 3-state gate 7. Each time the decoder output is generated, the counter 4 is reset and new counting is repeated. Therefore, the generated clock is the reference clock signal divided based on the set values of the counter and the decoder.

Two sets of clock generation circuits configured as described above are provided, and one of the two blocks is selected by the configuration shown in FIG. 3 and the clock signal is output.
That is, when the switching control signal CONT is at the H level, the 3-state gate of the clock generation circuit 1 is turned on and the gate of the clock generation circuit 2 is turned off, so that the output of the clock generation circuit 1 is selected. Conversely, when the switching control signal is at the L level, the output of the clock generation circuit 2 is selected as the clock signal. However, since the above-described two conventional clock generation circuits generate clocks independently of each other, there is a drawback that the clock cycles before and after do not match when switching and the phase of the clock signal shifts. .
The phase shift of the clock signal causes a data error in information transmission, and remarkably impairs the reliability of the transmission device.

[0006]

It is an object of the present invention to eliminate the drawbacks of switching in a conventional clock generator having a redundant configuration as described above. It is an object of the present invention to provide a clock generation device having a redundant configuration that does not generate the phase fluctuation.

[0007]

SUMMARY OF THE INVENTION To achieve this object, the present invention comprises a plurality of blocks which generate a clock signal each time a reference clock is counted and counted up by a predetermined number, and a clock having a redundant configuration for selecting one of the blocks. In the generation circuit, each counter of the plurality of blocks is configured to be reset based on the clear signal of the block selected as the current block. Also, a counter that generates a clock signal each time the reference clock is counted and counted up by a predetermined number, gate means that controls the output of this counter output to the outside, its own counter output, or the counter output of another block. It is characterized in that it is provided with a plurality of blocks having means for resetting the counter depending on which one of them, and one of the blocks is selected.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A clock generation circuit having a redundant configuration of the present invention will be described in detail below with reference to the illustrated embodiments. Figure 1
FIG. 3 is a block diagram showing an embodiment of a clock generation circuit according to the present invention. The circuit shown in this figure is almost the same as the conventional circuit shown in FIG. 3, but is different in that the two clock generation circuits 1 and 2 are connected to each other by a clear terminal. That is, the clock generation device having this redundant configuration includes the clock generation circuits 1 and 2, and one circuit 1
Includes a reference clock signal SC and a switching control signal CONT,
The other circuit 2 receives the reference clock signal SC and the inverter.
The switching control signals logically inverted by the clock 3 are supplied to each other, the clear terminals of the two clock generation circuits are connected to each other, and the clock outputs of both are wired-ORed and supplied to the necessary blocks. It is composed of. One of the outputs of these two clock generation circuits is selected by the state value of the switching control signal CONT.

FIG. 2 is a block diagram showing an example of a concrete configuration of the clock generating circuit. The characteristic of this circuit is that of the conventional one shown in FIG. 4 having a selector 8 and a second 3-state gate. 9 is added and connected as follows. That is, a counter 4 for counting the number of pulses of the reference clock,
A decoder 5 for decoding the counter output, a waveform shaping circuit 6 for shaping the output waveform of the decoder, a 3-state gate 7, an output of the decoder 5 and a second 3 steps
A selector 8 for selecting the output of the gate gate 9 and supplying it to the reset terminal of the counter 4, and a second 3-state gate 9 for receiving the output of the decoder 5 as an input and generating a clear output.
And output control, that is, connected so as to control the enable terminals of the first and second 3-state gates 7 and 9 and the selector terminal of the selector 8 by the switching control signal CONT. It is a thing.

According to this structure, as described above, the decoder 5 is provided every time the reference clock SC is counted by a predetermined number.
Pulse is generated from the waveform shaping circuit 6 and 3 states.
It is output as a clock signal via the gate 7. Deco
The counter 4 is reset each time a double output is generated, and a new count is repeated. Therefore, the generated clock is the reference clock signal divided based on the set values of the counter and the decoder. Two sets of clock generation circuits configured in this way are provided, and one of the two blocks is selected by the configuration shown in FIG. 1 and the clock signal is output.

That is, in this embodiment, the counter 4 is reset by the output of the selector 8. Therefore, for example, when the clock generation circuit 1 is selected, that is, when the switching control signal is at the H level, the The counter operates based on the reference clock signal input to the circuit, and when the count value reaches a predetermined decode value, a decode output is generated. The selector 8 selects the output of the decoder 5 when its own block is selected, and the counter is reset by the decoder output of the selected block. In this way, the counter repeats counting up and resetting and shapes the decoded output into a rectangular wave with a duty ratio of 50% and outputs it as a clock signal. On the other hand, in the block which is not selected, that is, when the switching control signal is at the L level, in the clock generation circuit 2 in FIG. 1, the first and second 3-state gates are in the off state. No clock signal is output, and the clear output which is the second 3-state gate output is not generated. Only the clear output from the other selected circuit is passed through the selector 8 to the counter 4 It is supplied to the reset terminal of. Therefore, since the counters of both clock generation circuits are always reset by the clear output of one circuit, the counter operations of both circuits match each other, and the count-up and the reset are repeated with the synchronization always established.

In this state, if a failure occurs in one of the working circuits, a circuit (not shown) detects the failure, and when the switching control signal is in the L state, the clock generating circuit 2 of the spare block is selected. When the clock generation circuit 2 is selected, the related operation similar to that described above functions in the reverse order of the circuits 1 and 2, and the clock signal from the circuit 2 is continuously output to the outside.

[0013]

As described above, according to the present invention, the plurality of counters for counting the reference clock signals in the clock generation circuit are simultaneously reset by the block output which is currently selected. The phases match, and the output clock signal does not fluctuate even when the active spare is switched.

[Brief description of drawings]

FIG. 1 is a block diagram of a clock generation circuit having a redundant configuration showing an embodiment of the present invention.

FIG. 2 is a block diagram showing an internal configuration example of a clock generation circuit used in the embodiment of the present invention.

FIG. 3 is a block diagram showing a conventional clock generation circuit having another redundant configuration.

FIG. 4 is a block diagram showing an example of a conventional clock generation circuit.

[Explanation of symbols]

1, 2 clock generation circuit, 3 inverter, 4
Counter, 5 decoder, 6 waveform shaping circuit,
7, 9 3 state gate, 8 selector.

Claims (2)

[Claims] 1. A clock generation circuit having a plurality of blocks for generating a clock signal each time a reference clock is counted and counted up by a predetermined number, and having a redundant configuration for selecting one of the blocks, each of the plurality of blocks being provided. A clock generation circuit having a redundant configuration, characterized in that a counter is configured to be reset based on a clear signal of a block selected as a working block. 2. A counter for generating a clock signal each time a reference clock is counted and counted up by a predetermined number, and a gate means for controlling output of the counter output to the outside.
A plurality of blocks having means for resetting the counter according to either the self counter output or the counter output of another block are provided, and one of the blocks is configured to have a redundant configuration. Clock generation circuit.