JP4751359B2 - EL display device - Google Patents

Description

  The present invention relates to an EL display device and a method for driving the EL display device using a self-luminous display panel (display device) such as an EL display panel (display device) using an organic or inorganic electroluminescence (EL) element. is there. The present invention also relates to a power supply circuit (power supply IC) of the organic EL display device.

  In an active matrix image display device using an organic electroluminescence (EL) material or an inorganic EL material as an electro-optic conversion substance, light emission luminance changes according to a current written to a pixel. The EL display device is a self-luminous type having a light emitting element in each pixel. The EL display device has advantages such as high image visibility, high luminous efficiency, no need for a backlight, and high response speed compared to a liquid crystal display panel.

  FIG. 1 is a configuration diagram of a pixel 16 of an EL display device. The pixels 16 are formed in a matrix on the display screen 22. As an example, four transistors (TFTs) 11 a to 11 d are formed in the pixel 16.

  The gate terminal of the driving transistor 11a is connected to the source terminal of the switching transistor 11b. The gate terminals of the switching transistor 11b and the switching transistor 11c are connected to the gate signal line 17a.

  The drain terminal of the transistor 11b is connected to the drain terminal of the switching transistor 11c and the source terminal of the transistor 11d. The source terminal of the switching transistor 11 c is connected to the source signal line 18.

  The gate terminal of the transistor 11d is connected to the gate signal line 17b. The drain terminal of the transistor 11 d is connected to the anode electrode of the EL element 15. The cathode terminal of the EL element 15 is connected to the cathode terminal (Vss). The source terminal of the driving transistor 11a is connected to the anode terminal (Vdd).

  The switching transistors 11b and 11c are on (closed) and off (open) controlled by an on / off control signal applied to the gate signal line 17a. The gate terminal of the transistor 11d is connected to the gate signal line 17b. The transistor 11d is on (closed) and off (open) controlled by an on / off control signal applied to the gate signal line 17b.

  As shown in FIG. 2, the gate driver circuit 12a is formed or arranged at the left end of the display screen 22, and the gate driver circuit 12b is formed or arranged at the right end. The gate driver circuit 12a controls the gate signal line 17a, and the gate driver circuit 12b controls the gate signal line 17b. The gate driver circuits 12a and 12b are supplied with an on-voltage (VGL) of the gate signal line 17 and an off-voltage (VGH) of the gate signal line 17.

  The source driver circuit 14 generates a program current Iw, and the generated current is selected by the gate driver circuit 12 a and applied to the pixel 16. The driving transistor 11a of the pixel 16 is set (programmed) so that the current Iw flows. Setting is realized by holding a voltage in the capacitor 19 of the pixel 16.

  In the EL display device of the present invention, the gate driver circuit 12a has the off voltage VGH1 and the on voltage VGL1, and the gate driver circuit 12b has the off voltage VGH2 and the on voltage VGL2. Further, VGH1 = VGH2, and VGL1 <VGL2.

  In the pixel configuration of the organic EL display device illustrated in FIGS. 1 and 2, the switching transistors 11 b and 11 c function as switches for selecting a pixel (row) to which a video signal output from the source driver circuit 14 is applied. . The switch transistor 11 d functions as a switch for supplying current to the EL element 15. That is, the switch transistor 11d operates as a switch for selecting a pixel (row) to emit light. An up / down signal (UP) is applied to the gate driver circuit 12 as a clock signal (CLK), start signals (ST1, ST2), and the like.

  The clock signal (CLK) is a signal for sequentially moving selected pixel rows. The start pulse signal (ST) is a signal for designating a pixel row to be selected. The start pulse signal (ST) moves in the shift register circuit of the gate driver circuit 12 by the clock signal (CLK). The up / down signal is a screen upside down switching signal. The gate signal line 17 is selected in accordance with the start pulse position in the shift register circuit (an ON voltage (VGL) is applied to the gate signal line 17).

  The state in which the pixel to which the video signal is applied is the state shown in FIG. The switching transistor 11d is in an open state, and the switching transistors 11b and 11c are in a closed state.

  The state where the EL element 15 is caused to emit light is the state shown in FIG. The switching transistor 11d is in a closed state, and the switching transistors 11b and 11c are in an open state.

  The above operation is illustrated on the display screen 22 as shown in FIG. Reference numeral 41 in FIG. 4A denotes a pixel row (write pixel row) selected for current or voltage programming. The writing pixel row 41 is not lit (non-display pixel row). In order to turn off the light, the gate driver circuit 12b is controlled, and the switching transistor 11d of the pixel 16 is opened. In order to open the switching transistor 11d, an off voltage (VGH) may be applied to the gate signal line 17b. The position where the gate driver circuit 12 applies the off voltage (VGH) to the gate signal line 17 is shifted in synchronization with the horizontal synchronizing signal (HD). HD is usually a clock signal (CLK).

  The non-lighting (non-display) state refers to a state in which no current flows through the EL element 15. Or, a state where a small current within a certain level flows. That is, it is a dark display state. A non-display (non-lighting) range of the display screen 22 is referred to as a non-display area 45. A display (lighting) range of the display screen 22 is referred to as a display (lighting) region 46. The switching transistor 11 d of the pixel 16 in the display area 46 is closed, and a current flows through the EL element 15. However, it is natural that no current flows through the EL element 15 in the black image display. A region where the switching transistor 11d is open is a non-display region 45.

  A timing chart is shown in FIG. In the pixel 16 of the selected pixel row, when the on voltage (VGL) is applied to the gate signal line 17a, the off voltage (VGH) is applied to the gate signal line 17b (see FIG. 3A). reference). During this period, no current flows through the EL elements 15 in the selected pixel row (non-lighting state).

  In the pixel row in which the on-voltage is not applied (not selected) to the gate signal line 17a and the pixel row in the lighting state, the on-voltage (VGL) is applied to the gate signal line 17b. Current flows through the EL elements 15 in this pixel row, and the EL elements 15 emit light. This light emission luminance is shown as luminance B (nt) in FIG.

  The off-voltage (VGH) is applied to the gate signal line 17b in the pixel row in which the on-voltage is not applied (not selected) to the gate signal line 17a and the pixel row is not lit. No current flows through the EL elements 15 in this pixel row, and the EL elements 15 are in a non-light emitting state.

  4 and 5 show a state in which the lighting region 46 of the N1 pixel row is generated. The illuminated area of the N1 pixel row is moved from the upper side to the lower side of the display screen 22. The period of movement depends on the operation frame rate of the gate driver circuit 12b.

  The rewriting cycle of the N1 display screen 22 depends on the operation frame rate (frame frequency) of the gate driver circuit 12a. Normally, the operation frame rate of NTSC is 60 Hz (60 frames per second, the time for rewriting one screen is 1/60 seconds), and PAL is 50 Hz (50 frames per second). In MPEG, there are 30 frames (30 frames per second, the time for rewriting one screen is 1/30 seconds) or 15 frames (15 frames per second, the time for rewriting one screen is 1/15 seconds).

  In synchronization with the frame frequency, a start pulse (ST1) is applied to the gate driver circuit 12a. As the start pulse (ST2), an input pattern having a frame rate period is generated and applied to the gate driver circuit 12b.

  In FIG. 4, it is assumed that the N1 pixel rows in the display screen 22 are continuously lit. The area to be lit may be divided as shown in FIG. If the area of the display screen 22 is 100, the area of the lighting region 46 in FIG. 4 is 20, and the display brightness is 10, the display brightness ratio of the display screen 22 is 20 × 10/200 = 1. Also in FIG. 6, in order to divide the lighting region 46 into three and make the same display luminance ratio as in FIG. 4, the display luminance of each divided lighting region 46 is 10, and the area of each lighting region 46 is N1 / 4. That's fine.

  The pixel configuration in FIG. 1 is a current programming pixel configuration. As another pixel configuration of the current programming method, the configuration of FIG. 7 is exemplified. In FIG. 7A, the driving transistor 11b and the transistor 11a constitute a current mirror circuit. A switching transistor 11 e is formed in the current path from the driving transistor 11 b to the EL element 15. When the program current applied to the source signal line 18 is applied to the pixel 16, an on-voltage is applied to the gate signal line 17a, and the switching transistors 11c and 11d are turned on. A voltage corresponding to the applied program current is held in the capacitor 19. When the on / off voltage is applied to the gate signal line 17b, the switching transistor 11e is turned on / off, and the current flowing through the EL element 15 is controlled.

  In FIG. 1, the driving transistor 11a is a P channel. FIG. 7B shows a case where the driving transistor 11a is an N channel. A switching transistor 11 d is formed in the current path between the driving transistor 11 a and the EL element 15.

  The above is a pixel configuration of a current programming method (current driving method). FIG. 8 shows a pixel configuration of a voltage programming method (voltage driving method).

  In FIG. 8A, a capacitor 19b is formed between the gate terminal of the driving transistor 11a and the switching transistor 11c. The video signal applied to the source signal line 18 is applied to the gate terminal of the driving transistor 11a via the capacitor 19b when the switching transistor 11c is turned on.

  In the pixel configuration of FIG. 8B, a switching transistor 11e is formed in the current path to the EL element 15, and a switching transistor 11c that generates a path for applying a video signal to the driving transistor 11a is provided. Yes. When the program voltage (video signal) applied to the source signal line 18 is applied to the pixel 16, an on-voltage is applied to the gate signal line 17a, and the switching transistors 11c and 11d are turned on. The video signal corresponding to the applied program voltage is held in the capacitor 19a. When the on / off voltage is applied to the gate signal line 17b, the switching transistor 11e is turned on / off, and the current flowing through the EL element 15 is controlled.

  In the pixel configuration of FIG. 8B, a switching transistor 11d is formed in the current path to the EL element 15, and a switching transistor 11b that generates a path for applying a video signal to the driving transistor 11a is provided. Yes. When the program voltage (video signal) applied to the source signal line 18 is applied to the pixel 16, an on-voltage is applied to the gate signal line 17a, and the switching transistor 11b is turned on. A video signal corresponding to the applied program voltage is held in the capacitor 19. When the on / off voltage is applied to the gate signal line 17b, the switching transistor 11d is turned on / off, and the current flowing through the EL element 15 is controlled.

  As a modified example of the voltage programming method or the current programming method, there is a pulse driving method (PWM driving method, subfield driving method) that has the concept of a subfield and expresses gradation by the number of times or time when the driving transistor is turned on / off. is there. These are also a voltage program system or a current program system.

  In the EL display device, the pixels 16 are formed in a matrix on the display screen 22. The number of pixels formed on the display screen 22 is several hundred thousand or more. When a defect occurs in the transistor 11 or the like of the pixel 16, the display quality is degraded. In the liquid crystal display device, the pixel is formed of one transistor, whereas in the EL display device, a plurality of transistors are formed in the pixel 16 as illustrated in FIGS. 1, 7, and 8. . Therefore, in the case of an EL display device, defects of the pixels 16 are likely to occur.

  Therefore, it is necessary to detect a defect of the pixel 16. However, there has been no proper method for detecting defects such as the pixels 16 (first problem).

  The EL display device is a self-luminous device, and the light emission efficiency of red (R), green (G), and blue (B) pixels is different. Also, the luminous efficiency varies from production lot to production lot. Therefore, it is important to adjust the white (W) balance and display luminance appropriately by adjusting the currents flowing through the red (R), green (G), and blue (B) pixels in the product shipping process. In the liquid crystal display device, the display luminance can be easily adjusted by adjusting the current flowing through the backlight, and the white (W) balance can be easily adjusted by changing the gamma characteristic of the voltage applied to the liquid crystal layer. . On the other hand, in the EL display device, the red (R), green (G), and blue (B) EL elements have different light emission efficiencies and characteristic variations of the transistor 11 of the pixel 16 occur. It was not easy to adjust, and brightness adjustment was not easy (second problem).

  In the liquid crystal display device, the light modulation rate of the liquid crystal layer does not decrease, whereas in the EL display device, the luminous efficiency of the EL element decreases with the lighting time. As for the decrease in luminous efficiency, a burn-in display occurs when there are a portion where light is emitted for a long time and a portion where the light emission is long. The rate at which the luminous efficiency decreases is large in the initial state, and the luminous efficiency hardly decreases after a certain lighting time. Therefore, the EL display device is shipped after the aging process is performed to reduce the light emission efficiency. However, white (W) balance is also required in the aging process, and it is necessary to emit light with higher brightness than in the normal display state, but there was no appropriate light emission method and adjustment or aging setting method. (Third problem).

  An object of the present invention is to solve the above first conventional problem, and to provide an EL display device capable of appropriately detecting a pixel defect.

  In the present invention, a test transistor for applying a voltage or current to the source signal line 18 of the display screen 22 is formed simultaneously with the pixel 16. The test transistor is configured so that the magnitude of the current applied for each of RGB can be adjusted.

  In addition, a voltage is applied to each pixel 16 via a test transistor, and a current flowing through the anode wiring or the cathode wiring is measured with the voltage applied. Variation data of transistor characteristics of the pixel 16 is obtained from the measured current. Further, the voltage applied via the test transistor is adjusted so that the current flowing through the anode wiring or the cathode wiring becomes a predetermined value.

  In the present invention, a voltage or a constant current can be applied to the source signal line via the test transistor. Therefore, inspection of pixels and the like can be easily realized without using other means.

  The present invention can be applied to both the current program type EL display device and the voltage program type EL display device shown in FIGS. Further, the present invention can also be applied to a pulse drive type (PWM drive type, subfield drive type) EL display device.

  In the present specification, some drawings are omitted and enlarged or reduced for easy understanding and drawing. Moreover, the part which attached | subjected the same number or the symbol etc. has the same or similar form, structure, material, function, or operation | movement.

  In the embodiment of the present invention, as shown in FIGS. 4 and 6, a non-display area 45 and a display area 46 are generated on the display screen 22. In the pixel configuration of FIG. 1, the display region 46 applies a selection voltage (ON voltage) to the gate signal line 17b to turn on the switching transistor 11d in the selected pixel row. In the non-display area 45, a non-selection voltage (off voltage) is applied to the gate signal line 17b to turn off the switching transistor 11d in the non-selected pixel row.

  Similarly, in the pixel configuration of FIG. 7A, the display region 46 applies a selection voltage (ON voltage) to the gate signal line 17b to turn on the switching transistor 11e in the selected pixel row. In the non-display area 45, a non-selection voltage (off voltage) is applied to the gate signal line 17b to turn off the switching transistor 11e in the non-selected pixel row.

  In the pixel configuration of FIG. 7B, the display region 46 applies a selection voltage (ON voltage) to the gate signal line 17b to turn on the switching transistor 11d in the selected pixel row. In the non-display area 45, a non-selection voltage (off voltage) is applied to the gate signal line 17b to turn off the switching transistor 11d in the non-selected pixel row.

  In FIG. 8A, which is a voltage-driven pixel configuration, the display region 46 applies a selection voltage (ON voltage) to the gate signal line 17b to turn on the switching transistor 11e in the selected pixel row. . In FIG. 8B, the display region 46 applies a selection voltage (ON voltage) to the gate signal line 17b to turn on the switching transistor 11d in the selected pixel row. In the non-display area 45, a non-selection voltage (off voltage) is applied to the gate signal line 17b to turn off the switching transistor 11d in the non-selected pixel row.

  A driving method in which the display area 46 and the non-display area 45 are generated on the display screen 22 and the non-display area 45 or the display area 46 is moved in the vertical direction of the display screen 22 for display is called a duty drive system.

  The ratio of the display area 46 / (display area 46 + non-display area 45) is called a duty ratio. Alternatively, the duty ratio is also (number of gate signal lines 17b to which an ON voltage is applied) / (number of all gate signal lines 17b). In addition, an ON voltage is applied to the gate signal line 17b, which is (the number of selected pixel rows connected to the gate signal line 17b) / (the total number of pixel rows on the display screen 22).

  The EL display device of the present embodiment changes the ratio of the display area 46 and the non-display area 45, changes the area of the non-display area 45 relative to the area of the display screen 22, or sets the number of pixels in the display state. The brightness or brightness of the screen is adjusted by increasing / decreasing it. Further, the magnitude or amplitude value of the video signal written to the display screen 22 is changed. As an example, the brightness of the screen is realized by changing or adjusting the duty ratio, the reference current, and the video amplitude value.

  In the present embodiment, the duty ratio is changed in accordance with the lighting rate. The lighting rate is a ratio with respect to the maximum current flowing through the anode or cathode of the panel. The lighting rate can also be restated as the ratio of the current that flows through the panel when a certain image is displayed and the maximum current that flows through all the EL elements of the panel. When the lighting rate is high, the display is close to a white raster. When the lighting rate is low, there are many black display portions on the entire screen. By changing the duty ratio corresponding to the lighting rate, the power consumed on the display screen 22 can be averaged. In addition, the power consumption can be suppressed below a certain level.

  The low lighting rate means that the current flowing through the display screen 22 is small, but also means that there are many low gradation display pixels constituting the image. That is, the image forming the display screen 22 has many dark pixels (low gradation pixels). Therefore, the low lighting rate can be paraphrased as a state where there is a lot of low gradation video data when the video data constituting the screen is subjected to histogram processing.

  The high lighting rate means that the current flowing through the display screen 22 is large, but also means that there are many high gradation display pixels constituting the image. In other words, the image forming the display screen 22 has many bright pixels (high gradation pixels). Therefore, the high lighting rate can be paraphrased as a state where there is a lot of high gradation video data when the video data constituting the screen is subjected to histogram processing.

  Controlling the duty ratio or the like corresponding to the lighting rate may mean a state that is synonymous or similar to the control corresponding to the gradation distribution state or histogram distribution of the pixel.

  From the above, the control based on the lighting rate is based on the gradation distribution state of the image (low lighting rate = many low tone pixels, high lighting rate = many high tone pixels) depending on the case. In other words, it can be controlled. For example, it is also effective to increase the reference current ratio as the lighting rate decreases. Reducing the duty ratio as the lighting rate increases is also effective in averaging the power consumed by the EL display panel. It is also effective in that peak power can be suppressed.

  In the present embodiment, as shown in FIG. 13, the duty ratio is changed in accordance with the lighting rate (%). The lighting rate is obtained from a video signal input to the EL display device. Alternatively, the lighting rate is obtained by measuring the current flowing through the anode wiring 231 or the cathode wiring 232 of the EL display device. The current flowing through the anode wiring 231 and the cathode wiring 232 is the power supply circuit (power supply IC) of this embodiment, the EL display device of this embodiment, or the EL display of this embodiment, which will be described with reference to FIGS. It can be obtained by driving or adjusting the apparatus.

  The lighting rate and the duty ratio vary depending on the display image displayed on the display screen 22. The lighting rate and duty ratio are not changed in real time, but with a certain delay or hysteresis. It is also effective to vary the duty ratio according to the external environment illuminance of the EL display device. The external environment illuminance is measured by a photosensor added to the EL display device. When the external environment illuminance is higher than a certain value, the duty ratio is fixed to the maximum value. When the external illuminance is low, the duty ratio is reduced in accordance with the external illuminance.

  The higher the lighting rate, the smaller the duty ratio, and the lower the lighting rate, the larger the duty ratio. Further, the lighting rate correlates with the power or current consumed on the display screen 22 of the EL display device. Therefore, the duty ratio may be obtained from the power or current consumed on the display screen 22 of the EL display device. The relationship between the lighting rate and the duty ratio is obtained from FIG. 13 as an example. FIG. 13 is obtained in advance or obtained in real time by calculation.

  In order to facilitate understanding, in this specification, description will be made mainly assuming that duty ratio control or the like is changed according to the lighting rate (%).

  As shown in FIG. 6, the EL display device according to the present embodiment can divide the display area 46 in the display screen 22 into a plurality of parts. The division of the display area 46 can be realized by an input pattern of a start pulse signal (ST2) input to the gate driver circuit 12b. By dividing the display area 46 into a plurality of parts, the occurrence of flicker can be suppressed even at a low frame rate. Further, the number of divisions of the display area 46 or the non-display area 45 is made different between moving image display and still image display. Further, the number of divisions of the display area 46 may be changed in accordance with the lighting rate.

  The non-display area 45 or the display area 46 occupying the display screen 22 has a band shape and moves downward from the top of the screen or upward from the bottom of the screen. In some cases, for each frame, the screen may be switched from the top to the bottom and from the bottom to the top.

  In this specification, the gate driver circuit 12a selects a pixel row into which a video signal is written, and the gate driver circuit 12b selects a pixel row to be lit. Therefore, the gate driver circuit 12 is a pixel row selection circuit. The gate driver circuit 12a and the gate driver circuit 12b do not need to be clearly separated from each other. The gate driver circuit 12a and the gate driver circuit 12b may be formed or arranged in one gate driver circuit. Also in this case, it is considered that the gate driver circuit 12a and the gate driver circuit 12b are formed or arranged. The gate driver circuit 12 has a function of selecting or specifying a pixel row. Therefore, if it has the function of a shift register circuit, it is synonymous with the gate driver circuit 12. The gate driver circuit 12 is a function for designating or selecting a specific pixel row. As described above, in this specification, the gate driver circuit 12 is used in a broad sense.

  In this specification, the off voltage is VGH and the on voltage is VGL. This is a case where the switching transistors 11b, 11c, 11d and the like are P-channel transistors. When the switching transistors 11b, 11c, 11d, etc. are N-channel transistors, the on voltage is VGH and the off voltage is VGL. Therefore, the logic voltages (VGH, VGL) to be applied to the gate signal line 17 may be set in accordance with the channel polarities of the driving transistor 11a and the switching transistor 11.

  FIG. 9 is an explanatory diagram of a program current generation circuit of the source driver circuit 14 of the EL display device according to the present embodiment. The source driver circuit 14 includes reference current circuits 93 (93R, 93G, 93B) corresponding to red (R), green (G), and blue (B). The reference current circuit 93 includes a resistor R1 (R1r, R1g, R1b), an operational amplifier 91a, and a transistor 94a. The value of the resistor R1 (R1r, R1g, R1b) is configured so that it can be set or adjusted independently corresponding to the R, G, B gradation currents. The resistor R1 is an external resistor arranged outside the source driver circuit 14.

  A voltage Vi is applied to the + terminal of the operational amplifier 91a by an electronic volume 92. The voltage Vi is obtained by dividing a stable reference voltage Vb with a resistor R. The electronic volume 92 changes the output voltage Vi according to the signal IDATA. The reference current Ic is (Vs−Vi) / R1. The RGB reference currents Ic (Icr, Icg, Icb) are adjusted or varied by independent reference current circuits 93, respectively. The variable is implemented by an electronic volume formed for each RGB. Therefore, the value of the voltage Vi output from the electronic volume 92 changes according to the control signal applied to the electronic volume 92. The magnitude of the RGB reference current changes with the voltage Vi, and the magnitude of the gradation current (program current) Iw output from the terminal 96 changes proportionally.

  The generated reference current Ic (Icr, Icg, Icb) is applied to the transistors 94a to 94b. Transistor 94b and transistor group 95 form a current mirror circuit. In FIG. 9, the transistor 94 b 1 is illustrated as being constituted by one transistor, but actually, as with the transistor group 95, the transistor 94 b 1 is formed as a set (transistor group) of unit transistors 102.

  The program current Iw from the transistor group 95 is output from the output terminal 96. The gate terminal of each unit transistor 102 of the transistor group 95 and the gate terminal of the transistor 94 b are connected by a gate wiring 104.

  The transistor group 95 is configured as a set of unit transistors 102 as illustrated in FIG. In order to facilitate understanding, description will be made assuming that the video data and the program current are converted in a proportional or correlated relationship. The switch 101 is selected by the video signal, and the selection of the switch 101 generates a program current Iw as a set (addition) of output currents of the unit transistors 102. Therefore, the video signal can be converted into the program current Iw. In this embodiment, the unit current of the unit transistor 102 is configured to correspond to the size of 1 of the video data.

  The unit current is the magnitude of one unit of program current output from the unit transistor 102 corresponding to the magnitude of the reference current Ic. When the reference current Ic changes, the unit current output from the unit transistor 102 also changes in proportion. This is because the transistor 94b and the unit transistor 102 constitute a current mirror circuit.

  Each of the RGB transistor groups 95 includes a group of unit transistors 102, and the magnitude of the output current (unit program current) of the unit transistors 102 can be adjusted by the magnitude of the reference current Ic. If the magnitude of the reference current Ic is adjusted, the magnitude of the program current (constant current) Iw for each gradation can be changed or varied for each RGB. Therefore, in an ideal state where the characteristics of the RGB unit transistors 102 are the same, the white balance of the display image of the EL display device is achieved by changing the magnitude of the reference current Ic of the RGB reference current circuit 93. be able to.

  Hereinafter, in order to facilitate the description and to facilitate the drawing, the description will be made assuming that the transistor group 95 of the source driver circuit (IC) 14 is 6 bits. In FIG. 10, each unit transistor 102 is arranged for each constant current data (D0 to D5). One unit transistor 102 is arranged in the D0 bit. Two unit transistors 102 are arranged in the D1 bit. Four unit transistors 102 are arranged for the D2 bit, eight unit transistors 102 are arranged for the D3 bit, and 16 unit transistors 102 are arranged for the D4 bit. Similarly, 32 unit transistors 102 are arranged in the D5 bit.

  Whether or not the output current of the unit transistor 102 of each bit is output to the output terminal 96 is realized by on / off control by the analog switch 101 (101a to 101f). The decoder circuit 105 decodes the input video data KDATA. The analog switch is ON / OFF controlled corresponding to the video signal data KDATA.

  Program current Iw flows through internal wiring 103. The potential of the internal wiring 103 becomes the potential of the source signal line 18. The potential of the internal wiring 103 is AVdd or less and GND potential or more. The potential of the source signal line 18 is the voltage of the gate terminal of the driving transistor 11a of the pixel 16 (in the case of the pixel configuration in FIG. 1) when the constant current Iw is applied to the source signal line 18 to obtain a steady state. .

  FIG. 11 is an explanatory diagram of a gradation voltage output circuit of a voltage program method. The minimum potential generated in the gradation voltage output circuit is 0 V (GND potential), and the maximum potential is the power supply voltage AVdd of the source driver circuit 14. Note that the low potential of the gamma curve is defined by the gradation amplifier 112L. The high potential of the gamma curve is defined by the gradation amplifier 112H. The voltage output from the gradation amplifier 112H is VH. The voltage output from the gradation amplifier 112L is VL. Therefore, the amplitude width is VH-VL.

  The output voltage of the gradation amplifier 112 is controlled by the amplitude adjustment register 111. The output bit of the amplitude adjustment register 111 is 8 bits. Therefore, the gradation amplifier 112 can change the output in 256 stages. Increasing the value of the gradation amplifier 112H (to a high potential) increases the amplitude value of the gamma curve. By reducing the value of the gradation amplifier 112H (to a low potential), the amplitude value of the gamma curve is reduced. By increasing the value of the gradation amplifier 112L (to a high potential), the amplitude value of the gamma curve decreases. By reducing the value of the gradation amplifier 112H (to a low potential), the amplitude value of the gamma curve increases. In the configuration of FIG. 11, the gradation amplifier 112H and the gradation amplifier 112L can be operated independently.

  A resistor is connected in a ladder shape between the gradation amplifier 112H and the gradation amplifier 112L. A wiring terminal 113 is drawn between the resistors (VR1, VR2, VR3, VR4..., VRN). The wiring terminal 113 is connected to each selector circuit of the voltage DAC circuit 123 of FIG. Note that the driving transistor 11a of the pixel 16 is a P-channel transistor, and the low gradation side is close to AVdd, and the high gradation side is close to GND.

  The resistance values of the resistors (VR1, VR2, VR3, VR4..., VRN) of the resistor ladder are configured to be variable by command setting. The resistance value changes according to the command.

  As shown in FIG. 12, the video signal data KDATA is held in the voltage data latch A circuit 121a. Each data is 6 bits. In addition, the pixel column is 240 dots, and each dot is RGB 3 data. Therefore, the line memories of the voltage data latch A circuit 121a and the voltage data latch B circuit 121b are 6 bits × 240 RGB. The data of the voltage data latch A circuit 121a is copied to the voltage data latch B circuit 121b in synchronization with the horizontal synchronization signal (HD).

  The voltage DAC circuit 123 is composed of a switch circuit. One of the terminals 113 of the gradation voltage output circuit 122 is selected from the digital data of the voltage data latch B circuit 121b. The voltage of the selected terminal 113 is output to the source signal line 18.

  When the operation frame rates of the gate driver circuit 12a and the gate driver circuit 12b are different, an ON voltage (VGL) may be applied to the gate signal line 17a and the gate signal line 17b connected to the same pixel 16.

  The source driver circuit 14 includes both the program current output circuit shown in FIGS. 9 and 10 and the program voltage output circuit shown in FIGS. The program current method causes insufficient video signal writing in the low gradation region, but the program voltage method can realize good video signal writing even in the low gradation region. However, in the program voltage method, compensation for variation characteristics of the driving transistor 11a is not complete. In the program current method, compensation for variation characteristics of the driving transistor 11a is good.

  By configuring and operating both the program current output circuit and the program voltage output circuit in the source driver circuit 14, it is possible to compensate for the disadvantages of the program current method and the program voltage method. Can be realized. In the present embodiment, a drive in which a program voltage is applied to each pixel in the first half of a period for selecting one pixel row and a program current is applied in the second half of a period for selecting one pixel row in the applied video signal. The method is adopted. A program current is applied after applying a program voltage. The program voltage is not applied when the corresponding video signal has a high gradation. This is because the target gradation signal can be sufficiently written by the program current.

  If both the program current output circuit and the program voltage output circuit are configured in the source driver circuit 14, a constant current is applied to each pixel in the first half of the period for selecting one pixel row for the applied video signal. The present invention can also be applied to a driving method in which a program voltage is applied in the latter half of the period for selecting one pixel row. By applying a constant current, the operating point of the driving transistor 11a is reset (offset position is obtained). Next, a program voltage is applied to the pixel. As the pixel configuration, a combination of FIG. 1 and FIG. 23 is used.

  If the source driver circuit 14 includes both a program current output circuit and a program voltage output circuit, the amplitude or magnitude of the video signal can be easily modulated by the reference current. Also, white balance adjustment and duty drive system can be easily realized.

  In the EL display device of this embodiment, a test transistor 145 is formed as shown in FIG. The test transistor 145 is formed on the array substrate 162 on which the pixel transistor 11 is formed. The test transistor 145 is formed by the same process as the transistor 11. The test transistor 145 is formed on the array substrate 162 by the same process as the gate driver circuit 12.

  The test transistor 145 basically has the same configuration as the transistor 11 of the pixel 16. The transistor 145 is the same channel transistor as the switching transistor 11c. If the switching transistor 11c is a P-channel transistor, the test transistor 145 is also a P-channel transistor. If the switching transistor 11c is an N-channel transistor, the test transistor 145 is also an N-channel transistor.

  The switching transistor 11c is ON / OFF controlled by the applied voltage (VGH1, VGL1) of the gate signal line 17a. When the switching transistor 11c is a P-channel transistor, the switching transistor 11c is turned off at VGH1, and the switching transistor 11c is turned on at VGL1. When the switching transistor 11c is an N-channel transistor, the switching transistor 11c is turned on at VGH1, and the switching transistor 11c is turned off at VGL1.

  The test transistor 145 is turned off by the off voltage of the gate signal line 17a. When the test transistor 145 is a P-channel transistor, the test transistor 145 is turned off at VGH1. When the test transistor 145 is an N-channel transistor, the test transistor 145 is turned off at VGL1.

  The test transistor 145 is turned on at a voltage higher than the on voltage of the gate signal line 17a. When the test transistor 145 is a P-channel transistor, the transistor is turned on with a voltage VGLt (a large voltage in the negative direction) lower than VGL1. For example, if VGL1 = −3V, VGLt = −9V.

  VGHt and VGLt are voltages used in the inspection mode. VGH1 (VGH) and VGL1 (VGL) are generated by the power supply IC 222. VGHt and VGLt are generated by an inspection circuit manufactured for inspection. Alternatively, VGHt and VGLt are generated by the power supply IC 222. The power supply IC 222 changes the output voltage by command setting.

  By varying the VGHt and VGLt voltages and inspecting or evaluating the display state and display luminance with the variable voltage setting values, the characteristic margin and the operation margin of the EL display panel can be quantitatively acquired. The same applies to Vdd (Vddt) and Vss (Vsst).

  The test transistor 145 is on / off controlled by the applied voltages (VGH1, VGL1) of the gate signal line 17a. The W / L ratio of the test transistor 145 is made larger than the W / L ratio of the switching transistor 11c. For example, if the channel width W of the switching transistor 11c is 4 μm and the channel length L is 5 μm (W / L = 4/5 = 0.8), the channel width W of the test transistor 145 is 10 μm and the channel length L is 5 μm. (W / L = 10/5 = 2).

  As illustrated in FIG. 15, the test transistor 145 has a drain terminal connected to the source signal line 18. Further, an output terminal pad 141 for connecting the output terminal of the source driver IC 14 to the COG (chip on glass) is formed at one end of the source signal line 18. The source driver IC 14 is ACF-connected to the input terminal pad 143 and the output terminal pad 141, and is mounted at the source driver IC mounting position 144 indicated by the dotted line in FIG.

  The source terminal of the test transistor 145 is connected to the signal input terminal 146. A constant current source or a constant voltage source is connected to the signal input terminal 146.

  Note that the drain terminal of the test transistor 145 corresponds to an example of the first terminal of the present invention. The source terminal of the test transistor 145 corresponds to an example of the second terminal of the present invention, and the wiring connecting the source terminal and the signal input terminal 146 corresponds to an example of the first wiring of the present invention. The wiring connecting the gate terminal of the test transistor 145 and the transistor control terminal 147 corresponds to an example of the second wiring of the present invention.

  As an example of a circuit that generates a constant current, the circuit configuration illustrated in FIG. 18 is used. In FIG. 18, a constant current circuit is configured by the operational amplifier 181, the transistor 182, and the resistor R. The voltage Vi is applied to the + terminal of the operational amplifier 181. The voltage Vi is set by data (IDAT) applied to the electronic volume 183. The electronic volume 183 is a DA conversion circuit. The constant current Ia is determined by Ia = Vi / R.

  The circuit configuration of FIG. 18 includes three circuits for R, G, and B, and the constant current output from the R, G, and B constant current circuit outputs is an independently configured electronic circuit. It is adjusted or variable by the volume 183.

  As shown in FIG. 18, in the method of applying a constant current to each pixel 16, the pixel 16 needs to have a pixel configuration of a current program method. The current programming pixel configuration needs to be configured such that a direct current flows between the current path flowing through the driving transistor 11 a or 11 b and the source signal line 18.

  As an example of a circuit that generates a constant voltage, the circuit configuration illustrated in FIG. 20 is used. In FIG. 20, the operational amplifier 181 constitutes a constant voltage circuit. The voltage Vi is applied to the + terminal of the operational amplifier 181. The voltage Vi is set by data (IDAT, 8 bits = 256 levels) applied to the electronic volume 183.

  The circuit configuration of FIG. 20 includes three circuits for R, G, and B, and the constant voltage output from the R, G, and B constant voltage circuit outputs is an independently configured electronic circuit. It is adjusted or variable by the volume 183.

  18 and 20, the current or voltage to be applied to each pixel of RGB is varied as necessary. This is because the light emission efficiency of the EL element may be different for RGB and the size of the driving transistor 11a may be different, so that the light emission luminance for each RGB is different with the same current or voltage. Since the EL display device of this embodiment includes the electronic volumes 183 independent of RGB, it can be flexibly handled.

  18 and 20, the test transistor 145 is turned on (closed) during panel inspection or panel adjustment, and is applied with a voltage as shown in FIG. 17 and turned off (opened) during normal display.

  A shift register circuit 333 (see FIG. 33 and the like) is added to the gate terminal of the test transistor 145 in the same manner as the gate driver circuit 12, and one or a plurality of test transistors 145 are sequentially formed according to the function of the shift register circuit 333. May be selected. With the above configuration, the test transistor 145 can be controlled on and off independently. Therefore, by turning on and off the test transistor 145 separately from the gate driver circuit 12a, the pixels 16 arranged in a matrix can be individually selected or selected in units of pixel columns, and a voltage or current can be applied. The above can be similarly applied to other examples of the present embodiment.

  The test transistor 145 may be cut and removed after the panel inspection or the panel adjustment process is completed. For example, the test transistor 145 is formed at a position B in FIG. 23 (the opposite side on which the source driver IC 14 is mounted). The test transistor 145 cuts the array substrate 162 at aa ′ in FIGS. The above can be similarly applied to other examples of the present embodiment.

  In the following description, it is assumed that the test transistor 145 is a P channel transistor. When the test transistor 145 is an N-channel transistor, VGH and VGL may be read.

  Voltages (VGH, VGLt) applied to the gate driver circuit 12a are applied to the transistor control terminals G (GR, GG, GB) connected to the gate terminal of the test transistor 145. When the test transistor 145 is a P-channel transistor, the test transistor 145 is turned on by applying the VGLt voltage. When turned on, a signal (constant current or constant voltage) applied to the signal input terminal 146 is applied to the source signal line 18.

  The constant current is not limited to a constant DC (direct current) current. It may be changed to a rectangular shape. Further, it may be changed stepwise. The constant current may be a constant current during a constant period (a period when at least one pixel row is selected. Similarly, the constant voltage is not limited to a constant DC (direct current) voltage. The constant voltage may be changed to a rectangular shape, or may be changed to a step shape, as long as it is a constant voltage for a certain period (a period in which at least one pixel row is selected).

  The voltage applied to the signal input terminal 146 is applied to the source signal line 18 to which the test transistor 145 is connected when the test transistor 145 is turned on. The voltage for turning on the test transistor 145 is VGLt. For example, if the constant voltage applied to the signal input terminal 146 is −2V, −2V is applied to each source signal line 18. If the constant current applied to the signal input terminal 146 is 10 mA, 10 mA is shunted and applied to each selected source signal line 18.

  When the pixel configuration is a current programming method as shown in FIGS. 1 and 7, a constant current is applied to the signal input terminal 146. The pixel rows are selected one by one, and the constant current is divided and applied to the selected pixel rows. For example, if 240 test transistors 145 are selected, the constant current of 10 mA is divided by 240 and applied to each source signal line 18. Therefore, a program current is applied to each pixel 16 and a relatively good image display can be realized.

  When the pixel configuration is a voltage programming method as shown in FIG. 8, a constant voltage is applied to the signal input terminal 146. Pixel rows are selected one by one, and the constant voltage is applied to the selected pixel rows. For example, if 240 test transistors 145 are selected, a constant voltage of −2 V is applied to each source signal line 18. Therefore, the program voltage is uniformly applied to each pixel 16.

  In the following embodiments, the pixel configuration is illustrated in FIG. 1, and the test transistor 145 is described as a P-channel transistor. However, it goes without saying that the present embodiment can be applied even if the pixel configuration is the configuration of FIGS.

  In FIG. 14, 145R is formed as the test transistor 145 for red (R). A voltage for turning on and off the test transistor 145R is applied to the transistor control terminal 147R, and a constant current or a constant voltage is applied to the signal input terminal 146R.

  Further, 145G is formed as the test transistor 145 for green (G). A voltage for turning on and off the test transistor 145G is applied to the transistor control terminal 147G, and a constant current or a constant voltage is applied to the signal input terminal 146G. 145B is formed as the test transistor 145 for blue (B). A voltage for turning on / off the test transistor 145B is applied to the transistor control terminal 147B, and a constant current or a constant voltage is applied to the signal input terminal 146B.

  As shown in FIG. 14, by configuring the test transistors 145 to be selected for each RGB, RGB images can be displayed on the display screen 22, and inspection such as defect inspection can be easily performed.

  In the gate signal line 17a, the selected pixel row position is shifted by one pixel row in synchronization with the horizontal synchronizing signal. A voltage or current from the test transistor 145 is applied to each pixel row. Usually, an on-voltage is always applied to the gate terminal of the test transistor 145.

  In the pixel row in which the on voltage is applied to the gate signal line 17a, the off voltage is applied to the gate signal line 17b. In the pixel row in which the off voltage is applied to the gate signal line 17a, the on voltage is applied to the gate signal line 17b. Alternatively, as shown in FIGS. 4 and 6, when duty driving is performed, an off voltage is applied to the gate signal line 17a and the gate signal line 17b of the pixel row corresponding to the non-display area 45.

  In FIG. 14, test transistors 145 (145R, 145G, 145B) are arranged for each of red (R), green (G), and blue (B), and a predetermined current or a predetermined voltage independent of RGB is applied. is there. However, the present embodiment is not limited to this. For example, as shown in FIG. 34, the test transistor 145 may be arranged without distinguishing between RGB. In the embodiment of FIG. 34, the voltage (current) applied to the signal input terminal 146 is controlled by the control voltage applied to the transistor control terminal 147 and applied to the source signal line 18. In FIG. 14, a voltage (current) is applied to the entire display screen 22 by the control voltage applied to the transistor control terminal 147. However, the present embodiment is not limited to this, and the display screen 22 may be divided into a plurality of regions, and different voltages (currents) may be applied to the divided regions.

  In order to apply the on / off voltage to the gate signal line 17, the gate driver circuit 12 is operated (FIG. 14). When a test is performed with an image displayed, ST1 and CLK in FIG. 2 are controlled to match the frame rate of 60 Hz or 50 Hz. When evaluating or inspecting characteristics such as point defect detection and pixel driving transistor 11a, ST1, CLK, etc. are controlled to reduce the frame rate to 1 Hz. VGH and VGL voltages are applied to the gate driver circuit 12.

  The gate driver circuit 12a sequentially selects the gate signal lines 17a. In synchronization with the selection of the gate signal line 17a, a predetermined current or a predetermined voltage is applied to the source signal line 18 from the test transistor 145, and the voltage or the like is written to the pixel by the switching transistor 11c in the selected pixel row.

  In the gate driver circuit 12b, the non-selection voltage is applied to the pixel row in which the gate signal line 17a is selected and a predetermined voltage (predetermined current) is written. In other pixel rows, a selection voltage is applied, or the duty ratio driving shown in FIGS. 4 and 6 is performed.

  In the above embodiment, a pixel row is selected for each pixel row, and a predetermined voltage (predetermined current) is written to the pixel 16. However, the present embodiment is not limited to this. For example, a plurality of pixel rows (for example, one pixel row and two pixel rows, three pixel rows and four pixel rows, five pixel rows and six pixel rows,...) Are selected, and a predetermined voltage (predetermined current) is selected as a pixel. 16 may be written. Alternatively, all the gate signal lines 17a may be simultaneously selected and a predetermined voltage (predetermined current) may be written to the pixel 16. Further, the gate signal line 17a in the upper half of the screen is simultaneously selected and a predetermined voltage (predetermined current) is written to the pixel 16, and then the gate signal line 17a in the lower half of the screen is simultaneously selected and the predetermined voltage (predetermined current) is selected. ) May be written to the pixel 16.

  The embodiments of FIGS. 14 and 34 are embodiments in which a predetermined voltage or a predetermined current for testing is written to the pixel row by the gate driver circuit 12. The gate driver circuit 12 is formed simultaneously with the transistor of the pixel 16 by polysilicon technology.

  FIG. 35 shows an embodiment in which probing pads Pa and Pb are formed at one end of the gate signal line 17 without using the gate driver circuit 12. A probe 234 or the like is brought into contact with the probing pads Pa and Pb, and a VGH voltage and a VGL voltage are applied. If the VGL voltage (selection voltage) is sequentially applied to the probing pads Pa1, Pa2,... And the VGH voltage (non-selection voltage) is applied to the non-selected probing pads Pa, the gate driver circuit 12a The same operation can be realized. Further, the selection voltage may be applied in a staggered pattern (pads Pa1, Pa3, Pa5,...).

  After the inspection of the EL display panel, a gate driver IC 12 made of a semiconductor is mounted on the end of the gate signal line 17.

  FIG. 36 shows an embodiment in which the probing pads Pa and Pb are individually formed on the gate signal lines 17a and 17b, the probe 234 and the like are brought into contact with each other, and the VGH voltage and the VGL voltage are applied. In this embodiment, a plurality of gate signal lines 17a are short-circuited by a short-circuit wiring 361 and a probing pad Pa is arranged. Further, in this embodiment, a plurality of gate signal lines 17b are short-circuited by a short-circuit wiring 362 and a probing pad Pb is arranged. By bringing the probe 234 or the like into contact with the probing pads Pa and Pb and applying the VGH voltage and the VGL voltage, the entire display screen 22 can be controlled on and off.

  By operating the test transistor 145, an image can be displayed on the display screen 22 without mounting the source driver IC 14. By displaying an image, it is possible to easily detect a point defect, a line defect, a color shift, and the like.

  In modes other than the inspection mode (during normal image display), the source terminal and the gate terminal of the test transistor 145 are electrically short-circuited as shown in FIG. By short-circuiting as shown in FIG. 17, the test transistor 145 becomes equivalent to a diode. Therefore, when the off voltage (VGH) is applied to the source terminal and the gate terminal of the test transistor 145, no voltage or current is applied from the test transistor 145 to the source signal line 18. Further, the diode composed of the test transistor 145 functions as a protection diode for electrostatic protection and functions as an element for protecting the EL display panel.

  As shown in FIG. 17, the test transistor 145 is diode-connected using the method shown in FIG.

  In the above embodiment, the P-channel test transistor 145 is formed on the source signal line 18, but the N-channel test transistor 145 may be formed on the source signal line 18. However, the channel polarity of the test transistor 145 may be matched with the channel polarity of the switching transistor 11c of the pixel 16 (a transistor that generates a current path with the pixel 16 by a current or voltage applied to the source signal line 18). preferable. This is because the test transistor 145 can be reliably turned off with a voltage that turns off the switching transistor 11c. As the test transistor 145, two transistors of P channel and N channel may be formed on each source signal line 18. By forming the test transistor 145 having two channel polarities, a voltage (current) more optimal for testing can be applied to the source signal line 18.

  An EL display device is completed by ACF-connecting a flexible substrate (flexible substrate) 161 to the array substrate 162 (EL display panel) (see also FIG. 25). A power supply IC 222, an EEPROM 253, a flash memory 252, and the like are mounted on a flexible substrate (flexible substrate) 161. The voltage VGH for turning off the test transistor 145 (or the voltage VGL when the test transistor 145 is an N-channel transistor) is supplied from the power supply IC 222.

  FIG. 37 is a cross-sectional view in which the terminals of the array substrate 162 and the flexible substrate 161 are connected by the ACF 371. The terminals 147 and 146 of the array substrate 162 and the short-circuit electrode wiring 165 of the flexible substrate 161 are connected by the ACF 371.

  The inspection mode of FIG. 14 is performed without connecting the flexible substrate (flexible substrate) 161 to the array substrate 162. Alternatively, the flexible substrate (flexible substrate) 161 is connected to the array substrate 162, but the source driver IC 14 is not mounted on the array substrate 162.

  In the inspection mode, probes are set on the transistor control terminal 147 and the signal input terminal 146 of the array substrate 162. A VGH or VGLt voltage is applied to the transistor control terminal 147.

  After the inspection, the flexible substrate (flexible substrate) 161 is ACF connected to the array substrate 162. The connection terminal 164 of the flexible substrate (flexible substrate) 161 and the connection terminal 163 of the array substrate 162 are connected. The transistor control terminal 147 and the signal input terminal 146 are electrically short-circuited by a short-circuit electrode terminal 165 of a flexible substrate (flexible substrate) 161. A VGH voltage is applied to the short-circuit electrode terminal 165. Since the power supply IC 222 is mounted on the flexible substrate (flexible substrate) 161, VGH is applied from the power supply IC 222 to the short-circuit electrode terminal 165.

  The short-circuit electrode terminal 165 corresponds to an example of the wiring short-circuit portion of the present invention.

  Although 161 is a flexible substrate (flexible substrate), this embodiment is not limited to this. For example, 161 may be a printed circuit board. In the present embodiment, the transistor control terminal 147 and the signal input terminal 146 are electrically connected to each other before shipment of the EL display device using the short-circuit electrode terminal 165 or the like. Therefore, the transistor control terminal 147 and the signal input terminal 146 may be electrically connected by another method. For example, the transistor control terminal 147 and the signal input terminal 146 may be electrically short-circuited by applying a copper paste. In this embodiment, the transistor control terminal 147 and the signal input terminal 146 are electrically set to the same potential before shipping the EL display device. In addition, the test transistor 145 is turned off. Therefore, a predetermined potential may be applied to each terminal of the test transistor 145 to turn off the test transistor 145. For example, a method of directly applying the VGH potential output from the power supply IC 222 to both the transistor control terminal 147 and the signal input terminal 146 is exemplified.

  The above embodiment has the pixel configuration of FIG. However, the present embodiment is not limited to the pixel configuration in FIG. For example, FIG. 21 is an example of the pixel configuration of FIG. As a matter of course, the present embodiment can also be implemented in the pixel configurations of FIG. 7A and FIG.

  FIG. 22 is an explanatory diagram of the power supply IC of this embodiment. By using the power supply IC of the present embodiment, inspection, aging, brightness adjustment, and the like can be easily realized.

A Vin voltage (voltage 2.3 V or more) is applied to the Vin terminal of the power supply IC 222. The power supply IC 222 generates all voltages necessary for the EL display device. As for the generated voltage, an anode voltage Vdd and a cathode voltage Vss are generated by a DCDC circuit. The DCDC circuit uses a coil Lp for the positive voltage Vdd. The negative voltage Vss uses the coil Ln. Vdd is common to the analog voltage Avdd of the source driver IC 14 (Vdd = Avdd). The driving transistor 11a of the pixel 16 is a P-channel transistor. By setting Vdd = Avdd, the gradation voltage potential and the anode potential Vdd change in conjunction with each other, so that a satisfactory gradation display can be realized.

  The power supply IC 222 generates the logic voltage Dvdd of the source driver IC by a linear regulator circuit. Dvdd = 1.85V. Further, the power supply (VGH, VGL) of the gate driver circuit 12 is generated by the charge pump circuit. The charge pump circuit uses a capacitor Cp for the positive voltage VGH. The charge pump circuit uses a capacitor Cn for the negative voltage VGL.

  Note that the voltage used in the gate driver circuit 12 such as VGH and VGL may be generated by a charge pump circuit formed in the source driver IC 14. In this case, an open switch is formed in the VGH and VGL output circuits of the source driver IC 14 (the source driver IC 14 has an output open function). In the following embodiments, it is assumed that the power supply IC 222 includes VGH and VGL voltage generation circuits. In the case where the VGL and VGH voltage generation circuits are provided in the source driver IC 14, this embodiment may be implemented even if the source driver IC 14 and the power supply IC 222 are synchronized.

  The present embodiment has an output open function in order to cope with adjustments such as an aging process, defect inspection, and luminance adjustment. As shown in FIG. 22, in the output open function, switches (SW1, SW2, SW3, SW4, SW5, SW6) are formed at the output stage of each voltage generation circuit. With the open function, another voltage can be applied to the output terminal of the power supply IC 222 by opening the switch SW (high impedance). For example, by setting Vdd = 5V and opening the switch SW2 of the Vdd output terminal, a voltage of 7V can be applied to the Vdd output terminal. By setting Vss = −3V and opening the switch SW1 of the Vss output terminal, a voltage of −5V can be applied to the Vss output terminal. By opening the switch SW of each terminal, the off-leakage current is configured to be 10 μA or less when an external voltage is applied to each terminal. This configuration can be realized by adopting a circuit configuration in which a voltage is applied to the gate terminal of the FET constituting each switch SW via a buffer circuit.

  The switch SW1 has a function of opening the Vss voltage (high impedance). The switch SW2 has a function of opening the Vdd voltage (high impedance), and the switch SW3 has a function of opening the Avdd voltage (high impedance). Similarly, the switch SW4 opens the Dvdd voltage (high impedance), and the switch SW5 opens the VGH voltage (high impedance). The switch SW6 has a function of opening the VGL voltage (high impedance).

  Note that the switches (SW1 to SW6) need not clearly form a switch circuit. For example, if the Vdd output is equivalently opened by stopping the oscillation voltage applied to the Vdd generation circuit 221b, the physical formation of the switch SW2 is not necessary.

  The output circuit of the power supply voltage includes a transistor (FET), and a predetermined voltage is generated by resonating with the FET, diode, and external coil (L). By applying an OFF voltage to the gate terminal of the FET to be resonated or opening it, no voltage is output from the FET. As a result, the output terminal of the corresponding power supply IC 222 is open (high impedance). Further, a reverse bias may be applied to a diode built in the power supply IC 222 to turn off the diode.

  That is, the function of making the open (high impedance) of the present embodiment equivalently needs only to be a function of setting the terminal of the power supply IC 222 to a high impedance state when viewed from the outside. Further, any configuration that can apply another voltage from the outside to the output terminal of the power supply IC 222 when it is in the high impedance state or in the high impedance state is sufficient.

  The power supply IC 222 of the present embodiment incorporates a negative power supply side diode and FET. Further, a standard data bus such as SMBus is provided, and an output voltage or the like can be varied or set by a command transmitted to the standard data bus.

  The voltages that can be set by the command are the VGH voltage, the VGL voltage, and the Vss voltage. These voltages are configured so that they can be set with 0.5V knurling. The variable voltage can be easily realized by providing a DA converter circuit in the power supply IC 222. The output open function can also be controlled by a command. For example, the Vss voltage terminal can be opened by command control via a standard data bus (SMBus or the like).

  The output open function may be turned on / off under the control of the hardware terminal. For example, the first pin of the power supply IC 222 is TEST1, and the second pin is TEST2. By setting TEST1 to 'H', the Vdd terminal and the Vss terminal are brought into the output open state. By setting TEST1 to 'L', the Vdd terminal and the Vss terminal are set to the voltage output state. By setting TEST2 to 'H', the VGH terminal and the VGL terminal are brought into the output open state. By setting TEST2 to 'L', the VGH terminal and the VGL terminal are set to the voltage output state. Further, by setting logic voltages to a plurality of pins, the VGH voltage is set to any voltage from 5.0 V to 8.0 V and can be output from the terminal.

  The VGH voltage is not less than 5.0V and not more than 9V, and this range can be set with 0.5V scratches. The VGL voltage is not less than −6.0 V and not more than −0.5 V, and this range can be set with 0.5 V knurling. The Vss voltage is −6.0 V or more and −0.5 V or less, and this range can be set with 0.5 V knurling.

  In addition, the power supply IC 222 of this embodiment can also set the oscillation frequency of the DCDC circuit. The oscillation frequency is selected from a plurality of 0.6 KHz and 1.2 KHz. The oscillation frequency can also be easily realized by selecting one from a plurality of resistors built in the power supply IC 222. A discharge circuit is formed at the output of each power source.

  The On / Off terminal is a terminal for starting the power supply IC. When a clock signal is applied to the On / Off terminal, a Dvdd voltage is output. The clock signal detects the rising or falling edge of the signal, and outputs Dvdd when the rising or rising edge of the clock signal is detected a plurality of times. As the clock signal, a video signal clock or a horizontal synchronization signal HD applied to the EL display device of this embodiment is used. The video signal is generated by a graphic controller of a device in which the EL display device of this embodiment is incorporated.

  When Dvdd is activated, the logic circuit unit of the source driver IC 14 is activated, and data can be sent to a standard data bus such as SMBus. The source driver IC 14 sets values of voltages (VGH, VGL, Vss) output from the power supply IC 222 using a standard data bus (SMBus or the like). Also, set the oscillation frequency. In addition, Avdd (Vdd), VGH, and VGL are output from the power supply IC 222.

  The power supply IC 222 is mounted on a flexible substrate (flexible substrate) 161 as shown in FIG. In this state, the terminals (signal input terminal 146 and transistor control terminal 147) of the array substrate 162 are short-circuited by the short-circuit electrode terminal 165 of the flexible substrate (flexible substrate) 161. Further, a VGH voltage (an off voltage of the test transistor 145) is applied to the short-circuit electrode terminal 165. Gold bumps are formed on each output terminal of the power supply IC 222 and are flip-chip mounted by ACF (connection by anisotropic conductive film). Note that reference numeral 254 in FIG. 25 denotes a test transistor group. A test transistor 145 is formed on each source signal line 18. As shown in FIGS. 23 and 24, the test transistor 145 may be formed on the opposite side (position B) where the source driver IC 14 is mounted. The source driver IC 14 is not limited to an IC, and may be a source driver circuit formed by a low-temperature polysilicon technique or the like.

  The switches SW3, SW4, and SW6 are not actually formed. Or it can be omitted. Dvdd = 1.85 V is output by the clock signal of the video signal. Therefore, the switch SW4 is not necessary. AVdd is also output simultaneously with the oscillation of the DCDC circuit. AVdd is an analog power supply for the source driver IC 14 and also a power supply voltage for the internal shift register of the gate driver circuit 12.

  An on / off control signal for each power source is sent from the source driver IC 14 to the power source IC 222 via a standard data bus such as SMBus or I2CBus. By the command ON1, the VGH switch SW5 and the VGL switch SW6 are turned on. When the switches SW5 and SW6 are turned on, VGH and VGL (VGL1) are output, and the gate driver circuit 12 operates. The start pulse (ST1, ST2), clock (CLK1, CLK2), and up / down (UD) applied to the gate driver circuit 12 are controlled by the source driver IC. In particular, the internal shift register of the gate driver circuit 12b is cleared, and all the gate signal lines 17b are in a non-selected state.

  Next, the Vdd switch SW2 and the Vss switch SW1 are turned on by the command ON2. When the switches SW2 and SW1 are turned on, the anode voltage Vdd and the cathode voltage Vss are output.

  A voltage Vin from the battery of the main body is supplied to the power supply IC 222. The Vin voltage is supplied to the power supply IC 222 via the connector 251. The power supply IC 222 generates a voltage (anode voltage Vdd, cathode voltage Vss, VGH, VGL, AVdd, Dvdd = 1.85 V) necessary for the EL display panel from one Vin voltage. The flexible substrate 161 and the array substrate 162 are connected by an ACF (differential conductive film). That is, since the flexible substrate 161 and the array substrate of the EL display device 162 are bonded together, a connector is not necessary to apply the voltage output from the power supply IC 222 to the EL display panel 162.

  FIG. 38 is a block diagram of a conventional EL display device. The flexible substrate 161 and the array substrate 162 are ACF-connected. The power supply IC 222 is mounted on the printed circuit board 381 of the main body. A battery voltage Vin is applied to the power supply IC 222. The power supply IC 222 generates a voltage (anode voltage Vdd, cathode voltage Vss, VGH, VGL, AVdd, Dvdd = 1.85 V) necessary for the EL display panel from one Vin voltage. The generated voltages (anode voltage Vdd, cathode voltage Vss, VGH, VGL, AVdd, Dvdd = 1.85 V) are delivered to the flexible substrate 161 via the connector 251 and supplied to the EL display panel. Accordingly, the required number of pins of the connector 251 is multi-pin since there are many types that the power supply IC 222 generates. The source driver IC 14 outputs a signal for turning on and off the power supply IC 222. The connector also requires pins for this signal.

  From the above, in the conventional configuration (configuration in which the power supply IC 222 is mounted on the printed circuit board 381 of the main body), the number of pins required for the connector 251 is larger than that in the configuration of the present embodiment (FIG. 25). Therefore, poor contact is likely to occur and the cost is increased.

  The voltage generated by the power supply IC 222 has a certain range of variation. For example, even if Vdd = 5.5V is an ideal value, a variation of about ± 0.2V occurs. When the voltage output from the power supply IC 222 changes, the light emission luminance of the EL display panel changes. For example, it is assumed that the display brightness is adjusted with an ideal anode voltage of 5.5 V in the EL display panel by the adjustment method of the present embodiment described above. However, in the conventional configuration shown in FIG. 38, since the printed circuit board 381 of the main body is connected to the flexible circuit board 161 after adjusting the display brightness, if the anode voltage Vdd output from the power supply IC 222 mounted on the printed circuit board 381 is 5.7V. The light emission luminance of the EL display panel deviates from the adjusted value.

  That is, in the configuration of FIG. 38, the adjustment is effective if the voltage output from the power supply IC 222 is an ideal value (in this example, the anode voltage is 5.5 V), but unless the voltage output from the power supply IC 222 is an ideal value, Even if the adjustment is made on the EL display panel, the adjustment becomes meaningless.

  In this embodiment and other examples of FIG. 25, the power supply IC is mounted on the flexible board 161, and the power supply IC 222 is operated to perform brightness adjustment, white balance adjustment, and the like. Therefore, even if the generated voltage of the power supply IC 222 varies individually, there is no problem because the EL display panel is adjusted in consideration of the variation. Also in aging and the like, aging can be favorably performed by using voltages VGH and VGL that are actually used.

  In particular, in this embodiment, the power supply IC 222 and the EL display panel are integrally operated (simultaneously operated), and adjustment, aging, and the like are performed. In the EL display device of this embodiment, a power supply IC 222 and an EL display panel are integrated (completion of connection).

  By configuring in this way, the number of pins of the connector 251 is reduced and cost reduction can be realized. Also, ideally, brightness variation and white balance adjustment can be realized. In order to realize this, the present embodiment effectively uses the output open function of the power supply IC 222.

  In the above embodiment, the output open function is mounted on the power supply IC 222. However, the present embodiment is not limited to this. For example, an analog switch and a relay circuit may be arranged between the anode output terminal of the power supply IC 222 and the anode wiring 231 of the EL display panel. That is, a switch circuit or the like may be disposed or formed outside the power supply IC 222.

  The source driver IC 14 displays an image by controlling start pulses (ST1, ST2), clocks (CLK1, CLK2), and up / down (UD) applied to the gate driver circuit 12. One start signal ST1 is applied to the gate driver circuit 12a in one frame period, and a start pulse ST2 is applied to the gate driver circuit 12b so as to correspond to the duty drive.

  FIG. 23 and FIG. 24 are explanatory diagrams of an inspection and adjustment method for an EL display device using the open function of the power supply IC of this embodiment. Also in the following examples, the pixel configuration will be described with reference to FIG. 1, but this embodiment is not limited to this, and the current driving pixel configuration in FIG. 7, the voltage driving in FIG. Any pixel configuration may be used.

  FIG. 23 shows a method for adjusting the luminance, white balance, and contrast of an EL display device. In FIG. 23, the switch SW1 is opened using the open function of the power supply IC 222 of the present embodiment. That is, the cathode voltage Vss is not output, and the output terminal is in a high impedance state. The probe 234 is used to probe the pad P1 of the output terminal of the cathode voltage Vss. An ammeter 233 for measuring current is disposed between the probe 234 and the external power supply Vsst. Note that the cathode voltage Vsst at the time of adjustment = the cathode voltage Vss at the time of image display.

  When the driving transistor 11a of the pixel 16 is a P-channel transistor, the cathode electrode is opened and the current of the cathode wiring 232 is measured. When the driving transistor 11a of the pixel 16 is an N-channel transistor, the anode electrode is opened and the current of the anode wiring 231 is measured.

  The source driver IC 14 controls the gate driver circuit 12 to enter an image display state. The magnitude of the reference current Ic is assumed to be one time as normal. As described with reference to FIG. 9, the light emission luminance of the display screen 22 changes in proportion to the magnitude of the reference current Ic. This is because the transistor 94b and the unit transistor 102 constitute a current mirror circuit. The transistor 94b includes a plurality of transistors. When the magnitude of the reference current changes from 1 to 2, the brightness of the display screen 22 is doubled. The power used on the display screen 22 is also doubled.

  In the EL display device of the present embodiment, the cathode current Is of the display screen 22 flows through the cathode wiring 232. The anode current on the display screen 22 flows through the anode wiring 231.

  In the configuration of FIG. 23, the cathode voltage output terminal of the power supply IC 222 is open and the external cathode voltage Vsst is connected, so that the current flowing through the cathode wiring 232 is externally connected via the probe 234 and the ammeter 233. It flows to the cathode voltage Vsst. Therefore, the ammeter 233 can measure the current used on the display screen 22. The cathode current Is is measured because the current flowing through the cathode wiring 232 is the current flowing through the display screen 22. Part of the anode current Ip flowing through the anode wiring 231 flows as a program current in the source driver IC 14.

  In the EL display device, the magnitude of the cathode current Is and the light emission luminance have a proportional relationship. Therefore, the light emission luminance of the display screen 22 can be grasped by measuring the cathode current. From the above, the light emission luminance of the display screen 22 can be adjusted by adjusting the cathode current to be a predetermined current.

  In the example of FIG. 23, the cathode current flowing through the entire display screen 22 is measured, but the present embodiment is not limited to this. For example, the cathode current of a pixel included in a part of the display screen 22 or a predetermined area may be measured. With this cathode current, it is possible to estimate the cathode current flowing through the entire display screen 22, and in the white raster display, the entire screen is displayed with the same luminance. Because it is easy. Further, the characteristic distribution of the display screen 22 can be measured by dividing the display screen 22 by a predetermined area and measuring the cathode current in each divided region. Examples of the division include a pixel column, a pixel row, and a matrix shape. This embodiment is also described in FIG. 26, FIG. 27, FIG.

  A case where the pixel 16 is a current programming method will be described. The adjustment of the magnitude of the cathode current Is (adjustment of display brightness) is performed by setting the gradation number (the magnitude of the video signal) of the video signal applied to the display screen 22 to a constant value and changing the magnitude of the reference current. By doing. The fixed value for setting the gradation number of the video signal (the magnitude of the video signal) is usually the maximum gradation number. When the magnitude of the reference current is increased, the cathode current Is is also increased and the light emission luminance is increased. Therefore, the magnitude of the cathode current Is is measured by the ammeter 233, and the adjustment is completed when the current reaches a predetermined value. By performing the above in RGB, white balance can be adjusted. A reference current that has been subjected to white balance adjustment (luminance adjustment) is defined as Ik. The reference current Ik is individually set in RGB (Ikr for red (R), Ikg for green (G), and Ikb for blue (B)).

  Next, the case where the pixel 16 is a voltage program system will be described. Adjustment of the magnitude of the cathode current (adjustment of display luminance) is performed by setting the gradation number (the magnitude of the video signal) of the video signal applied to the display screen 22 to a constant value, and the amplitude adjustment register 111 described with reference to FIG. This is done by controlling The gradation amplifiers 112H and 112L are changed under the control of the amplitude adjustment register 111. When the gradation amplifier 112H is made high (close to the Vdd voltage), the black level corresponding to the low gradation can be adjusted. When the gradation amplifier 112L is lowered (close to the GND voltage), the white level corresponding to the high gradation can be adjusted. In this embodiment, the output gradation is set to the maximum gradation, and the gradation amplifier 112L is changed. The value of the gradation amplifier 112L is adjusted so that the value of the cathode current becomes a desired value.

  If the gradation amplifier 112L is lowered, the cathode current Is also increases and the light emission luminance increases. Therefore, the magnitude of the cathode current is measured by the ammeter 233, and the adjustment is completed when the current reaches a predetermined value. By performing the above in RGB, white balance can be adjusted.

  Note that the voltages VGH, VGL, and Vdd output from the power supply IC 222 are set to normal display voltages. Further, in this embodiment, the gate driver circuit 12a is operated with the VGH1 and VGL1 voltages, and the gate driver circuit 12b is operated with the VGH2 and VGL2 = GND voltages, and VGH1 = VGH2.

  With the above adjustment, white balance adjustment can be realized, and light emission luminance adjustment of the display screen 22 can be realized. The contrast adjustment of the EL display device can be realized by adjusting the cathode current that flows during black display.

  First, the case where the pixel 16 is a current programming method will be described. In the adjustment of the magnitude of the cathode current Is (adjustment of display luminance), the gradation number (the magnitude of the video signal) of the video signal applied to the display screen 22 is set to a constant value.

  The magnitude of the reference current is maintained while maintaining (holding) the set value Ik (Ikr for red (R), Ikg for green (G), and Ikb for blue (B)) adjusted for white balance.

  The gradation number of the video signal at the black level (the magnitude of the video signal) is the lowest gradation. In current driving, the program current is 0 at the lowest gradation. The black level is adjusted by applying a voltage of the lowest gradation from the voltage generation circuit of FIG. The lowest gradation voltage is obtained by changing the potential output from the gradation amplifier 112H. In this state, the magnitude of the cathode current is measured with an ammeter 233, and the adjustment is completed when the current reaches a predetermined value.

  Next, the case where the pixel 16 is a voltage program system will be described. Adjustment of the magnitude of the cathode current Is (adjustment of display luminance) is performed by setting the lowest gradation number applied to the display screen 22 and controlling the amplitude adjustment register 111 described with reference to FIG. The gradation amplifier 112H is changed under the control of the amplitude adjustment register 111. When the gradation amplifier 112H is increased (close to the Vdd voltage), the cathode current Is at the black level decreases. When the gradation amplifier 112H is lowered, the cathode current increases. The adjustment is completed when the value of the cathode current Is reaches a desired value.

  The EL display device according to the present embodiment includes both the current drive circuit of FIGS. 9 and 10 and the voltage output circuit of FIGS. 11 and 12. When both the current driving circuit and the voltage output circuit are provided, a program voltage is applied from the voltage output circuit to the pixel 16 in the first half of one horizontal scanning period (period for selecting one pixel row), and one horizontal scanning period (one pixel). A program current is applied to the pixel 16 from the current driving circuit in the latter half of the period during which a row is selected. Each pixel has a determination circuit (not shown) for applying a program voltage, a program current, or both a program voltage and a program current. Whether the determination circuit applies a program voltage or a program current to each pixel based on the magnitude (gradation number) of the video signal and the magnitude (gradation number) of the video signal applied to the source signal line. Alternatively, it is determined whether to apply both the program voltage and the program current.

  In FIG. 23, the cathode current is measured by the ammeter 233, but the present embodiment is not limited to this. For example, a pickup resistor may be arranged in series on the current path of the cathode current, and the terminal voltage of the pickup resistor may be measured with a voltmeter.

  In FIG. 23, the cathode terminal of the power supply IC 222 is opened and the cathode current is measured. However, the present embodiment is not limited to this. The anode terminal of the power supply IC 222 may be opened and the anode current may be measured. The above matters are the same in FIG.

  The technical idea of the present embodiment is to measure or acquire the current flowing through the cathode wiring or the anode wiring to obtain a predetermined value. Further, the technical idea of the present embodiment is that the power supply IC 222 is mounted on a flexible substrate (flexible substrate) 161 or the like, and a wiring (cathode wiring or anode wiring) for supplying a current flowing through the EL element 15 and a power supply In this method, panel inspection, evaluation, aging, and the like are performed while the output terminal of the IC 222 is connected. The output open function of the power supply IC 222 is used, and a voltage is supplied to the panel from the outside to the opened terminal. Each terminal of the power supply IC 222 changes and outputs a voltage value using a standard data bus (SMBus or the like) as necessary. A test transistor 145 is used.

  FIG. 24 is an explanatory diagram of an aging method. In the aging process, the display screen 22 of the EL display device is caused to emit light with a brightness higher than the normal display brightness. As an example, the light emission luminance of the display screen 22 is set to double or quadruple luminance. This is because initial deterioration of the EL element is caused and 'burning' is suppressed.

  The display brightness is set to 2 times or 4 times by changing the reference current. The reference current setting value Ik (red (R) is Ikr, green (G) is Ikg, blue (B) is Ikb) is adjusted to be doubled or quadrupled. For example, to double the display brightness, the reference current Ik × 2 is used. The set value of the reference current n times (n is a real number from 1 to 4) used during aging is Ikm (red (R) is Ikmr, green (G) is Ikmg, and blue (B) is Ikmb).

  When the reference current is increased, the current (anode current Ip, cathode current Is) flowing through the anode wiring 231 and the cathode wiring 232 increases. When the anode current Ip and the cathode current Is increase, the voltage between the terminals of the EL element 15 and the channel voltage of the driving transistor 11a increase.

  During aging, the reference current is set larger than that during normal display. Therefore, the anode voltage Vdd is increased (for example, 5 V (Vdd) is set to 7 V (Vddt) during normal image display) and the cathode voltage Vss is decreased (for example, −3 V (Vss) during normal image display). -5V (Vsst) when aging). When the anode voltage is increased, the voltages (VGH1, VGL1) applied to the gate signal line 17a also need to be changed. VGH1 voltage is increased (for example, VGH = 6.5V during normal image display is set to 7.5V during aging), and VGL1 voltage is decreased (for example, VGL1 = −3V during normal image display is −5V during aging) ).

  At the time of aging, when the pixel configuration is current drive (FIGS. 1 and 7), the reference current is set to Ikm, and an image (white raster) is displayed by the current drive method. When the pixel configuration is voltage driven (FIG. 8), the amplitude adjustment register 111 is controlled to lower the potential of the gradation amplifier 112L (close to GND or lower than GND), so that white raster display is performed.

  The power supply IC 222 supplies VGL, VGH, Avdd, and Dvdd to the EL display panel. Vddt and Vsst are supplied from an external power source. During aging, the brightness of the display screen 22 is monitored by a photosensor, and aging is terminated when a certain value is lowered from the initial brightness.

  As described above, the power supply IC according to the present embodiment has an open (high impedance) function of the voltage output terminal. In an aging process or the like, the output terminal is opened, and another power supply voltage is applied to the opened terminal for aging. Further, an ammeter is connected to the open terminal, and white balance adjustment and display brightness adjustment are performed by measuring a current flowing between predetermined power supply voltages.

  In the above embodiment, Vdd and Vss are supplied from the outside, and VGH and VGL are supplied from the power supply IC 222 by changing the output voltage. However, the present embodiment is not limited to this. For example, Vdd, Vss, VGH, and VGL may be supplied from the outside, and only Avdd and Dvdd may be supplied from the power supply IC 222.

  14, 18, and 20 are examples in which a test transistor 145 is formed on the source signal line 18. The test transistor 145 may be formed in the cathode wiring 232 or the anode wiring 231 as illustrated in FIG. By turning on the test transistor 145, a current flows through the cathode wiring 232, and the flowing current can be measured with an ammeter 233. A video signal (program current or program voltage) is applied to the source signal line 18 from the source driver circuit 14.

  A shift register 333 (see FIG. 33 and the like) is added to the gate terminal of the test transistor 145 in the same manner as the gate driver circuit 12, and one or more test transistors 145 are sequentially selected by the function of the shift register 333. You may comprise.

  With the above configuration, the test transistor 145 can be controlled on and off independently. Accordingly, by turning on / off the test transistor 145 separately from the gate driver circuit 12a, the pixels 16 arranged in a matrix form can be individually or selected in units of pixel columns, and the cathode current or the anode current can be measured or controlled. . Needless to say, the test transistor 145 may be formed on the anode wiring 231. Needless to say, the test transistor 145 may be formed on any two or more of the anode wiring, the cathode wiring, and the source signal line 18. The above can be similarly applied to other examples of the present embodiment.

  In FIG. 19, the characteristics of the pixel 16 can be measured or grasped by using the power supply IC 222 of this embodiment.

  The driving transistor 11a of the pixel 16 has the characteristics shown in FIG. The driving transistor 11a will be described as a P-channel transistor. In FIG. 31, the horizontal axis represents the gate terminal voltage of the driving transistor 11a. The vertical axis represents the current flowing between the channels of the transistor (current flowing in the EL element 15). If the gate terminal voltage is V1, the current is I1. If the gate terminal voltage is V0, the current is zero. That is, if the current I1 is passed, the gate terminal voltage becomes V1. Conversely, if V1 is applied to the gate terminal, the output current becomes I1.

  For example, a constant current I1 such as 1 μA or 0.5 μA is supplied from the source driver circuit (IC) 14 to the specific driving transistor 11a of FIG. 31A, and the gate terminal voltage of the driving transistor 11a of the pixel 16 is set. taking measurement. The measured characteristic curve of the V1 driving transistor 11a is obtained, and voltage program data corresponding to each gradation is created. The characteristic curve is a substantially square curve. As final data, V0 at which the current becomes 0 is obtained. This V0 is held as characteristic variation data of each pixel in a ROM such as a flash memory. The gradation data of the video signal is added to or calculated from the held V0 data to generate a video signal (program voltage or program current) that takes into account the pixel characteristic variation (characteristic variation of the driving transistor 11a). The generated video data program voltage or program current is applied to the corresponding pixel. Therefore, display defects due to characteristic variations of the driving transistor 11a are not displayed.

  Further, as shown in FIG. 31B, the grayscale voltage may be obtained from V2 and V1 by supplying the I2 current to the driving transistor 11a of the pixel 16 and measuring the gate terminal voltage V2 with respect to the I2 current. . That is, the potential of the source signal line 18 is measured from at least one constant current (including current 0), and a voltage (program voltage) corresponding to the gradation is obtained from the measured potential. Alternatively, a predetermined voltage (V2, V1) is applied to the gate terminal of the driving transistor 11a, and the specification of the driving transistor 11a is estimated or obtained from the output current (I2, I1), and is stored in the memory as V0 data. A video signal (program voltage or program current) is obtained from the stored data.

  FIG. 32 is an explanatory diagram of a method of correcting the video data DATA from the acquired V0 voltage and obtaining an appropriate video signal (program voltage or program current). The V0 voltage can be considered as a correction amount indicating the characteristic variation of the driving transistor 11a of the pixel 16.

  The magnitude V0 to be corrected is held in the flash memory 252. The ROM data of the flash memory 252 can be rewritten from the outside as RDaTa.

  The data held in the flash memory 252 is also 8 bits. The ROM data of the flash memory 252 and the gradation data DATA are added by an addition (may be subtracted) circuit 321. Generally, the gradation data DATA is shifted to the anode voltage side by the correction data V0 by the addition process.

  The added data becomes 9 bits. This data is temperature-compensated by a temperature compensation circuit 323 that detects the panel temperature, and is applied to the source driver circuit (IC) 14. The reason why the temperature compensation circuit 323 is required is that the correction data stored in the flash memory 252 has temperature dependency.

  As described above, the characteristic variation of the driving transistor 11a can be obtained by applying a constant voltage to the gate terminal of the driving transistor 11a and measuring the current output from the driving transistor 11a. When the acquired characteristic variation data is stored as compensation data in the flash memory 252 or the like, and the gradation data input from the outside of the EL display device is corrected using the compensation data of the flash memory 252, the driving transistor 11a of the pixel 16 is corrected. Therefore, a good image display can be realized.

  FIG. 26 is an explanatory diagram of a method for measuring or acquiring the characteristics of the pixel 16. The Vss output terminal of the power supply IC 222 is opened, and the probe 234 is connected to the terminal pad P1. The anode voltage Vdd is supplied from the power supply IC 222. The test cathode voltage Vsst and the anode voltage Vdd are set to voltage values for performing normal image display.

  In this state, the source driver circuit 14 outputs a predetermined voltage V 1 to each source signal line 18. Further, an on voltage (VGH) for turning on the N-channel transistor 11 b is applied to the gate signal line 17 (1), and an off voltage (VGL) is applied to the other gate signal line 17. As described with reference to FIG. 31, when a voltage of V1 is applied to the gate terminal of the driving transistor 11a, a current having a magnitude of I1 is output. Assuming that m pixels 16 are arranged in one pixel row, a current of m × I1 is output to the cathode wiring 232 when the V1 voltage is applied to each source signal line 18. However, actually, there is a variation in pixel characteristics within the surface of the display screen 22, and the current flowing through the cathode wiring 232 does not become m × I 1.

  In the present embodiment, the voltage V1 applied to each source signal line 18 is changed, and the current flowing through the cathode wiring 232 is adjusted to be m × I1. The voltage when this m × I1 is reached is Vx. This voltage Vx indicates the characteristics of the selected one pixel row. The Vx voltage is subjected to AD conversion (analog-digital conversion), subjected to a predetermined calculation process to become correction data, and the correction data is stored in the flash memory 252.

  Next, an off voltage (VGL) for turning off the N-channel transistor 11b is applied to the gate signal line 17 (1), an on voltage (VGH) is applied to the gate signal line 17 (2), and another gate signal line 17 is applied. An off-voltage (VGL) is applied to.

  In this state, a predetermined voltage is output from the source driver circuit 14 to each source signal line 18. The voltage V1 applied to each source signal line 18 is changed, and the current flowing through the cathode wiring 232 is adjusted to be m × I1. The voltage when m × I1 (m is an integer and the number of pixels in one pixel row) is Vx. This voltage Vx indicates the characteristics of the selected pixel row of the second pixel row. The Vx voltage is subjected to AD conversion (analog-digital conversion), subjected to a predetermined calculation process to become correction data, and the correction data is stored in the flash memory 252. The above operation is performed up to the last pixel row.

  As described above, the characteristics of all the pixel rows are selected by sequentially selecting the pixel rows and adjusting the voltage applied from the source driver circuit 14 to each source signal line 18 so that the current flowing through the cathode wiring 232 becomes a constant value. Variations can be acquired. The acquired data is subjected to arithmetic processing and the like to be corrected data and stored in the flash memory 252. In the subsequent processing, the method described with reference to FIGS. 31 and 32 is performed, and thus description thereof is omitted.

  In the above embodiment, the characteristic variation of the pixel 16 or the pixel row is measured, but it can also be applied to the inspection method. In the embodiment of FIG. 26, the V1 voltage is applied to each source signal line 18, the V1 voltage is adjusted so that the current flowing through the cathode wiring 232 becomes a predetermined value, and the Vx voltage indicating the characteristic is acquired. there were. However, even if the V1 voltage is changed within a certain range, the current flowing through the cathode wiring 232 may not reach a predetermined value. In this case, the pixel 16 is almost always defective. Therefore, when the voltage applied to the source signal line 18 is out of the range, it is possible to detect that a defect or the like of any pixel 16 in the selected pixel row has occurred. The degree of defects can also be grasped by the size of the voltage variable range.

  For example, the first voltage V1 = 2.0V and the variable range is ± 0.5V. If the current flowing through the cathode wiring 232 in the range of 1.5V to 2.5V cannot be set to m × I1, it is assumed that a defect has occurred. Further, the variable range is set to ± 0.8 V, and even in this range, it is assumed that a serious defect has occurred if the current flowing through the cathode wiring 232 cannot be set to m × I1. Needless to say, the above items can also be applied to FIG.

  FIG. 26 shows a system using the source driver IC 14 as means for applying a voltage to the source signal line 18. FIG. 27 shows an embodiment in which a test transistor 145 is used instead of the source driver IC 14. By using the test transistor 145, it is possible to apply a voltage to each source signal line 18 without using the source driver IC 14.

  FIG. 27 is an explanatory diagram of a method for measuring or acquiring the characteristics of the pixel 16 as in FIG. Also, defect inspection can be realized as in FIG. The Vss output terminal of the power supply IC 222 is opened, and the probe 234 is connected to the terminal pad P1. The anode voltage Vdd is supplied from the power supply IC 222. The test cathode voltage Vsst and the anode voltage Vdd are set to voltage values for performing normal image display.

  In this state, a predetermined voltage V1 is applied to the terminal 146, and a V1 voltage is applied to each source signal line 18 via the test transistor 145. Further, an on voltage (VGH) for turning on the N-channel transistor 11 b is applied to the gate signal line 17 (1), and an off voltage (VGL) is applied to the other gate signal line 17. As described with reference to FIG. 31, when a voltage V1 is applied to the gate terminal of the driving transistor 11a, a current having a magnitude of I1 is output. However, actually, there is a variation in pixel characteristics within the surface of the display screen 22, and the current flowing through the cathode wiring 232 does not become m × I 1.

  The voltage V1 applied to each source signal line 18 through the test transistor 145 is changed, and the current flowing through the cathode wiring 232 is adjusted to m × I1. The voltage when this m × I1 is reached is Vx. This voltage Vx indicates the characteristics of the selected one pixel row. The Vx voltage is subjected to AD conversion (analog-digital conversion), subjected to a predetermined calculation process to become correction data, and the correction data is stored in the flash memory 252. Hereinafter, since it is the same as that of FIG. 26, description is abbreviate | omitted.

  In the example of FIGS. 26 and 27, the characteristic variation of the driving transistor 11 a or the pixel 16 is obtained by measuring the current flowing through the cathode wiring 232. However, the present embodiment is not limited to this. By measuring the current flowing through the anode wiring 231, the characteristic variation of the driving transistor 11 a or the pixel 16 may be obtained.

  The characteristic variation is also caused by measuring the gate terminal voltage of the driving transistor 11a in a state in which a constant current is passed through the driving transistor 11a and the constant current is flowing, thereby causing the characteristic variation of the driving transistor 11a or the pixel 16 to vary. You can ask for it. For example, in the configuration of FIG. 33, the test transistor 145 is configured to be able to be turned on and off independently via the shift register circuit 333 and the like. The anode voltage Vdd is set to a constant voltage. An on voltage (VGH) for turning on the N-channel transistor 11 b is applied to the gate signal line 17 (1), and an off voltage (VGL) is applied to the other gate signal line 17. In this state, the test cathode voltage Vsst is operated so that the current flowing through the cathode wiring 232 becomes a predetermined value. The predetermined value is a current value for one selected pixel row.

  In FIG. 33, 333 is a shift register circuit, but this has a function of selecting the test transistor 145 (turning on the test transistor 145). Accordingly, it has a function of sequentially selecting one test transistor 145. Further, it has a function of selecting an arbitrary test transistor 145. Further, the number of test transistors 145 to be selected is not limited to one. A plurality of test transistors 145 may be selected simultaneously. For example, a method of selecting the red (R) pixel 16 and deselecting the GB pixel is exemplified.

  With the cathode current at a predetermined value, the test transistor 145 (1) is turned on, and the other test transistors 145 are kept off. By turning on the test transistor 145 (1), the gate terminal voltage of the driving transistor 11a of the pixel 16 (11) is output to the terminal 146. The voltage output to the terminal 146 is subjected to AD conversion (analog-digital conversion) and becomes data indicating the characteristic variation of the pixel 16 (11).

  Next, by turning on the test transistor 145 (2) and turning off the other test transistors 145, the gate terminal voltage of the driving transistor 11 a of the pixel 16 (12) is output to the terminal 146. The voltage output to the terminal 146 is subjected to AD conversion (analog-digital conversion) and becomes data indicating the characteristic variation of the pixel 16 (12).

  Similarly, with the gate signal line 17 (1) selected, the test transistors 145 are sequentially turned on and the other test transistors 145 other than one test transistor 145 are turned off, whereby the gate of the driving transistor 11 a of the pixel 16 is turned on. The terminal voltage is output to the terminal 146. The voltage output to the terminal 146 is subjected to AD conversion (analog-digital conversion) and becomes data indicating the characteristic variation of each pixel 16.

  When the test transistor 145 (m) is completed, the gate signal line 17 (2) is selected, and an off voltage (VGL) is applied to the other gate signal lines 17.

  In this state, the test cathode voltage Vsst is operated in the same manner as in the first pixel row so that the current flowing through the cathode wiring 232 becomes a predetermined value.

  With the cathode current at a predetermined value, the test transistor 145 (1) is turned on, and the other test transistors 145 are kept off. By turning on the test transistor 145 (1), the gate terminal voltage of the driving transistor 11a of the pixel 16 (21) is output to the terminal 146. The voltage output to the terminal 146 is subjected to AD conversion (analog-digital conversion) and becomes data indicating the characteristic variation of the pixel 16 (21).

  Next, by turning on the test transistor 145 (2) and turning off the other test transistors 145, the gate terminal voltage of the driving transistor 11 a of the pixel 16 (22) is output to the terminal 146. The voltage output to the terminal 146 is subjected to AD conversion (analog-digital conversion) and becomes data indicating the characteristic variation of the pixel 16 (22).

  Similarly, with the gate signal line 17 (2) selected, the test transistors 145 are sequentially turned on and the other test transistors 145 other than one test transistor 145 are turned off, whereby the gate of the driving transistor 11a of the pixel 16 is turned on. The terminal voltage is output to the terminal 146. The voltage output to the terminal 146 is subjected to AD conversion (analog-digital conversion) and becomes data indicating the characteristic variation of each pixel 16.

  As described above, by sequentially selecting pixels and measuring the gate terminal voltage of the driving transistor 11a of the pixel 16, it is possible to obtain the characteristic variation of all the pixels. The acquired data is subjected to arithmetic processing and the like to be corrected data and stored in the flash memory 252. In the subsequent processing, the method described with reference to FIGS. 31 and 32 is performed, and thus description thereof is omitted.

  In FIG. 33, the current of the cathode wiring 232 is measured, and the pixel also has a voltage-driven pixel configuration. 39 measures the current of the anode wiring 231 and the pixel has the current-driven pixel configuration described in FIG. The method (operation) of FIG. 39 is the same as that of FIG. As described above, this embodiment can cope with any pixel configuration.

  26 and 33 have been described as being applicable to an inspection method. The method described in FIG. 33 can also be applied to the inspection method.

  In the embodiment of FIG. 33, the test cathode voltage Vsst is manipulated so that the current flowing through the cathode wiring 232 becomes a predetermined value. However, even if Vsst is changed within a predetermined range, the current flowing through the cathode wiring 232 may not reach a predetermined value.

  In this case, the pixel 16 is almost always defective. Therefore, when the change in Vsst or the adjustment range is out of the range, it is possible to detect that a defect or the like of any pixel 16 in the selected pixel row has occurred. The degree of defects can also be grasped by the size of the voltage variable range.

  For example, the initial voltage Vsst = −3.0V and the variable range is ± 0.5V. If the current flowing through the cathode wiring 232 in the range of −3.5 V to −2.5 V cannot be set to m × I1, it is assumed that a defect has occurred. Further, the variable range is set to ± 0.8 V, and even in this range, it is assumed that a serious defect has occurred if the current flowing through the cathode wiring 232 cannot be set to m × I1.

  In FIG. 25, FIG. 27, and FIG. 33, the test transistor 145 can be subjected to a wider variety of inspections by performing on / off control in a pulsed manner or periodically turning on / off. In FIG. 25, when the test transistor 145 is turned on, a switch formed in the final output stage of the source driver IC 14 is opened (high impedance), the source driver IC 14 is disconnected from the source signal line, and the source signal line is separated by the test transistor 145. 18 is protected from the voltage (current) applied to it.

  25, 27, 33, etc., the Vdd and Vss voltages output from the power supply IC 222 or the external power supplies Vddt and Vsst are variable or adjusted, and the variable or adjusted state is synchronized with the on / off state of the test transistor 145. By doing so, a wider variety of inspection adjustments can be realized. For example, in the aging process, Vddt and Vsst are applied, and the test transistor 145 applies a voltage or current for turning on (displaying) and turning off (not displaying) the pixel 16 in one frame or a plurality of frame periods. Then, the EL display panel becomes a flash display with the aging configuration, and a great stress can be applied, so that the aging process can be shortened. By causing the EL display device to perform flash display, defects that will occur in the future in the EL component film of the EL element 15 can be generated in the aging configuration. The above method can be realized not only by controlling the test transistor 145 but also by controlling the source driver IC 14.

  In FIG. 26, FIG. 27, and FIG. 33, the voltage-driven pixel configuration has been described as an example. However, the present embodiment is not limited to this, and the present embodiment can also be applied to the current-driven pixel configuration shown in FIGS. The present invention can also be applied to other voltage-driven pixel configurations shown in FIG.

  The driving method of the present embodiment is not limited to the driving method and driving circuit of the organic EL display panel. Needless to say, the present invention can be applied to other displays such as a field emission display (FED) and an inorganic EL display.

  Next, a display device of this embodiment using an EL display device that implements the driving method of this embodiment as a display will be described.

  FIG. 28 is a plan view of a mobile phone as an example of an information terminal device. An antenna 281 and the like are attached to the housing 283. 282a is a switch key for changing the duty ratio, 282b is a power on / off key, and 282c is a key for switching the operation frame rate of the gate driver circuit 12b. Reference numeral 285 denotes a photo sensor. The photosensor 285 automatically adjusts the brightness of the display screen 22 by changing the duty ratio and the like according to the intensity of external light.

  FIG. 29 is a perspective view of the video camera. The video camera includes a photographing (imaging) lens unit 293 and a video camera body 283. The EL display device of this embodiment is also used as a display monitor 284. The display screen 22 can freely adjust the angle at a fulcrum 291. When the display screen 22 is not used, it is stored in the storage unit 294.

  In the display device of this embodiment such as FIG. 28 and FIG. 29, the duty ratio can be switched by operating the key 282a. The user can switch the operation of the key 282a. In addition, it is possible to switch whether it can be automatically changed in the setting mode. In the case of automatic, the brightness of external light is detected and the display luminance can be automatically set to 50%, 60%, 80%, and the like.

  The EL display device and the like of this embodiment can be applied not only to a video camera but also to an electronic camera as shown in FIG. The EL display device of this embodiment is used as the display screen 22 attached to the camera body 301. In addition to the shutter switch 303, a switch 282 a is attached to the camera body 301.

  As described above, the EL display device of this embodiment can apply a voltage or a constant current to the source signal line 18 through the test transistor. Therefore, the inspection of the pixels 16 and the like can be easily realized without using other means.

  In addition, since the EL display device of this embodiment has an output open function in the power supply IC, in the aging process, a voltage higher than the normal state can be applied to the EL display panel, and aging can be performed efficiently. By using this output open function, the current from the cathode wiring can be measured while the power supply IC is mounted on a substrate or the like. Therefore, white balance and luminance adjustment of the EL display device can be easily performed. Further, by sequentially selecting the pixels and measuring the current output from the selected pixels, it is possible to detect a pixel defect and to measure the characteristic variation of the driving transistor of the pixel.

  The EL display device according to this embodiment can apply a voltage or a constant current to the source signal line through the test transistor. Therefore, inspection of pixels and the like can be easily realized without using other means.

  In addition, since the power supply IC has an output open function, in the aging process, a voltage higher than the normal state can be applied to the EL display panel, and aging can be performed efficiently. By using this output open function, the current from the cathode wiring can be measured while the power supply IC is mounted on a substrate or the like. Therefore, white balance and luminance adjustment of the EL display device can be easily performed. Further, by sequentially selecting the pixels and measuring the current output from the selected pixels, it is possible to detect a pixel defect and to measure the characteristic variation of the driving transistor of the pixel.

  Accordingly, a self-luminous display panel (display device) such as an EL display panel (display device) using an organic or inorganic electroluminescence (EL) element, a driving method thereof, a driving device, and a display device using these display panels It is useful for such as.

Configuration diagram of pixel of EL display device Configuration diagram of EL display device (A), (b) Explanatory drawing of operation | movement of the pixel of EL display apparatus. (A), (b) Explanatory drawing of the drive method of EL display device (A)-(c) Explanatory drawing of the drive method of EL display apparatus (A), (b) Explanatory drawing of the drive method of EL display device (A), (b) Pixel configuration diagram of an EL display device (A), (b) Pixel configuration diagram of an EL display device Explanatory drawing of EL display device of embodiment of this invention Explanatory drawing of EL display device of embodiment of this invention Explanatory drawing of EL display device of embodiment of this invention Explanatory drawing of EL display device of embodiment of this invention Explanatory drawing of EL display device of embodiment of this invention Explanatory drawing of EL display device of embodiment of this invention Explanatory drawing of EL display device of embodiment of this invention Explanatory drawing of EL display device of embodiment of this invention Explanatory drawing of EL display device of embodiment of this invention Explanatory drawing of EL display device of embodiment of this invention Explanatory drawing of EL display device of embodiment of this invention Explanatory drawing of EL display device of embodiment of this invention Explanatory drawing of EL display device of embodiment of this invention Explanatory drawing of EL display device of embodiment of this invention Explanatory drawing of EL display device of embodiment of this invention Explanatory drawing of EL display device of embodiment of this invention Explanatory drawing of EL display device of embodiment of this invention Explanatory drawing of EL display device of embodiment of this invention Explanatory drawing of the drive method of EL display apparatus of embodiment of this invention Explanatory drawing of EL display device of embodiment of this invention Explanatory drawing of EL display device of embodiment of this invention Explanatory drawing of EL display device of embodiment of this invention (A), (b) Explanatory drawing of EL display device of embodiment of this invention Explanatory drawing of EL display device of embodiment of this invention Explanatory drawing of EL display device of embodiment of this invention Explanatory drawing of EL display device of embodiment of this invention Explanatory drawing of EL display device of embodiment of this invention Explanatory drawing of EL display device of embodiment of this invention Explanatory drawing of EL display device of embodiment of this invention Illustration of a conventional EL display device Explanatory drawing of EL display device of embodiment of this invention

Explanation of symbols

11 Transistor (TFT)
12 Gate driver IC (circuit)
14 Source Driver Circuit (IC)
15 EL (element)
16 pixels 17 gate signal line 18 source signal line 19 storage capacity (additional capacitor, additional capacity)
22 Display screen 41 Write pixel row 45 Non-display area (non-lighting area, black display area)
46 Display area (lighting area, image display area)
91 Operational amplifier (buffer circuit)
92 Electronic volume (voltage output circuit)
93 Reference current circuit 94 Transistor 95 Unit transistor group 96 Output terminal 101 Analog switch (ON / OFF means, selection means)
102 Unit transistor 103 Internal wiring 104 Gate wiring 105 Decoder circuit 111 Amplitude adjustment register 112 Gradation amplifier 113 Terminal (wiring)
114 Gamma circuit 121 Voltage data latch circuit 122 Gradation voltage output circuit 123 Voltage DAC circuit 124 Voltage amplifier circuit 141 Output terminal pad 143 Input terminal pad 144 Source driver IC mounting position 144
145 Test transistor 146 Signal input terminal 147 Transistor control terminal 161 Flexible substrate (flexible substrate)
162 Array substrate 163, 164 Connection terminal 165 Short-circuit electrode terminal 181 Operational amplifier 182 Transistor 183 Electronic volume 222 Power supply IC
231 Anode wiring 232 Cathode wiring 233 Ammeter 234 Probe 251 Connector 252 Flash memory 253 EEPROM
254 Test transistor group 281 Antenna 282 Key 283 Case 284 Display panel 285 Photo sensor 291 Support point 293 Shooting lens 294 Storage unit 301 Main body 302 Imaging unit 303 Shutter switch 321 Addition (subtraction) circuit 323 Temperature compensation circuit 333 Shift register (selection circuit)
361, 362 Short-circuit wiring 371 ACF

Claims (10)

A panel substrate having a display screen in which pixels having EL elements are arranged in a matrix;
A source driver circuit for outputting a video signal;
A gate driver circuit for sequentially selecting pixel rows of the display screen;
A power supply circuit that generates at least one of an anode voltage and a cathode voltage of the EL element;
The source driver circuit sets a current flowing through the display screen at the maximum gradation of the video signal, and a second setting circuit sets a current flowing through the display screen at the minimum gradation of the video signal. And a setting circuit,
The power supply circuit has a function of electrically setting at least one of an anode terminal that outputs the anode voltage and a cathode terminal that outputs the cathode voltage to have high impedance by command control or hardware terminal control,
At least one of the wiring between the anode terminal of the power circuit and the anode voltage input unit of the display screen, and the wiring between the cathode terminal of the power circuit and the cathode voltage input unit of the display screen,
Possess a site for inputting an external voltage, at least one portion of the portion connected with the external current detection means,
At the maximum gradation of the video signal, the current flowing through the display screen is measured by the external current detection means, and the first setting circuit is set.
An EL display device , wherein the second setting circuit is set by measuring the current flowing through the display screen at the lowest gradation of the video signal by the external current detection means . Further comprising a flexible substrate,
The source driver circuit is formed or mounted on the panel substrate;
The power supply circuit is formed or mounted on the flexible substrate,
The flexible substrate is connected to the panel substrate ;
2. The EL display device according to claim 1 , wherein the flexible substrate has at least one of a part for inputting the external voltage and a part connected to the external current detection unit . 2. The EL display device according to claim 1 , wherein the source driver circuit generates a voltage used in the gate driver circuit . The EL display device according to claim 1 , wherein at least one of the anode voltage and the cathode voltage can be varied .   A source signal line is connected to the output terminal of the source driver circuit,
  2. The EL display device according to claim 1, further comprising a switch circuit for applying a voltage to the source signal line.   The EL display device according to claim 1, wherein the power supply circuit generates an analog voltage used in the source driver circuit, and can independently control on / off of the analog voltage, the anode voltage, or the cathode voltage.   The EL display device according to claim 1, further comprising a temperature compensation circuit for detecting a temperature of the panel.   2. The EL display device according to claim 1, further comprising a photosensor for detecting the intensity of external light.   The EL display device according to claim 1, further comprising an arithmetic circuit for calculating a lighting rate.   In the pixel, a driving transistor for supplying current to the EL element is formed,
  2. The EL display device according to claim 1, wherein the driving transistor is a P-channel transistor.

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