JPH10214060A - Electric field light emission display device and its driving method - Google Patents

Electric field light emission display device and its driving method

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Publication number
JPH10214060A
JPH10214060A JP9027323A JP2732397A JPH10214060A JP H10214060 A JPH10214060 A JP H10214060A JP 9027323 A JP9027323 A JP 9027323A JP 2732397 A JP2732397 A JP 2732397A JP H10214060 A JPH10214060 A JP H10214060A
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Japan
Prior art keywords
voltage
light emitting
period
driving
display device
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
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JP9027323A
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Japanese (ja)
Inventor
Masaharu Shiotani
Hiroyasu Yamada
雅治 塩谷
裕康 山田
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Casio Comput Co Ltd
カシオ計算機株式会社
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Application filed by Casio Comput Co Ltd, カシオ計算機株式会社 filed Critical Casio Comput Co Ltd
Priority to JP9027323A priority Critical patent/JPH10214060A/en
Priority claimed from US09/013,708 external-priority patent/US5990629A/en
Publication of JPH10214060A publication Critical patent/JPH10214060A/en
Application status is Abandoned legal-status Critical

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Abstract

PROBLEM TO BE SOLVED: To provide the driving method for the electric field light emission display device which can make a gradational display with controllability and be driven with low power consumption.
SOLUTION: One frame period of the electric field light emission device which has electric field light emission elements arranged in matrix and selection transistors and driving transistors of the electric field light emission elements connected is divided into eight subframes 1 to 8. Those subframes are so set that they consist of different display discharge times Ton by the respective subframes 1 to 8 and an address period Tadd of the same time among all the subframes 1 to 8. Consequently, total light emission times by pixels can be made different according to whether pixels are selected in the eight subframes 1 to 8, thereby enabling gradational representation.
COPYRIGHT: (C)1998,JPO

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】この発明は電界発光表示装置およびその駆動方法に関し、さらに詳しくは、エレクトロルミネッセンス発光を行う表示装置の駆動方法に関する。 TECHNICAL FIELD The present invention relates to light emitting display and a driving method thereof, and more particularly, to a driving method of a display device which performs electroluminescence emission.

【0002】 [0002]

【従来の技術】従来、図10に示すような、1画素に2 Conventionally, as shown in FIG. 10, 2 to 1 pixel
つの薄膜トランジスタ(以下、TFTという)を備えた構造の有機ELディスプレイ(電界発光表示装置)がある。 One thin film transistor (hereinafter, referred to as TFT) and organic EL display structure with (light emitting display). この有機ELディスプレイにおいては、同図に示すように、有機EL素子1と直列に繋がる駆動TFT2のチャネル抵抗を、そのゲートバイアスを選択TFT3が書き込むことで階調表示させていた。 In this organic EL display, as shown in the figure, the driving TFT2 in channel resistance leading to the organic EL element 1 in series, were allowed to gradation display by writing the gate bias selection TFT 3. ここで、選択TF Here, select TF
T3が走査ラインXmで選択されると、書き込む信号が信号ラインYnから供給されるようになっている。 T3 is so when it is selected by the scanning line Xm, written signal is supplied from the signal line Yn. 図1 Figure 1
1は、このように書き込まれた駆動TFT2の、ゲート電圧(Vg)とチャネル抵抗との関係、所謂電界効果トランジスタ(FET)の静特性を示すグラフである。 1, the driving TFT2 in this way is written, the relationship between the channel resistance between the gate voltage (Vg), which is a graph showing the static characteristics of the so-called field effect transistor (FET). 図12は、1画素における有機EL素子1と電圧制御手段Vcと全画素共通EL電源4との関係を示す等価回路図である。 Figure 12 is an equivalent circuit diagram showing the relationship between the organic EL element 1 and the voltage control means Vc and common to all pixels EL power supply 4 in 1 pixel. この電圧制御手段Vcは、選択トランジスタ3 The voltage control means Vc is the selection transistor 3
と駆動トランジスタ2とから構成されている。 And a drive transistor 2.

【0003】 [0003]

【発明が解決しようとする課題】上記した従来の1画素2セルTFT構造の有機ELディスプレイでは、駆動T [SUMMARY OF THE INVENTION In the organic EL display of the above-mentioned conventional 1 pixel 2 cell TFT structure, driving T
FT2のゲートバイアスの変化によってチャネルに流れる電流を変えることにより、画素ELの発光輝度を変化させることで階調を表現している。 By varying the current flowing through the channel by a change in the gate bias of FT2, expresses the gradation by changing the light emission luminance of the pixel EL. このため、たとえば256階調を実現しようとすると、パネル内の各画素の駆動TFT2の線形領域での特性バラツキが256階調の制御に要求される範囲内になければならず、そのような均一な特性のTFTパネルの製造は実現が困難であるという問題がある。 Thus, for example, 256 when attempting to realize a gradation, should be within the range of characteristic variation of the driving TFT2 in the linear region of each pixel in the panel is required for the control of 256 gradations, such uniform the production of TFT panels properties there is a problem that it is difficult to realize.

【0004】この発明が解決しようとする課題は、制御性のよい階調表示が行えると共に、低消費電力動作が可能な電界発光表示装置の駆動方法を得るにはどのような手段を講じればよいかという点にある。 [0004] Problems to be the invention solved, good gray scale display with enabling controllability, Kojire what means to obtain a driving method with low power consumption capable of operating light emitting display lies in the fact that one.

【0005】 [0005]

【課題を解決するための手段】請求項1記載の発明は、 Means for Solving the Problems The invention according to claim 1,
電界発光表示装置であって、それぞれ一対の電極を有し、電圧の印加に応じて発光する複数の電界発光素子と、前記各電界発光素子の前記一対の電極の一方のそれぞれに接続され、各アドレス期間に、接地電圧或いは一定電圧値の駆動電圧のいずれか一方を、前記各アドレス期間に対応した各発光設定期間に発光すべき電界発光素子に、出力する複数の第1スイッチング回路と、前記各電界発光素子の前記一対の電極の他方のそれぞれに接続され、前記各発光設定期間に、前記接地電圧或いは前記駆動電圧の他方を、前記全電界発光素子に出力する第2 A light emitting display device, each have a pair of electrodes, and a plurality of light emitting elements that emit light in response to an applied voltage, which is connected to one of each of the pair of electrodes of each of electroluminescent devices, each in the address period, one of the driving voltage of the ground voltage or a constant voltage value, the electric field light emitting element to be emitted to the flash setting period corresponding to each address period, and a plurality of first switching circuit for outputting, the They are connected to each other of the pair of electrodes of each light emitting element, wherein each light-emitting setting period, a second that outputs the other of the ground voltage or the driving voltage, the entire light emitting element
スイッチング回路と、を具備することを特徴としている。 It is characterized by comprising a switching circuit.

【0006】請求項1記載の発明では、各発光設定期間に発光すべき電界発光素子を予め選択して、対応する各アドレス期間に接地電圧或いは一定電圧値の駆動電圧の一方を印加しているので、各発光設定期間に全電界発光素子の一対の電極の他方に接地電圧或いは駆動電圧の他方を印加すれば、選択された電界発光素子のみが各発光設定期間に発光することができる。 [0006] In the first aspect of the present invention, and preselected light emitting element to be emitted to the flash setting period, are applied one of the driving voltage of the ground voltage or a constant voltage value to a corresponding each address period because, by applying the other of the other to the ground voltage or the drive voltage of the pair of electrodes of all light emitting elements in each light emitting set period, can be only selected light emitting element emits light to the light emitting setting period. したがって、複数の発光設定期間中に選択的に電界発光素子を発光することにより、言い換えれば、選択された発光設定期間の総時間に応じて、各電界発光素子の見かけ上の発光輝度を制御することができる。 Therefore, by selectively emitting the light emitting element in a plurality of light-emitting setting period, in other words, depending on the total time of the selected light emission setting period, and controls the emission luminance of the apparent each electroluminescent element be able to.

【0007】請求項2記載の発明は、前記電界発光素子はマトリクス状に配列され、1フレーム期間は、前記複数のアドレス期間と、各アドレス期間にそれぞれ対応し且つ互いに異なる長さの時間である複数の発光設定期間と、からなることを特徴としている。 [0007] According to a second aspect of the invention, the light emitting element are arranged in a matrix, one frame period, the plurality of address periods, is in each of the corresponding and mutually different lengths times each address period It is characterized and a plurality of light-emitting setting period, in that it consists of. 請求項2記載の発明では、各発光設定期間の時間の長さが互いに異なるので、階調に応じた発光設定期間を選択すれば一定電圧値の駆動電圧にもかかわらず、それぞれの画素が1フレーム期間に少ない選択数で多くの輝度階調数の発光を実現することができる。 In the second aspect of the present invention, since the length of time of each light-emitting setting period are different from each other, despite the drive voltage of a constant voltage value by selecting the light emission setting period corresponding to the gradation, each pixel 1 it is possible to realize a light emission of a number of luminance gradation number in a small selected number in the frame period.

【0008】請求項3記載の発明は、前記第1スイッチング回路は、走査電圧が供給される走査ラインにゲート電極が接続され且つ信号電圧が供給される信号ラインにドレイン電極が接続された選択トランジスタと、ゲート電極が前記選択トランジスタのソース電極に接続され、 [0008] third aspect of the present invention, the first switching circuit, the select transistor having a drain electrode to the signal line and the signal voltage is connected to the gate electrode is supplied to the scan line scanning voltage is supplied is connected When, a gate electrode connected to the source electrode of the selection transistor,
且つドレイン電極が前記電界発光素子に接続されると共に、ソース電極が接地或いは前記駆動電圧のいずれか一方を出力する駆動電源に接続された駆動トランジスタと、を備えることを特徴としている。 And with a drain electrode connected to the electroluminescent device is characterized in that it comprises, a driving transistor connected to a driving power source for outputting either one of the source electrode is grounded or the drive voltage. 請求項3記載の発明では、アドレス期間に選択された電界発光素子に、発光設定期間中に容易に接地電圧或いは一定電圧値の駆動電圧の一方を印加できるようチャージできる。 In the invention of claim 3, wherein, in the electroluminescent elements selected in the address period, can charge so that one can apply a driving voltage of the light-emitting setting period easily ground voltage or a constant voltage value during.

【0009】請求項4記載の発明は、前記走査電圧および前記信号電圧は、それぞれの特性に応じたオン/オフの2値信号であることを特徴としている。 [0009] The invention of claim 4, wherein, the scanning voltage and the signal voltage is characterized in that a binary signal on / off in accordance with respective characteristics. また、請求項5記載の発明は、前記第2スイッチング回路には、オン/オフの2値信号が入力されることを特徴としている。 The invention of claim 5 wherein the wherein the second switching circuit is characterized in that a binary signal of ON / OFF is input.

【0010】請求項4および請求項5記載の発明では、 [0010] In the invention of claim 4 and claim 5, wherein the
走査電圧、信号電圧および第2スイッチング回路がオン/オフの2値信号で制御できるので、選択トランジスタ、駆動トランジスタ、第2スイッチング回路のV−I Scanning voltage, the signal voltage and the second switching circuit can be controlled by the binary signal on / off, selection transistors, the driving transistor, V-I of the second switching circuit
特性に多少のばらつきがあっても、飽和電流領域の電圧を印加すれば、良好に輝度階調を制御することができる。 Even if there is some variation in the characteristics, by applying a voltage of the saturation current region, it can be better to control the brightness gradation.

【0011】請求項6記載の発明は、前記各発光設定期間の時間の長さの比率は、それぞれ2のn乗(nは0以上の整数)のいずれかであることを特徴としている。 [0011] according to claim 6 invention, the length of time of the ratio of the respective light-emitting setting period is characterized in that (is n 0 or an integer) 2 n each is either.

【0012】請求項7記載の発明は、電圧の印加に応じて発光する複数の電界発光素子を有する電界発光表示装置の駆動方法において、1フレーム期間が、それぞれ任意の前記電界発光素子を選択する、複数のアドレス期間を備え、且つそれぞれの前記アドレス期間の後に、当該アドレス期間で選択された前記電界発光素子に駆動電圧を供給する、互いに異なる長さの時間に設定された駆動電圧供給期間を備えることを特徴としている。 [0012] According to a seventh aspect, in the driving method of the light emitting display device having a plurality of light emitting elements that emit light in response to an applied voltage, one frame period, select any of the light emitting element, respectively , comprising a plurality of address periods, and after each of the address period, the selected in the address period to supply an electric field driving voltage to the light emitting element, the set driving voltage supply period different lengths of time to each other It is characterized in that it comprises.

【0013】請求項7記載の発明では、各アドレス期間に、次の駆動電圧供給期間に発光すべき電界発光素子を予め選択して、駆動電圧供給期間に発光させるが、各駆動電圧供給期間の時間の長さが互いに異なるので、それぞれの画素が、階調に応じた駆動電圧供給期間を選択すれば一定電圧値の駆動電圧にもかかわらず、1フレーム期間に少ない選択で多くの輝度階調数の発光を実現することができる。 [0013] According to a seventh aspect, in the address period, and preselected light emitting element to be emitted to the next drive voltage supply period, but emit light in the driving voltage supply period, of the driving voltage supply period because the length of time are different from each other, each pixel, despite the drive voltage of a constant voltage value by selecting the driving voltage supply period corresponding to a gradation, many luminance gradation with less selective to one frame period it is possible to realize the light emission of several.

【0014】 [0014]

【発明の実施の形態】以下、この発明に係る電界発光表示装置の駆動方法の詳細を図面に示す実施形態に基づいて説明する。 BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, will be explained based on the embodiment shown the details of the driving method of the light emitting display device according to the invention with reference to the drawings. なお、駆動方法の説明に先駆けて、電界発光表示装置の構成について説明する。 Incidentally, prior to the description of the driving method, the configuration of the light emitting display. 図1は本実施形態に係る電界発光表示装置の駆動回路図である。 Figure 1 is a drive circuit diagram of a light emitting display device according to the present embodiment. 同図に示すように、電界発光素子としての有機EL素子101 As shown in the figure, the organic EL element 101 as the light emitting element
が、X−Yマトリクス状に配置されたそれぞれの画素領域に形成されている。 There are formed in the respective pixel areas arranged an X-Y matrix. これらの画素領域は、複数の走査ラインXと複数の信号ラインYとがそれぞれ交差する部分に形成されている。 These pixel regions, a plurality of scanning lines X and a plurality of signal lines Y is formed at the intersection, respectively. 1つの画素領域には、走査ラインXおよび信号ラインYに接続された選択トランジスタQ A single pixel region, is connected to the scan line X and signal line Y selection transistors Q
1と、この選択トランジスタQ 1にゲートが接続された駆動トランジスタQ 2とが設けられている。 1, a driving transistor Q 2 to which the gate is connected is provided on the select transistor Q 1. この駆動トランジスタQ 2は、有機EL素子101の一方の電極に接続されている。 The driving transistor Q 2 is connected to one electrode of the organic EL element 101. そして、選択トランジスタQ 1が選択され、且つ信号ラインYより駆動信号が出力されると駆動トランジスタQ 2がオン状態になるように設定されている。 The selection transistor Q 1 is selected, and the driving transistor Q 2 and the drive signal is outputted from the signal line Y is set to be turned on. この駆動信号は、ON/OFFの2値信号である。 The drive signal is a binary signal of ON / OFF.
なお、駆動トランジスタQ 2は、オフ状態では有機EL The driving transistor Q 2 is an organic EL is turned off
素子101に比べて充分高抵抗で、オン状態では有機E A sufficiently high resistance than the device 101, the on-state organic E
L素子101に比べて無視できるほど充分低抵抗となるようにその特性が設定されている。 Its characteristics as well a low resistance negligible compared to the L element 101 are set.

【0015】図2は、この電界発光表示装置の1画素部分の等価回路図である。 [0015] Figure 2 is an equivalent circuit diagram of one pixel portion of the EL display device. 同図に示すスイッチS 1は有機EL素子101の一方の電極に接続されており、このスイッチS 1の閉じている状態で、有機EL素子101の発光が可能となる。 Switch S 1 shown in the figure is connected to one electrode of the organic EL element 101, in the closed state of the switch S 1, it is possible to light emission of the organic EL element 101. また、スイッチS 2は、有機EL素子101の他方の電極側に接続されており、全画素に共通に用いられるとともに、後記するサブフレーム期間内の発光時間に従って全画素を同時にオン/オフし得るようになっている。 The switch S 2 is connected to the other electrode side of the organic EL element 101, along with commonly used in all the pixels may be simultaneously turned on / off all the pixels in accordance with light emitting times in the subframe period to be described later It has become way. なお、図2中Psは一定電圧に固定された駆動電源を示している。 In FIG. 2 Ps shows a driving power source which is fixed to a constant voltage.

【0016】ここで、本実施形態における電界発光表示装置の更に具体的な構成を、図3および図4を用いて説明する。 [0016] Here, further specific structure of a light emitting display device in this embodiment will be described with reference to FIGS. 図3は、本実施形態における電界発光表示装置の1画素部分を示す平面図である。 Figure 3 is a plan view showing one pixel portion of the EL display device in this embodiment. 図4は、図3のA− Figure 4 is, as shown in FIG. 3 A-
A断面図である。 A is a cross-sectional view. 図中100は電界発光表示装置を示している。 Figure 100 shows a light emitting display.

【0017】本実施形態の電界発光表示装置100は、 The light emitting display device 100 of this embodiment,
ガラス或いは樹脂フィルムからなる基板102の上に例えばアルミニウム(Al)でなるゲートメタル膜がパターニングされてなる、所定方向(X方向)に沿って平行かつ等間隔をなす複数の走査ライン103と、この走査ライン103に一体的な、選択トランジスタQ 1のゲート電極103Aと、駆動トランジスタQ 2のゲート電極103Bと、が形成されている。 Gate metal film made, for example, aluminum (Al) on a substrate 102 made of glass or resin film is formed by patterning a plurality of scanning lines 103 that extends parallel and at equal intervals along a predetermined direction (X direction), the the scan line 103 that integrally includes a gate electrode 103A of the selection transistors Q 1, and the gate electrode 103B of the driving transistor Q 2, is formed. なお、これらゲート電極103A、103Bおよび走査ライン103の表面には、陽極酸化膜104が形成されている。 Note that the gate electrodes 103A, 103B and the surface of the scanning lines 103, the anodic oxide film 104 is formed. また、これら走査ライン103、ゲート電極103A、103Bおよび基板102の上には、窒化シリコンでなるゲート絶縁膜105が形成されている。 Further, the scanning lines 103, the gate electrode 103A, on the 103B and the substrate 102, the gate insulating film 105 made of silicon nitride is formed. さらに、ゲート電極103 Furthermore, the gate electrode 103
A、103Bの上方のゲート絶縁膜105A、105B A, 103B of the upper gate insulating film 105A, 105B
の上には、アモルファスシリコン(a−Si)でなる半導体層106A、106Bがパターン形成されている。 On top of the semiconductor layer 106A made of amorphous silicon (a-Si), 106B are patterned.
また、それぞれの半導体層106A、106Bの中央には、チャネル幅方向に沿って形成されたブロッキング層107A、107Bが形成されている。 Further, each of the semiconductor layers 106A, the center of 106B, blocking layer 107A formed along the channel width direction, 107B are formed. そして、半導体層106Aの上には、ブロッキング層107A上でソース側とドレイン側とに分離されたオーミック層108 Then, on the semiconductor layer 106A is separated into the source and drain sides on the blocking layer 107A ohmic layer 108
A、108Aが形成されている。 A, 108A are formed. さらに、選択トランジスタQ 1においては、ドレイン側のオーミック層108 Further, in the select transistor Q 1, the drain side of the ohmic layer 108
Aに積層されて接続する信号ライン109Aと、ソース側のオーミック層108Aに積層されて接続するソース電極109Bとが形成されている。 A signal line 109A for connecting are stacked in A, and a source electrode 109B which connects are stacked in ohmic layer 108A on the source side are formed. このソース電極10 The source electrode 10
9Bは、図3に示すように、駆動トランジスタQ 2のゲート電極103Bに対して、ゲート絶縁膜105に開口したコンタクトホール110を介して接続されている。 9B, as shown in FIG. 3, the gate electrode 103B of the driving transistor Q 2, are connected via a contact hole 110 which is opened in the gate insulating film 105.
駆動トランジスタQ 2においては、ソース側のオーミック層108Bに積層されて接続するGND線111と、 In the driving transistor Q 2, the GND line 111 for connecting is laminated on the ohmic layer 108B on the source side,
一端がドレイン側のオーミック層108Bに積層されて接続し、且つ他端が有機EL素子101の後記するカソード電極114に接続するドレイン電極112が形成されている。 One end is connected is laminated on the ohmic layer 108B on the drain side, and the other end is formed a drain electrode 112 connected to the cathode electrode 114 to be described later of the organic EL element 101. これら選択トランジスタQ 1と駆動トランジスタQ 2は、図2に示したスイッチS 1を構成している。 These select transistors Q 1 and driver transistor Q 2 is, constitutes a switch S 1 shown in FIG.
また、ゲート電極103Bとゲート絶縁膜105とGN The gate electrode 103B and the gate insulating film 105 and GN
D線とでキャパシタCp1が構成される。 Capacitor Cp1 is constituted by the D line.

【0018】次に、有機EL素子101の構成を説明する。 [0018] Next, the configuration of the organic EL element 101. まず、上記した選択トランジスタQ 1 、駆動トランジスタQ 2およびゲート絶縁膜105の上に、電界発光表示装置100の発光表示領域全域に亙って、層間絶縁膜113が堆積されている。 First, select transistors Q 1 described above, on the drive transistor Q 2 and the gate insulating film 105, over a luminous entire display area of the light emitting display 100, an interlayer insulating film 113 is deposited. そして、上記した駆動トランジスタQ 2のドレイン電極112の端部上の層間絶縁膜113にコンタクトホール113Aが形成されている。 Then, a contact hole 113A is formed in the interlayer insulating film 113 on the end of the drain electrode 112 of the driving transistor Q 2 to which the above-mentioned. なお、本実施形態では、駆動トランジスタQ 2のドレイン電極112の端部は、1画素領域の略中央に位置するように設定されている。 In the present embodiment, the end portion of the drain electrode 112 of the driving transistor Q 2 is set to be positioned at substantially the center of one pixel region. そして、層間絶縁膜113 Then, the interlayer insulating film 113
の上に、例えばMgInでなるカソード電極114が略1画素領域全域に亙って矩形状に形成されている。 Over, it is formed in a rectangular shape cathode electrode 114 made of, for example, MgIn over approximately 1 pixel entire region. すなわち、カソード電極114は、相隣接する信号ライン1 That is, the cathode electrode 114, a signal line 1 adjacent phase
09A、109Aと相隣接する走査ライン103、10 09A, 109A and mutually adjacent scanning lines 103,10
3とで囲まれる領域(1画素領域)を略覆うように形成されている。 3 is formed so as to substantially cover the area (1 pixel region) surrounded by the. このため、選択トランジスタQ 1と駆動トランジスタQ 2とは、カソード電極114で全面的に覆われている。 Therefore, the selection transistors Q 1 and driver transistor Q 2, the cathode electrode 114 are entirely covered.

【0019】さらに、図4に示すように、各画素毎にパターン形成されたカソード電極114、および層間絶縁膜113の上に、有機EL層115が発光表示領域全域に亙って形成されている。 Furthermore, as shown in FIG. 4, the cathode electrode 114 patterned for each pixel, and on the interlayer insulating film 113, the organic EL layer 115 is formed over the light emitting entire display area . さらに、有機EL層115の上には、透明なITOでなるアノード電極116が全有機EL素子101の発光表示領域全域に亙って形成されている。 Furthermore, on the organic EL layer 115, an anode electrode 116 made of a transparent ITO is formed over the light emitting entire display area of ​​the whole organic EL element 101. また、各有機EL素子101のアノード電極1 Further, the anode electrode 1 of the organic EL elements 101
16は、スイッチS2を介して駆動電圧Vddを供給する駆動電源Psに接続されている。 16 is connected to a driving power source Ps supplying driving voltage Vdd through the switch S2.

【0020】ここで、上記した構成の電界発光表示装置100の作用について説明する。 [0020] Here is a description of the operation of the light emitting display device 100 having the above-described structure. 本実施形態においては、カソード電極114が、相隣接する信号ライン10 In the present embodiment, the signal line 10 cathode electrode 114, the adjacent phase
9A、109Aと相隣接する走査ライン103、103 9A, 109A and a phase adjacent scan lines 103 and 103
とで囲まれる領域(1画素領域)を略覆うように形成されているため、有機EL素子101は1画素領域の略全域に亙って発光を行うことができる。 Because it is formed so as to substantially cover the area (1 pixel region) surrounded by the organic EL element 101 can perform light emission over the substantially entire region of one pixel region. また、カソード電極114が光反射性を有するMgInで形成されているため、カソード電極114とアノード電極116との間に駆動電圧が印加された場合に、有機EL層115で発生した表示光は、下方(ガラス基板102側)に漏れることなくアノード電極116側に出射される。 Further, since the cathode electrode 114 is formed by MgIn having light reflectivity, when the driving voltage between the cathode electrode 114 and anode electrode 116 is applied, the display light generated by the organic EL layer 115, It is emitted to the anode electrode 116 side without leaking downward (glass substrate 102 side). このため、選択トランジスタQ 1および駆動トランジスタQ 2の半導体層106A、106Bへ不要に光が入射するのを防止することができ、各トランジスタの光起電力による誤動作が生じるのを回避することができる。 Therefore, it is possible to avoid the semiconductor layer 106A of the selection transistors Q 1 and driver transistor Q 2, can unnecessarily light to 106B is prevented from entering, from malfunction due to the photovoltaic of each transistor is generated . また、表示光は、透明なアノード電極116側から出射されるため、ガラス基板102などにより光吸収されることがなく、輝度の高い状態で出射される。 The display light is to be emitted from the transparent anode electrode 116 side, without being light absorbed by a glass substrate 102 and is emitted at a high luminance state.

【0021】次に、本実施形態の電界発光表示装置10 Next, an electroluminescent display device of the embodiment 10
0の駆動回路系を説明する。 0 of the drive circuit system will be described. 図2の等価回路図が示すように、有機EL素子101とスイッチS 1 、S 2と駆動電源Psとから1画素部分のEL表示回路が構成されている。 As shown in an equivalent circuit diagram of FIG. 2, EL display circuit of a pixel portion of an organic EL element 101 and the switch S 1, S 2 and the drive power Ps is configured. また、上記したように、スイッチS 1は、選択トランジスタQ 1と駆動トランジスタQ 2とから構成され、有機EL素子101に選択的に接地電位を供給(出力)することができる。 Further, as described above, the switch S 1 is composed of the select transistor Q 1 and driver transistor Q 2 Prefecture, selectively ground potential to the organic EL element 101 can be supplied (output). 有機EL素子101においては、アノード電極側に正極性の一定電圧値の駆動電圧Vddを供給する駆動電源Psが接続され、そのカソード電極側にスイッチS 1が接続され、スイッチS 1を構成する駆動トランジスタQ 2のソース電極側はGND線111を介して接地されている。 In the organic EL element 101, the driving power Ps for supplying a driving voltage Vdd constant voltage value of the positive polarity is connected to the anode electrode side, the switch S 1 is connected to the cathode electrode side, constituting the switch S 1 driving the source electrode of the transistor Q 2 is grounded through a GND line 111.

【0022】以下、本実施形態の電界発光表示装置10 [0022] Hereinafter, light emitting display device of the present embodiment 10
0の駆動方法について説明する。 A description will be given 0 of the driving method. まず、本実施形態は、 First, the present embodiment,
電界発光表示装置100における走査ライン103の本数を例えば480本、信号ライン109Aの本数を例えば640本に設定する。 Light emitting display number, for example, 480 scanning lines 103 in 100, sets the number of signal lines 109A, for example, 640. そして、本実施形態では、図5 Then, in this embodiment, FIG. 5
に示すような階調表示方式を用いる。 The gradation display method as shown in use. 同図に示すように、1フレーム期間(1枚の表示を描く期間)が16. As shown in the figure, one frame period (the period to draw a single display) 16.
6ms固定であるとして、1フレーム期間を8つのサブフレーム期間(サブフレーム1〜8)に分割する。 As a 6ms fixed, divided into eight sub-frame periods of one frame period (subframe 1 to 8). 各サブフレーム期間は、アドレス書込みを行うためのアドレス期間Taddとアドレス期間に対応した駆動電圧供給期間Ton1〜8とからなる。 Each sub-frame period, a driving voltage supply period Ton1~8 Metropolitan corresponding to the address period Tadd an address period for performing an address write. この駆動電圧供給期間T The drive voltage supply period T
onの比率は、Ton1を1(=2 0 )とすると、To The ratio of on, when the Ton1 and 1 (= 2 0), To
n2は2(=2 1 )、Ton3は4(=2 2 )、Ton4 n2 is 2 (= 2 1), Ton3 is 4 (= 2 2), Ton4
は8(=2 3 )、Ton5は16(=2 4 )、Ton6は32(=2 5 )、Ton7は64(=2 6 )、Ton8は128(=2 7 )となる。 Is 8 (= 2 3), Ton5 is 16 (= 2 4), Ton6 is 32 (= 2 5), Ton7 is 64 (= 2 6), Ton8 becomes 128 (= 2 7). このような駆動電圧供給期間において、1の駆動電圧供給期間で1という輝度を表示するとすると、サブフレーム1のみを点灯することで1 In such a driving voltage supply period, when displaying a brightness of 1 by the first driving voltage supply period, 1 by lighting only subframe 1
の輝度が得られる。 Of brightness is obtained. 輝度2のときはサブフレーム2のみを、輝度3のときはサブフレーム1とサブフレーム2 Only sub-frame 2 at a luminance of 2, subframe 1 at a luminance 3 and the subframe 2
を、4のときはサブフレーム3のみを点灯するというように、以下同様にして組み合わせにより合計256(= The, so that lights only subframe 3 when the 4 total, by combining in the same manner 256 (=
8 )の階調を表示することが可能となる。 It is possible to display the gray scale of 2 8).

【0023】各サブフレームにおいては、アドレス期間Taddにアドレス書込みが終了した後に駆動電圧供給期間Tonの間アドレス選択された画素を同時に点灯させる。 [0023] In each subframe, at the same time it turns on between address selected pixel driving voltage supply period Ton after the address writing process has completed the address period Tadd. その次のサブフレームではアドレス期間Tadd Address period Tadd in the next sub-frame
中にアドレス書き換えを行って駆動電圧供給期間Ton To perform address rewriting in driving voltage supply period Ton
にアドレス選択された画素を同時に点灯させる。 At the same time it turns on the address selected pixel. このようにサブフレーム1からサブフレーム8まで1フレーム期間内に行う。 Thus performed from the sub-frame 1 in one frame period until the sub-frame 8. アドレス選択のタイミングは、図2に示したスイッチS 1で制御し、駆動電圧供給時間はスイッチS 2のオン時間で制御することができる。 Timing of address selection, controlled by switch S 1 shown in FIG. 2, the drive voltage supply time can be controlled by the on-time of the switch S 2. すなわち、 That is,
1つのサブフレーム期間内において、走査ラインと信号ラインとの線順次走査により、このサブフレーム特有の表示放電期間に点灯すべき画素の選択トランジスタQ 1 Within one sub-frame period, the line-sequential scanning of the scanning lines and the signal lines, the select transistor to Q 1 pixel to be turned on the sub-frame unique display discharge period
がオン状態となる。 There is turned on. そして、選択トランジスタQ 1がオンになると信号ラインから選択トランジスタQ 1を介して駆動トランジスタQ2のゲート電極への書込みが行われ、アドレス期間Tadd内においては駆動トランジスタQ 2にチャネルが形成された状態が保持される。 The state selection transistor Q 1 is from the consisting the signal lines on via the selection transistor Q 1 is performed writing to the gate electrode of the driving transistor Q2, the channel drive transistor Q 2 is in the address period Tadd is formed There is retained. このアドレス期間で点灯すべき画素がすべて選択された後、 After the pixel to be turned on in this address period is selected, all,
すなわちアドレス期間Tadd終了後の駆動電圧供給期間Tonまで選択状態が保持される。 That selection state is maintained until the drive voltage supply period Ton after the address period Tadd ends. 駆動電圧供給期間Ton中には、アノード電極116に接続された駆動電源PsがスイッチS 2でオンされる。 During the drive voltage supply period Ton, connected driving power Ps is turned on by the switch S 2 to the anode electrode 116. この駆動電圧供給期間は、上記したようにそれぞれのサブフレームでその長さが設定されている。 The driving voltage supply period, the length in each sub-frame as described above is set. ここで、1フレーム期間中の全アドレス期間Taddの時間の長さと駆動電圧供給期間Ton1〜Ton8の時間の長さを等しくすると、各アドレス期間Taddは、1.04ms程度となり、各走査ラインX 1 〜X 480の1駆動電圧供給期間で選択される時間は、2.2μs程度となる。 Here, to equalize the total address period length of time Tadd driving voltage time length of the supply period Ton1~Ton8 in one frame period, the address period Tadd becomes about 1.04 ms, the scanning lines X 1 time selected by the first driving voltage supply period to X 480 becomes about 2.2 microseconds.

【0024】次に、本実施形態の駆動方法で階調表示が行える原理を図6を用いて説明する。 Next, a principle that allows the gradation display in the driving method of this embodiment will be described with reference to FIG. この図は、簡略化するために、1フレーム期間を3つのサブフレームに分割した例であり、サブフレーム1の駆動電圧供給期間(発光時間)は1(=2 0 )、サブフレーム2の駆動電圧供給期間は2(=2 1 )、サブフレーム3の駆動電圧供給期間は4(=2 2 )とした。 This figure, for simplicity, an example in which one frame period is divided into three sub-frames, the driving voltage supply period of the sub-frame 1 (light emission time) is 1 (= 2 0), the driving of the sub-frame 2 voltage supply period is 2 (= 2 1), the drive voltage supply period of the sub-frame 3 is set to 4 (= 2 2). 図6は、網状の斜線を付した部分の画素13、22、24、31、35、4 6, pixels of the portion hatched reticular 13,22,24,31,35,4
2、44、53の輝度が高くなるように表示された例を示している。 Brightness of 2,44,53 indicates the displayed example to be higher. 具体的には、サブフレーム1で全画素が選択されて輝度1の発光を行ったとすると、サブフレーム2、3では線順次走査により画素13、22、24、3 Specifically, if it all the pixels are selected by the sub-frame 1 and subjected to light emission luminance 1, pixel by sub frames 2 and 3 in the line sequential scanning 13,22,24,3
1、35、42、44、53のみが選択され、輝度2と輝度4が加算されたと設定する。 Only 1,35,42,44,53 is selected, sets the luminance 2 and luminance 4 were added. このため、3つのサブフレームが終了した(1フレーム期間が終了した)状態では、画素13、22、24、31、35、42、4 Therefore, in the three sub-frames is finished (one frame period is completed) state, the pixel 13,22,24,31,35,42,4
4、53が輝度7となり、他の画素が輝度1であるのと比較して高輝度となる。 4,53 is compared to the next brightness 7, other pixels are luminance 1 a high luminance. このように、1フレーム期間を複数のサブフレームに分割することにより、アドレス期間合計と駆動電圧供給期間合計との比を変えることができるため、電界発光表示装置100の階調表示が可能となる。 Thus, by dividing one frame period into a plurality of sub-frames, it is possible to change the ratio of the address period sum and the drive voltage supply period total, it is possible to gradation display of an electroluminescent display device 100 . また、図7に示す有機EL素子の電圧−輝度−効率特性で最も効率の良い電圧値を発光駆動に用いるように設定すれば、低消費電力で発光駆動させることができる。 The voltage of the organic EL element shown in FIG. 7 - can be set to use the light emission drive the most efficient voltage value at efficiency characteristics, emit light driven with low power consumption - brightness. このような原理は、1フレーム期間を8つのサブフレームに分割した場合での同様に適用できるものであり、256階調の表現も可能となる。 This principle is for similarly applicable in the case where one frame period is divided into eight sub-frames, it becomes possible to express 256 gradations.

【0025】上記したように、本実施形態によれば、一定の駆動電圧Vddのスイッチングをオン/オフの2値信号で制御するスイッチS 2を用い、且つ選択トランジスタQ 1と駆動トランジスタQ 2にもオン/オフの2値信号をいずれかを選択的に出力するため、図10のソース・ドレイン間電圧VSDをソース・ドレイン間電流が飽和電流になる範囲に設定するので、各トランジスタの電圧VSDの1V〜5V間でのV−I特性に多少のばらつきがあっても、良好に輝度階調を制御することができ、安定した階調制御を行うことが可能となる。 [0025] As described above, according to this embodiment, using a switch S 2 to control a binary signal on / off switching of the constant drive voltage Vdd, and a selection transistor Q 1 to the driving transistor Q 2 for outputting be either a binary signal of oN / oFF selectively, since the source-drain voltage VSD in Fig. 10 is a source-drain current is set to range of the saturation current, the voltage of each transistor VSD even slight variations in the V-I characteristics between 1V~5V of, favorably can control the luminance gradation, it is possible to perform stable gradation control. 特に、1つの有機EL素子に対し選択トランジスタQ 1 、駆動トランジスタQ 2 、スイッチS 2の3つのスイッチング素子が構成している場合、それぞれのわずかな電気的特性のずれが相乗され、1つの画素として大きく輝度階調がずれてします恐れがあるが、選択トランジスタQ 1や駆動トランジスタQ 2およびスイッチS 2は、飽和電流領域での電圧値を用いオン/オフ制御を行うだけであるため、特性に多少のバラツキがあった場合でもその影響を受けにくいという利点がある。 In particular, the selection transistor Q 1 for one organic EL element, when the drive transistor Q 2, 3 two switching elements of the switch S 2 is constructed, displacement of each of the small electrical properties are synergistic, one pixel for larger there is a risk that will offset the luminance gradation as, select transistors Q 1 and driver transistor Q 2 and the switch S 2 is that only performs on / off control using a voltage value in the saturation current region, there is an advantage that is hardly affected by even if there is some variation in the characteristics. また、有機EL素子101にとって発光効率のよい電圧値を駆動電圧として設定できるため、低消費電力化を達成することができる。 Further, since it sets a good voltage value of luminous efficiency as a drive voltage taking the organic EL element 101, it is possible to achieve low power consumption.

【0026】以上、本実施形態について説明したが、本発明はこれに限定されるものではなく、構成の要旨に付随する各種の設計変更が可能である。 [0026] Having described the present embodiment, the present invention is not limited thereto, and can be various design changes associated with the gist of the structure. 例えば、上記した実施形態においては、サブフレーム期間におけるアドレス期間内でアドレス選択状態を保持するために、選択トランジスタQ 1と駆動トランジスタQ 2とを備えた構成としたが、図8の1画素等価回路で示すような構成としてもアドレス選択状態を保持することができる。 For example, in the above embodiment, in order to hold the address selected in the address period in the sub-frame period, a configuration having a selection transistor Q 1, the driving transistor Q 2, 1 pixel equivalent of FIG. 8 It may also be holding the address selected as the configuration shown in the circuit. 同図においてQ 3は選択トランジスタ、Q 4は駆動トランジスタ、 Q 3 are selected transistor in the figure, Q 4 is a driving transistor,
Cp2は容量を示している。 Cp2 shows the capacity. なお、この駆動トランジスタQ 4は別途容量Cp2が接続されているため、EEP Since the driving transistor Q 4 separately capacitance Cp2 is connected, EEP
ROM機能を有しないTFTを用いることができる。 It is possible to use a TFT does not have a ROM function. 駆動トランジスタQ 4のソース・ドレインの一方が各有機EL素子101の各カソード電極に接続され、他方がスイッチS 2を介して負電位Vdd′を供給する直流電源Ps′に接続されている。 One of the source and drain of the driving transistor Q 4 is connected to the cathode electrodes of the organic EL element 101, the other is connected to the 'DC power supply Ps supplies' negative potential Vdd via a switch S 2. 有機EL素子101は、発光表示領域全域に亙って形成されたアノード電極が接地され構造であり、駆動トランジスタQ 4が選択され、スイッチS 2がオンすると発光する。 The organic EL element 101 is an anode electrode formed over the light emitting entire display area is grounded structure, the driving transistor Q 4 is selected to emit light when the switch S 2 is turned on. また、上記した実施形態においては、電界発光素子として直流電界で発光できる有機EL素子101に特に有効であるが、無機EL素子やその他の電界発光素子を適用することも勿論可能である。 Further, in the above embodiment is particularly effective in the organic EL element 101 can emit light by a DC electric field as electroluminescent devices, it is of course possible to apply the inorganic EL element or other light emitting element. 本実施形態では、有機EL素子の発光層は電荷輸送性の異なる2層以上の有機層から構成されてもよく、 In the present embodiment, the light emitting layer of the organic EL element may be composed of charge-transporting different two or more layers of the organic layer,
アノード電極116上に酸素および水の侵入を防止する封止層を設けてもよい。 A sealing layer for preventing oxygen and water penetration on the anode electrode 116 may be provided. また、基板102側からアノード電極116、有機EL層115、カソード電極114 The anode electrode 116 from the substrate 102 side, the organic EL layer 115, a cathode electrode 114
の順に積層した構造としてもよい。 It may be of laminated in order.

【0027】なお、本実施形態では、1フレーム期間中の全アドレス期間Taddの時間の長さと駆動電圧供給期間Ton1〜Ton8の時間の長さを等しくしたが、 [0027] In the present embodiment, although equally the entire address period length of time Tadd driving voltage time length of the supply period Ton1~Ton8 in one frame period,
選択トランジスタQ 1 、Q 3 、駆動トランジスタQ 2 、Q 4 Select transistors Q 1, Q 3, the driving transistor Q 2, Q 4
の特性に応じて、アドレス期間Tadd、駆動電圧供給期間Tonの一方を長くしたり、他方を短くしたりしてもよい。 Depending on the characteristics, the address period Tadd, while the longer or the driving voltage supply period Ton, may be shorter or the other. また、各駆動電圧供給期間Tonは短い順(T Further, the driving voltage supplying period Ton is shorter order (T
on1、Ton2、…、Ton8)に印加されるがこれに限らず、長い順(Ton8、Ton7、…、Ton on1, Ton2, ..., but is applied to the Ton8) is not limited to this, long order (Ton8, Ton7, ..., Ton
1)でのよく、或いはTon8、Ton1、Ton5、 1) well in, or Ton8, Ton1, Ton5,
Ton4、Ton7、Ton2、Ton6、Ton3の順のように時間の長さの順番通りでなくてもよい。 Ton4, Ton7, Ton2, Ton6, may not be the order as the length of time as in the order of Ton3. また、駆動電源Psが供給する駆動電圧Vddは、直流電圧での交流でのでもよい。 The drive power Ps supplies driving voltage Vdd may even in exchange a DC voltage. さらに、階調数は256階調に限らず、複数の階調であれば256階調より多くても少なくてもよい。 Furthermore, the number of gradations is not limited to 256 gradations, it may be more or less than 256 gradations if a plurality of gradations.

【0028】本実施形態では、選択トランジスタQ 1と駆動トランジスタQ 2とからなるスイッチS 1がGND線111に接続され、駆動電圧供給期間TにオンするスイッチS 2が駆動電源Psに接続されているが、図9に示すように、有機EL素子101のアノード電極側のスイッチS2を駆動電源Psを介さずに直接接地させ、有機EL素子101のカソード電極側のスイッチS 1の駆動トランジスタQ 2をGND線111の代わりに負極性の一定値の駆動電圧Vdd′を供給する駆動電源Ps′に接続させてもよい。 [0028] In this embodiment, the selection switch S 1 comprising transistors Q 1 and driver transistor Q 2 Metropolitan is connected to the GND line 111, switch S 2 which is turned to the drive voltage supply period T is connected to a driving power source Ps are, but as shown in FIG. 9, the organic EL anode electrode side of the switch S2 of the element 101 is grounded directly without passing through the driving power Ps, the driving transistor Q 2 switches S 1 of the cathode side of the organic EL element 101 it may be connected to the 'driving power Ps supplying a' driving voltage Vdd of negative constant value instead of GND line 111. この場合であっても、走査ラインX、信号ラインYに、それぞれ2値信号のいずれかを出力し、有機EL素子101のアノード電極に接続されたスイッチS 2を2値信号でオン、オフ制御することができる。 Even in this case, scan lines X, the signal line Y, and outputs one of the respective binary signal, turning on the switch S 2 which is connected to the anode electrode of the organic EL element 101 in a binary signal, OFF control can do. すなわち、アドレス期間Taddには、選択された有機EL素子101のカソード電極側に駆動電圧Vd That is, the address period Tadd, the driving voltage Vd to the cathode electrode side of the organic EL element 101 selected
d′が供給され、駆動電圧供給期間Tonに全スイッチS 2がオンされ、有機EL素子101のアノード電極が接地され発光する。 d 'is supplied to the drive voltage supply period Ton entire switch S 2 is turned on, the anode electrode of the organic EL element 101 is grounded to emit light.

【0029】さらに、本実施形態では、有機EL素子1 Furthermore, in this embodiment, the organic EL element 1
01をスイッチS 1の上方に形成したが、スイッチS 1と同一平面上に形成してもよい。 01 has been formed over the switch S 1, it may be formed on the switch S 1 and the same plane. なお、この場合は、基板102側からアノード電極116、有機EL層115、 In this case, the anode electrode 116 from the substrate 102 side, the organic EL layer 115,
カソード電極114の順に積層して形成すれば、仕事関数の低く酸化されやすい材料からなるカソード電極11 It is formed by laminating in this order of the cathode electrode 114, a cathode electrode 11 made of easily oxidizable material low in work function
4をアノード電極116、有機EL層115の形成工程により劣化させることがない。 4 an anode electrode 116, is not deteriorated by the step of forming the organic EL layer 115.

【0030】 [0030]

【発明の効果】以上の説明から明らかなように、この発明によれば、電界発光表示装置を制御性よく階調表示できる共に、低消費電力動作を可能にするという効果を奏する。 As apparent from the foregoing description, according to the present invention, both can be controlled with good gradation display electroluminescent display device, an effect of enabling low power operation.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明の実施形態に係る電界発光表示装置の駆動回路図。 Drive circuit diagram of a light emitting display device according to an embodiment of the present invention; FIG.

【図2】本実施形態における電界発光表示装置の1画素部分の等価回路図。 Equivalent circuit diagram of one pixel portion of the EL display device in FIG. 2 embodiment.

【図3】本実施形態における電界発光表示装置の平面図。 Figure 3 is a plan view of a light emitting display device in this embodiment.

【図4】図3のA−A断面図。 [4] A-A cross-sectional view of FIG.

【図5】本実施形態の駆動方法示す説明図。 Figure 5 is an explanatory diagram illustrating a drive method of this embodiment.

【図6】1フレーム期間を3サブフレームに分割した場合の階調表示原理を説明する説明図。 Figure 6 is an explanatory diagram for explaining a gradation display principle in the case where one frame period is divided into 3 subframes.

【図7】本実施形態における有機EL素子の電圧−輝度−効率特性を示すグラフ。 [7] the voltage of the organic EL element in the present embodiment - brightness - graph showing efficiency characteristics.

【図8】本発明を適用し得る電界発光表示装置の1画素部分を示す等価回路図。 Equivalent circuit diagram showing one pixel portion of FIG. 8 light emitting display device to which the present invention is applicable.

【図9】本発明の他の実施形態に電界発光表示装置の駆動回路図。 Drive circuit diagram of a light emitting display device in another embodiment of the present invention; FIG.

【図10】従来の電界発光表示装置の1画素部分を示す等価回路図。 Figure 10 is an equivalent circuit diagram showing a pixel portion of a conventional light emitting display.

【図11】従来の電界発光表示装置における駆動TFT [11] driven in a conventional light emitting display TFT
2の、ゲート電圧(Vg)とチャネル抵抗との関係を示すグラフ。 2, the graph between the gate voltage (Vg) showing the relationship between the channel resistance.

【図12】従来の電界発光表示装置の1画素における有機EL素子1と電圧制御手段Vcと全画素共通EL電源4との関係を示す等価回路図。 Figure 12 is an equivalent circuit diagram illustrating a relationship between the organic EL element 1 and the voltage control means Vc and common to all pixels EL power supply 4 in one pixel of a conventional light emitting display.

【符号の説明】 DESCRIPTION OF SYMBOLS

100 電界発光表示装置 101 有機EL素子 103 走査ライン 109A 信号ライン Q 1選択トランジスタ Q 2駆動トランジスタ S 2スイッチ 100 light emitting display device 101 organic EL device 103 scanning lines 109A signal lines Q 1 selected transistor Q 2 driving transistor S 2 switch

Claims (12)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 それぞれ一対の電極を有し、電圧の印加に応じて発光する複数の電界発光素子と、 前記各電界発光素子の前記一対の電極の一方のそれぞれに接続され、各アドレス期間に、接地電圧或いは一定電圧値の駆動電圧のいずれか一方を、前記各アドレス期間に対応した各発光設定期間に発光すべき電界発光素子に、出力する複数の第1スイッチング回路と、 前記各電界発光素子の前記一対の電極の他方のそれぞれに接続され、前記各発光設定期間に、前記接地電圧或いは前記駆動電圧の他方を、前記全電界発光素子に出力する第2スイッチング回路と、 を具備することを特徴とする電界発光表示装置。 1. A each have a pair of electrodes, and a plurality of light emitting elements that emit light in response to an applied voltage, which is connected to one of each of the pair of electrodes of each electroluminescent device, each address period , one of the driving voltage of the ground voltage or a constant voltage value, the electric field light emitting element to be emitted to the flash setting period corresponding to each address period, and a plurality of first switching circuit for outputting, each electroluminescent are connected to each other of the pair of electrodes of the device to the each light emission setting period, the other of the ground voltage or the driving voltage, it includes a second switching circuit for outputting to the entire light emitting element light emitting display device according to claim.
  2. 【請求項2】 前記電界発光素子はマトリクス状に配列され、1フレーム期間は、前記複数のアドレス期間と、 Wherein said light emitting element are arranged in a matrix, one frame period includes a plurality of address periods,
    各アドレス期間にそれぞれ対応し且つ互いに異なる長さの時間である複数の発光設定期間と、からなることを特徴とする請求項1記載の電界発光表示装置。 A plurality of light-emitting setting period to each address period are the respective corresponding and different lengths time, be comprised of light emitting display device according to claim 1, wherein.
  3. 【請求項3】 前記第1スイッチング回路は、走査電圧が供給される走査ラインにゲート電極が接続され且つ信号電圧が供給される信号ラインにドレイン電極が接続された選択トランジスタと、ゲート電極が前記選択トランジスタのソース電極に接続され、且つドレイン電極が前記電界発光素子に接続されると共に、ソース電極が接地或いは前記駆動電圧のいずれか一方を出力する駆動電源に接続された駆動トランジスタと、を備えることを特徴とする請求項1または請求項2に記載の電界発光表示装置。 Wherein said first switching circuit includes a scanning line selection drain electrode to the signal line and the signal voltage is connected to the gate electrode is supplied is connected to a transistor scan voltage is supplied, the gate electrode is connected to the source electrode of the selection transistor, and provided with a drain electrode connected to the light emitting element, a driving transistor connected to a driving power source for outputting either one of the source electrode is grounded or the driving voltage, the light emitting display device according to claim 1 or claim 2, characterized in that.
  4. 【請求項4】 前記走査電圧および前記信号電圧は、それぞれの特性に応じたオン/オフの2値信号であることを特徴とする請求項3記載の電界発光表示装置。 Wherein said scanning voltage and the signal voltage, light emitting display device according to claim 3, characterized in that the binary signal on / off in accordance with respective characteristics.
  5. 【請求項5】 前記第2スイッチング回路には、オン/ Wherein said the second switching circuit, ON /
    オフの2値信号が入力されることを特徴とする請求項1 Claim, characterized in that the binary signal OFF is input 1
    〜請求項4のいずれかに記載の電界発光表示装置。 Light emitting display device according to any one of 1 to claim 4.
  6. 【請求項6】 前記各発光設定期間の時間の長さの比率は、それぞれ2のn乗(nは0以上の整数)のいずれかであることを特徴とする請求項1〜請求項5のいずれかに記載の電界発光表示装置。 The length of time the ratio of wherein said each light emitting setting period are each 2 n (n is an integer of 0 or more) of claims 1 to 5, characterized in that either light emitting display as claimed in any one.
  7. 【請求項7】 電圧の印加に応じて発光する複数の電界発光素子を有する電界発光表示装置の駆動方法において、 1フレーム期間が、それぞれ任意の前記電界発光素子を選択する、複数のアドレス期間を備え、且つそれぞれの前記アドレス期間の後に、当該アドレス期間で選択された前記電界発光素子に駆動電圧を供給する、互いに異なる長さの時間に設定された駆動電圧供給期間を備えることを特徴とする電界発光表示装置の駆動方法。 7. A voltage driving method of an electroluminescent display device having a plurality of light emitting element that emits light in response to application of, one frame period, respectively to select any of the electroluminescent device, a plurality of address periods provided, and after each of the address period, the selected in the address period to supply an electric field driving voltage to the light emitting element, characterized in that it comprises a driving voltage supply period is set to a different length of time from one another the driving method of an electroluminescent display device.
  8. 【請求項8】 前記複数の電界発光素子は、それぞれ一対の電極を有し、前記複数の電界発光素子の前記一対の電極の一方はそれぞれに対応した複数の第1スイッチング回路に接続され、前記複数の電界発光素子の前記一対の電極の他方はそれぞれ第2スイッチング回路に接続され、前記第1スイッチング回路は、前記各アドレス期間毎に前記電界発光素子を選択して接地電圧或いは一定電圧値の駆動電圧のいずれか一方を出力し、前記第2スイッチング回路は、前記各アドレス期間に応じて選択された電界発光素子を前記各アドレス期間に対応する前記駆動電圧供給期間に前記接地電圧或いは前記駆動電圧のいずれか他方を出力することを特徴とする請求項7に記載の電界発光表示装置の駆動方法。 Wherein said plurality of light emitting elements each have a pair of electrodes, wherein one of the plurality of the pair of electrodes of an electroluminescent device is connected to a plurality of first switching circuits corresponding to each of the the other of the pair of electrodes of the plurality of light emitting element is connected to the second switching circuits, respectively, said first switching circuit of each address period the electroluminescent device selected and the ground voltage or a constant voltage value for each and outputs one of the driving voltage, the second switching circuit, the ground voltage or the driving electroluminescent elements selected in response to the respective address period to the driving voltage supply period corresponding to the respective address period the driving method of an electroluminescent display device according to claim 7, characterized in that outputs any other voltage.
  9. 【請求項9】 前記第1スイッチング回路は、走査電圧が供給される走査ラインにゲート電極が接続され、信号電圧が供給される信号ラインにドレイン電極が接続された選択トランジスタと、ゲート電極が前記選択トランジスタのソース電極に接続され、ドレイン電極が前記電界発光素子に接続され、ソース電極が前記接地電圧或いは前記駆動電圧の一方を入力する駆動トランジスタと、を備えることを特徴とする請求項8記載の電界発光表示装置の駆動方法。 Wherein said first switching circuit, the scanning voltage is connected a gate electrode to a scanning line is supplied, a selection transistor having a drain electrode to the signal lines whose signal voltage is supplied is connected, the gate electrode is connected to the source electrode of the selection transistor, a drain electrode connected to the electroluminescent device, according to claim 8, wherein the and a driving transistor source electrode to enter one of the ground voltage or the drive voltage the driving method of the light emitting display.
  10. 【請求項10】 前記走査電圧、前記信号電圧および前記第2スイッチング回路は、それぞれの特性に応じたオン/オフの2値信号が入力されることを特徴とする請求項9記載の電界発光表示装置の駆動方法。 Wherein said scanning voltage, the signal voltage and the second switching circuit, light emitting display of claim 9, wherein the binary signal on / off in accordance with the respective characteristics are input the driving method of the device.
  11. 【請求項11】 前記電界発光素子はマトリクス状に配列され、前記1フレーム期間は、前記アドレス期間と駆動電圧供給期間とが交互に設定されることを特徴とする請求項7〜請求項10のいずれかに記載の電界発光表示装置の駆動方法。 Wherein said light emitting element are arranged in a matrix, wherein one frame period, according to claim 7 claim 10, characterized in that said address period and the driving voltage supplying period is set alternately the driving method of an electroluminescent display device according to any one.
  12. 【請求項12】 前記各駆動電圧供給期間の時間の長さの比率は、それぞれ2のn乗(nは0以上の整数)のいずれかであることを特徴とする請求項7〜請求項11のいずれかに記載の電界発光表示装置の駆動方法。 12. The method of claim 11, wherein the length of time the ratio of the driving voltage supply period, claim 7 of claim 11, (the n 0 or an integer) 2 n, respectively, characterized in that either the driving method of an electroluminescent display device according to any one of.
JP9027323A 1997-01-28 1997-01-28 Electric field light emission display device and its driving method Abandoned JPH10214060A (en)

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JP9027323A JPH10214060A (en) 1997-01-28 1997-01-28 Electric field light emission display device and its driving method
US09/013,708 US5990629A (en) 1997-01-28 1998-01-26 Electroluminescent display device and a driving method thereof
TW87101059A TW441136B (en) 1997-01-28 1998-01-26 An electroluminescent display device and a driving method thereof
CA 2249592 CA2249592C (en) 1997-01-28 1998-01-27 Active matrix electroluminescent display device and a driving method thereof
EP19980900761 EP0906609A1 (en) 1997-01-28 1998-01-27 Active matrix electroluminescent display device and a driving method thereof
CNB988000679A CN1151483C (en) 1997-01-28 1998-01-27 Electroluminescent display device and driving method thereof
PCT/JP1998/000327 WO1998033165A1 (en) 1997-01-28 1998-01-27 Active matrix electroluminescent display device and a driving method thereof

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