JP2010204617A - Display device and method for manufacturing display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device which can be inspected without mounting a driver IC and also without using an expensive panel contact tool, and to provide a method for manufacturing the display device and a method for inspecting the display device. <P>SOLUTION: A data voltage application circuit 16, a data selection circuit 16, and a gate selection circuit 17 connected to a display panel 11 are formed on an optical element substrate. Data is written in an optical element in the display panel 11 by using the data voltage application circuit 15, the data selection circuit 16, and the gate selection circuit 17, and light is emitted. Thus, a probe is not brought into contact with all wirings such as a gate line and data line in the display panel 11. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a display device using an organic EL (electroluminescence) element and a method for manufacturing the display device.

  In general, an organic EL element includes an anode electrode, a cathode electrode, and an electron injection layer, a light emitting layer, a hole injection layer, and the like formed between these electrodes. In the organic EL element, light is emitted by energy generated by recombination of holes supplied from the hole injection layer and electrons supplied from the electron injection layer in the light emitting layer. Such an organic EL element is used as a display device as disclosed in Patent Document 1, and is driven by, for example, a TFT (Thin Film Transistor) provided in each optical element.

  In such a display device, aging and lighting inspection before product shipment are electrically connected to the inspection device by a probe or the like to the driver connection terminal on the panel after mounting the driver IC (Integrated Circuit) or before mounting the driver IC. It is carried out by doing.

JP 2001-195012 A

  By the way, after mounting a driver IC as in the past, aging and lighting inspection are performed, and if a defect is found, it cannot be shipped as a product, and the mounted driver IC is wasted.

  Also, if the driver connection terminals (up to several hundred) on the panel are to be fully contacted with the inspection device using a probe or the like before mounting the driver IC, the probe itself will be expensive and the probe will contact the panel. Load (for example, 4 g per probe can be several kg as a whole), and the contact jig needs to be rigid. As a result, the jig itself is expensive.

  Further, although it is possible to perform aging and lighting inspection by simple driving such as a short circuit between terminals before mounting the driver IC, there is a possibility that inspection items may be limited.

  Thus, there is a need for a display device that can be inspected without mounting a driver IC and without using an expensive panel contact jig and a method for manufacturing the display device.

  The present invention has been made in view of the above-described problems, and provides a display device that can be inspected without mounting a driver IC and without using an expensive panel contact jig, and a method for manufacturing the display device. For the purpose.

In order to achieve the above object, a display device according to the first aspect of the present invention provides:
An optical element formed on a substrate, a driving element for driving the optical element, a selection element for selecting the driving element, a control signal wiring for supplying a control signal to the selection element, and a gradation for the driving element An optical element driving circuit including a gradation signal wiring for supplying a signal;
Formed along one side of the substrate, connected to an output circuit that outputs a voltage value or a current value from the driving element before output, and separated from the output circuit after output. A voltage for measuring a voltage by connecting a current to the gradation signal wiring by connecting a current to the gradation signal wiring; or a line for measuring a current by applying a voltage to the gradation signal wiring;
And a driver formed along the other side of the substrate.

The output circuit includes a transistor formed in the same process as the drive element and the selection element in the optical element drive circuit,
The transistor includes a first wiring connected to the gradation signal wiring, a second wiring connected to a measurement unit that measures a voltage value or a current value according to element characteristics of the driving element, and a third wiring Wiring, a first electrode, a second electrode, and a control electrode,
The control electrode of the transistor is connected to a third wiring; the first electrode is connected to the first wiring; the second electrode is connected to the second wiring;
At the time of output of the output circuit, a current flows or voltage is applied to the gradation signal wiring through the transistor and the first wiring.

The transistor includes an output control transistor,
The output circuit further includes a selection control signal supply circuit that supplies a control signal to the first electrode of the output control transistor.

  The output circuit includes a control signal supply circuit that is connected to the control signal wiring and transmits a control signal to the selection element.

In order to achieve the above object, a method for manufacturing a display device according to the second aspect of the present invention includes:
An optical element formed on a substrate, a driving element for driving the optical element, a selection element for selecting the driving element, a control signal wiring for supplying a control signal to the selection element, and a gradation for the driving element An optical element driving circuit including a gradation signal wiring for supplying a signal; a transistor formed in the same process as the driving element and the selection element in the optical element driving circuit; and along one side on the substrate A circuit forming step of forming an output circuit that is arranged and outputs a voltage value or a current value from the driving element;
After the circuit formation step, the element characteristics of the driving element are either measured by supplying a current to the gradation signal wiring and measuring the voltage, or applying a voltage to the gradation signal wiring and measuring the current. A voltage value or a current value according to the output to the measurement unit, the inspection step of inspecting the drive of the optical element drive circuit by the measurement unit,
After the inspection step, an output circuit dividing step of dividing the output circuit from the optical element driving circuit;
A driver forming step of forming a driver along the other side of the substrate.

  According to the present invention, an output panel formed on a substrate is used to measure a voltage value or a current value corresponding to the element characteristics of a light emission driving transistor at a measuring unit, thereby eliminating an expensive panel without mounting a driver IC. A display device that can be inspected without using a contact jig and a method for manufacturing the display device can be provided.

It is a figure which shows the display apparatus before driver IC mounting. It is a figure which shows the display apparatus after driver IC mounting. It is a figure which shows a gate selection circuit, a data voltage application circuit, and a data selection circuit. It is an equivalent circuit diagram of an optical element drive circuit. (A) is a figure explaining write-in operation | movement, (b) is a figure explaining light emission operation | movement. It is a top view which shows the structural example of an optical element. It is the VII-VII sectional view taken on the line shown in FIG. It is a figure which shows the modification of an optical element drive circuit. It is a figure which shows a shift register circuit. FIG. 10 is a timing chart of the shift register circuit shown in FIG. 9.

  A display device manufacturing method and a display device inspection method according to an embodiment of the present invention will be described with reference to the drawings. In the present embodiment, a display device using a bottom emission type organic EL (electroluminescence) element will be described as an example.

  1 and 2 are diagrams illustrating a configuration example of a display device 10 according to the embodiment. FIG. 1 is a diagram showing the display device 10 before mounting the driver IC, and FIG. 2 is a diagram showing the display device 10 after mounting the driver IC. FIG. 3 is a diagram showing a gate selection circuit, a data voltage application circuit, and a data selection circuit. FIG. 4 is an equivalent circuit diagram of a drive circuit for the optical element. FIG. 5 is a diagram for explaining writing and light emitting operations of the optical element 30. 6 is a plan view of the optical element 30, and FIG. 7 is a sectional view taken along line VII-VII shown in FIG.

  As shown in FIGS. 1 and 2, the display device 10 includes a display panel 11, a gate driver 12, a data driver 13, an anode wiring 14 (La), a data voltage application circuit 15, a data selection circuit (selection control signal). Supply circuit) 16 and a gate selection circuit (control signal supply circuit) 17. The display panel 11 includes n rows × m columns of optical elements 30. The data voltage application circuit 15, the data selection circuit 16, and the gate selection circuit 17 are output circuits used for aging, lighting inspection, transistor characteristic inspection, and the like of the optical element 30. The optical element substrate 31 is formed along each side. In order to separate from the optical element driving circuit DS before mounting the gate driver 12 and the like, the optical element substrate 31 is cut by a laser or glass cut along a cutting line shown by a dotted line in FIG. The application circuit 15, the data selection circuit 16, and the gate selection circuit 17) are omitted from the final display device 10 as shown in FIG.

  As shown in FIG. 1, the data voltage application circuit 15 is provided on one side of the display panel 11 (a side where the data driver 13 is not mounted later is preferable). The reason why the data voltage application circuit 15 is preferably provided on a side different from the side on which the data driver 13 is mounted later is that the data line Ld and the data driver 13 are provided when the data voltage application circuit 15 is provided on the same side as the data driver 13. This is because the wiring for making contact between the data line Ld and the data voltage application circuit may become complicated. As shown in FIG. 3, the data voltage application circuit 15 includes a test data voltage supply wiring (second wiring) Ltd (Ltd1 to Ltd3) formed on one side of the display panel 11 in the row direction, and a display. The inspection gate wiring (third wiring) Ltg (Ltg1 to Ltg3) formed side by side in the row direction on one side of the panel 11, and the data voltage supply wiring Ltd and the inspection gate wiring Ltg in the column direction. An inspection wiring (first wiring) Lt formed side by side, and an output control transistor 51 provided between the data voltage supply wiring and the inspection data wiring are provided.

  The output control transistor 51 is a TFT (Thin Film Transistor) configured by, for example, an n-channel FET (Field Effect Transistor), and includes, for example, a semiconductor layer made of a-Si, a protective insulating film, The amorphous silicon TFT includes a drain electrode, a source electrode, an ohmic contact layer made of a-Si containing an n-type impurity, and a gate electrode. The output control transistor 51 can be formed in the same process as the first selection transistor (selection element) Tr11, the second selection transistor Tr12, and the light emission drive transistor (drive element) Tr13 in the optical element drive circuit. The drain electrode of the output control transistor 51 is connected to the inspection wiring Lt, the source electrode is connected to the data voltage supply wiring Ltd, and the gate electrode is connected to the inspection gate wiring Ltg.

  The inspection wiring Lt is provided in the same number as the number of data lines Ld of the optical element driving circuit DS of the display panel 11. For example, when m optical elements 30 are arranged in the column direction on the display panel 11, M wirings Lt are provided. The inspection wiring Lt is connected to the data line Ld in the display panel 11. In the present embodiment, three data voltage supply lines Ltd and three inspection gate lines Ltg correspond to the three colors of red (R), green (G), and blue (B) of the optical element 30. ing. In the present embodiment, the data voltage supply lines Ltd1 to Ltd3 are connected to a constant current source (not shown), and Vd (red), Vd (green), and Vd (blue) corresponding to the light emission luminance gradation are respectively supplied. . At the time of inspection, the voltage value of the data voltage supply wiring Ltd is measured by the voltage measurement unit (measurement unit) 18. Further, the data voltage supply wiring Ltd may be connected to a constant voltage source.

  Further, Vg (red), Vg (green), and Vg (blue) are respectively supplied to the inspection gate wirings Ltg1 to Ltg1 to 3 from a power source (not shown). Note that the number of the data voltage supply wirings LTD and the number of inspection gate wirings Ltg provided is arbitrary.

  As shown in FIG. 3, the data selection circuit 16 includes a reading transistor 61 and a selection circuit 62 that supplies a high-level or low-level signal. The read transistor 61 is a TFT composed of an n-channel FET (Field Effect Transistor), and includes, for example, a semiconductor layer made of a-Si, a protective insulating film, a drain electrode, and a source electrode. And an amorphous silicon TFT provided with an ohmic contact layer made of a-Si containing an n-type impurity and a gate electrode. The reading transistor 61 can be formed in the same process as the first selection transistor Tr11, the second selection transistor Tr12, and the light emission driving transistor Tr13 in the optical element driving circuit. The reading transistor 61 is provided in each inspection wiring Lt. When the number of the inspection wiring Lt is m, the m reading transistors 61 are provided. The gate of the read transistor 61 is connected to the selection circuit 62, the drain is connected to the inspection wiring Lt, and the source is connected to the voltage measurement unit 18.

  The selection circuit 62 is a so-called shift register circuit including an amorphous silicon TFT (Thin Film Transistor). The selection circuit 62 sequentially outputs high-level (on-level ON) pulses from the reading transistor 61 in the first column to the reading transistor 61 in the m-th column. For example, the shift register circuit has the configuration shown in FIG. 9, and the control signal from the controller is supplied to the drains of the odd-numbered signal output transistors 72 and becomes the output signal OUT, and the even-numbered signal output transistors 72. The clock signal CK2 supplied to the drain and serving as the output signal OUT, the signal φ1 supplied to the gate of the odd-numbered input transistor 71, the signal φ2 supplied to the gate of the even-numbered input transistor 71, the start signal Pst, and the reference voltage Vss is supplied. Among these, the start signal Pst is supplied to the first stage RS (1). The operation of the shift register shown in FIG. 9 is shown in the timing chart of FIG. Note that a capacitance formed in a wiring that is surrounded by a source of the input transistor 71, a gate of the signal output transistor 72, and a drain of the reset transistor 73 in one stage is referred to as a wiring capacitance Ca. In FIG. 10, the 1T period is one line period, and the 1F period is one frame period. Each output signal OUT is supplied to the reading transistor 61.

  The gate selection circuit 17 is connected to the gate line Lg of the optical element driving circuit DS of the display panel 11. The gate selection circuit 17 is a so-called shift register circuit including amorphous silicon TFTs (Thin Film Transistors), and sequentially increases from the first row gate line Lg to the nth gate line Lg (on level ON). The pulse is output. The shift register circuit of the gate selection circuit 17 has substantially the same configuration as the selection circuit 62.

  In the present embodiment, as will be described in detail later, using the output circuits (the data voltage application circuit 15, the data selection circuit 16, and the gate selection circuit 17), the lighting inspection and aging of the optical element 30 and the driving of the optical element 30 are performed. Measurement of transistor characteristics of the circuit DS is performed.

  The gate driver 12 is formed of an IC chip or the like, and sequentially increases from the first row gate line Lg to the nth gate line Lg of the display panel 11 in accordance with a control signal group output from the control circuit. ) Pulse is output.

  The data driver 13 is composed of an IC chip or the like. The data driver 13 is a current driver that applies a gradation current that has a current value according to the image data received by the control circuit, or a voltage that applies a gradation voltage for supplying a current having a current value according to the image data. One of the drivers, and a sink current flows from the first data line Ld to the mth data line Ld.

  In the present embodiment, a lighting test or the like is performed, and the optical circuit board 31 is cut along the cutting line to divide the output circuit from the optical drive circuit DS, and then the gate driver 12 and the data driver 13 are placed on the optical board 31. It is mounted by chip on glass.

  The display panel 11 includes an optical element substrate 31, an organic EL element (optical element) 30 arranged in a matrix on the optical element substrate 31, and a sealing substrate 32 that seals the optical element 30. In the display panel 11, a set of three optical elements 30 that emit three colors of red (R), green (G), and blue (B) on the optical element substrate 31, respectively. For example, m are arranged, and a plurality of, for example, n optical elements of the same color are arranged in the column direction. In this way, m × n optical elements emitting each color of RGB are arranged in a matrix. The three optical elements 30 of red (R), green (G), and blue (B) may be in a delta arrangement. Further, as shown in FIG. 4, the display panel 11 includes an optical element driving circuit DS that actively operates each optical element 30 that emits RGB light.

  As shown in FIGS. 6 and 7, the organic EL element 30 includes an optical element electrode 34, a hole injection layer 36, an interlayer 37, a light emitting layer 38, and a counter electrode 40. The hole injection layer 36, the interlayer 37, and the light emitting layer 38 are carrier transport layers in which electrons and holes are transported as carriers. The carrier transport layer is disposed between the interlayer insulating film 35 and the partition 39 arranged in the column direction.

  As shown in FIG. 4, the optical element driving circuit DS includes a first selection transistor (selection element) Tr11 that selects an optical element, a second selection transistor Tr12, a light emission driving transistor (drive element) Tr13 that drives the optical element, and a capacitor. Cs and the organic EL element 30. The first selection transistor Tr11, the second selection transistor Tr12, and the light emission drive transistor Tr13 are inverted staggered n-channel TFTs (Thin Film Transistors) each including a semiconductor layer having amorphous silicon.

  The optical element driving circuit DS is applied with a plurality of anode lines (current supply wirings) La and a voltage Vss such as a ground potential, which is a cathode formed by a single electrode layer for all the optical elements. An electrode (second electrode) 40, a data line (gradation signal wiring) Ld connected to a plurality of optical element circuits DS arranged in a predetermined column, and a plurality of optical element circuits DS arranged in a predetermined row, respectively. A plurality of gate lines (control signal lines) Lg for selecting the first selection transistor Tr11 and the second selection transistor Tr12 are formed.

  As shown in FIGS. 6 and 7, the gate electrode 11g of the first selection transistor Tr11 is gated through the contact portion 42, which is a contact hole provided in the insulating film 33, and the gate electrode 12g of the second selection transistor Tr12. The anode line La is connected to the line Lg, and is connected to the drain electrode 11d by being stacked on the drain electrode 11d of the first selection transistor Tr11. The source electrode 11s of the first selection transistor Tr11 is connected to the capacitor electrode Cs1 through a contact portion 43 that is a contact hole provided in the insulating film 33.

  The drain electrode 12d of the second selection transistor Tr12 is connected to the source electrode 13s of the light emission drive transistor Tr13 via the optical element electrode (first electrode) 34, and the source electrode 12s is provided on the insulating film 33. It is connected to the data line Ld through a contact portion 41 which is a contact hole. The gate electrode 12g of the second selection transistor Tr12 is connected to the gate line Lg through the contact portion.

  The drain electrode 13d of the light emission drive transistor Tr13 is connected to the anode line La, the gate electrode 13g of the light emission drive transistor Tr13 is connected to the capacitor electrode Cs1 via the contact portion 44, and further via the capacitor electrode Cs1. The first selection transistor Tr11 is connected to the source electrode 11s. Further, the source electrode 13s of the light emission drive transistor Tr13 is connected by partially overlapping the optical element electrode 34.

  The capacitor Cs includes a capacitor electrode Cs1, an optical element electrode 34 that functions as the other capacitor electrode, and an insulating film 33 such as silicon nitride that is a derivative interposed between the capacitor electrode Cs1 and the optical element electrode 34. .

  Next, the writing operation and the light emitting operation of the optical element driving circuit DS will be described.

(Write operation)
In accordance with the control signal group output from the control circuit, the gate driver 12 sequentially outputs a high level (on level ON) pulse from the first row gate line Lg to the nth gate line Lg. Further, during a period (scanning period) during which an ON level ON pulse is output to the gate line Lg of each row, a low level L pulse signal is output from the power source to the anode line La, and the data driver 13 is output from the control circuit. In accordance with the control signal group, a sink current (that is, a current toward the data driver) according to the light emission luminance gradation is generated in the data lines Ld of all columns. The low level L pulse signal supplied to the anode line La is equal to or lower than the reference potential Vss.

  In this way, during the period when the ON level ON pulse is output to the gate line Lg of each row, the first selection transistor Tr11 and the second selection transistor Tr12 are turned on, and the data driver 13 has a voltage value equal to or lower than the reference voltage Vss. The sink current for current control is to flow through the data line Ld of each column. Therefore, a voltage corresponding to the current value of the sink current is applied to one end of the gate and source of the light emission drive transistor Tr13, and as shown in FIG. 5A, the data line Ld and the second selection transistor Tr12 are used. A sink current flows through the light emission drive transistor Tr13.

  Since the potential of the gate electrode 13g of the light emission drive transistor Tr13 is equal to the potential of the drain electrode 13d, a potential difference is generated between the gate and the source of the light emission drive transistor Tr13, and the data line Ld follows the voltage specified by the data driver. The sink current I having the current value (that is, the current value according to the image data) flows in the direction indicated by the arrow K shown in FIG. In the scanning period, since the power supply signal voltage of the anode line La is equal to or lower than the reference voltage H, the anode potential of the organic EL element 30 is lower than the cathode potential, and a reverse bias voltage is applied to the organic EL element 30. Will be. Therefore, current from the anode line La does not flow through the organic EL element 30.

  At this time, both ends of the capacitor Cs of the optical element 30 become a voltage according to the current value of the current flowing through the drain 13d-source electrode 13s of the light emission drive transistor Tr13 based on the gradation signal controlled by the data driver 13. That is, a potential difference between the gate and the source of each light emission drive transistor Tr13 is generated in the capacitor Cs of the optical element 30 such that the current I according to the gradation signal flows to each light emission drive transistor Tr13 of the organic EL element 30. Charge is charged.

(Light emission operation)
The pulse output from the gate driver 12 to the gate line Lg is switched from ON level ON to OFF level OFF, and the signal output from the power source to the anode line La is switched from low level L to high level H. A scanning signal voltage of OFF level OFF (low level) is applied to the gate of the first selection transistor Tr11 and the gate of the second selection transistor Tr12 to the gate line Lg, and the power supply signal voltage applied to the anode line La is a reference potential. The power supply voltage H is a high level sufficiently higher than Vss and the low level L.

  Therefore, as shown in FIG. 5B, the second selection transistor Tr12 in the non-selected row is turned off, and no current flows through the second selection transistor Tr12. Further, the first selection transistor Tr11 is turned off, the capacitor Cs continues to hold the charge charged by one end and the other end thereof, and the light emission drive transistor Tr13 continues to maintain the on state. That is, the gate-source voltage value Vgs of the light emission drive transistor Tr13 is held. Therefore, even during the light emission period, the light emission drive transistor Tr13 keeps flowing a current having a current value according to the image data, so that the current value of the current I in the light emission period is equal to the current value of the current K in the writing period. During the light emission period, the current K flowing through the light emission drive transistor Tr13 flows into the organic EL element 30, and emits light with luminance according to the current value of the current I flowing through the organic EL element 30. In this way, the organic EL element 30 emits light at a luminance gradation according to the gradation signal.

  In the present embodiment, operations similar to the above-described write operation and light emission operation are performed by using the data voltage application circuit 15, the data selection circuit 16, and the gate selection circuit 17, thereby performing a lighting test, an aging test, and transistor characteristics. Measure.

(Lighting inspection)
Also in the lighting inspection, the writing operation and the light emitting operation are performed for the optical element driving circuit DS as described above to check the lighting. In the lighting inspection, white, gray, black, and checkered patterns are displayed, and there are no point defects (dark spots / bright spots) and line defects (total dead lines / total bright lines / intermediate extinction lines / intermediate bright lines). Inspection is performed for inspection items such as that the luminance variation between elements is within a reference value (for example, within 4%) and that the in-plane luminance variation is within a reference value (for example, within 10%). In the following, an example in which lighting inspection is performed on the red (R) optical element 30 in s rows and t columns will be described.

  First, during a write operation, a high level (on level ON) pulse is sequentially output from the gate selection circuit 17 to the gate line Lg of the first row from the gate line Lg of the first row. Here, a low level L signal is output from the power source to the s row anode line La during a period (scanning period) in which an ON level ON pulse is output to the s row gate line Lg. The low level L pulse signal supplied to the anode line La is equal to or lower than the reference potential Vss.

  During this scanning period, a high level signal is supplied from the selection circuit 62 of the data selection circuit 16 to the read transistors 61 in the t column, and the read transistors 61 are turned on. At the same time, a high level (on level) signal is supplied to the inspection gate wiring Ltg (here, for example, Ltg1) corresponding to the t column, and the output control transistor 51 is turned on. In addition, a sink current (that is, a current from the optical element toward the data voltage supply wiring Ltd) from the constant current source is supplied to the data voltage supply wiring Ltd (here, for example, LTd1), and the voltage Vd ( supply red). At this time, the voltage value of the data voltage supply wiring Ltd is measured by the voltage measuring unit 18.

  At this time, the first selection transistor Tr11 and the second selection transistor Tr12 of the optical element driving circuit DS are turned on, so that a sink current is caused to flow to the data voltage supply wiring Ltd. As a result, as shown in FIG. 5A, a voltage corresponding to the current value of the sink current is applied to one end of the gate and source of the light emission drive transistor Tr13. Thereby, it can be confirmed that there is no defect in the predetermined optical element driving circuit DS.

  In the scanning period, the anode potential of the organic EL element 30 is lower than the cathode potential, and no current from the anode line La flows through the organic EL element 30. The capacitor Cs of the optical element 30 is charged with a charge that causes a potential difference between the gate and the source of each light emission drive transistor Tr13 that causes the current I according to the gradation signal to flow to the light emission drive transistor Tr13 of the optical element 30. Is done.

  Next, a light emission operation is performed.

  A pulse output from the gate selection circuit 17 to the gate line Lg is switched from ON level ON to OFF level OFF, and a signal output from the power source to the anode line La is switched from low level L to high level H. As a result, the gate of the first selection transistor Tr11 and the gate of the second selection transistor Tr12 are turned off.

  Further, a low level signal is supplied from the selection circuit 62 of the data selection circuit 16 to the read transistor 61 in the t column, and the read transistor 61 is turned off. At the same time, a low level (off level) signal is also supplied to the inspection gate wiring Ltg (here, for example, Ltg1) corresponding to the t column, and the output control transistor 51 is turned off.

  Therefore, as shown in FIG. 5B, the second selection transistor Tr12 in the non-selected row is turned off, and no current flows through the second selection transistor Tr12. Further, the first selection transistor Tr11 is turned off, the capacitor Cs continues to hold the charge charged by one end and the other end thereof, and the light emission drive transistor Tr13 continues to maintain the on state. The light emission drive transistor Tr13 continues to pass a current having a current value according to the image data. In this way, the organic EL element 30 emits light at a luminance gradation according to the gradation signal.

  In the aging inspection, the writing operation and the light emitting operation are performed in a high temperature (for example, 60 ° C.) environment, and the optical element 30 is caused to emit light for a time (for example, 1 hour) in which a desired aging effect is obtained. Inspecting whether the lighting inspection standard is satisfied and whether the power consumption, luminance, and chromaticity coordinate values are within the initial specification range is performed.

  By performing the above writing operation and light emitting operation, it is possible to inspect whether or not the desired optical element 30 emits light normally. As described above, in the present embodiment, the gate line Lg is turned on / off by the gate selection circuit 17, and writing to the light emission drive transistor Tr 13 is performed by the data selection circuit 16 and the data voltage application circuit 15. Thereby, in order to light each optical element 30, it becomes possible to perform a lighting test and an aging test without providing a probe for each wiring.

(Measurement of transistor characteristics)
In the characteristic measurement, the current value and the voltage value flowing through the light emission drive transistor Tr13 are measured by performing the same operation as the write operation of the lighting test described above. Hereinafter, a case where the transistor characteristics of the light emission driving transistor Tr13 of the red (R) optical element 30 of s rows and t columns is measured will be described as an example.

  First, in the same manner as the lighting test writing operation described above, a low level L is supplied from the power source to the s row anode line La during a period (scanning period) during which an ON level ON pulse is output to the s row gate line Lg. Is output. During this scanning period, a high level signal is supplied from the selection circuit 62 of the data selection circuit 16 to the read transistors 61 in the t column, and the read transistors 61 are turned on. At the same time, a high level (on level) signal is supplied to the inspection gate wiring Ltg (here, for example, Ltg1) corresponding to the t column, and the output control transistor 51 is turned on. In addition, a sink current (that is, a current from the optical element toward the data voltage supply wiring Ltd) from the constant current source is supplied to the data voltage supply wiring Ltd (here, for example, LTd1), and the voltage Vd ( red).

  At this time, the first selection transistor Tr11 and the second selection transistor Tr12 of the optical element driving circuit DS are turned on, so that a sink current is caused to flow to the data voltage supply wiring Ltd. As a result, as shown in FIG. 5A, a voltage corresponding to the current value of the sink current is applied to one end of the gate and source of the light emission drive transistor Tr13.

  At this time, the voltage measurement unit 18 measures the voltage value of the inspection wiring Lt. As described above, a constant current flows through the inspection wiring Lt and the data voltage supply wiring Ltd by the constant current source. Therefore, the current-voltage characteristic can be measured by appropriately changing the current supplied from the constant current source and measuring the voltage value corresponding to the element characteristic of the light emission drive transistor Tr13 by the voltage measuring unit 18. The measurement values obtained in this way can also be used for driving the display panel 11.

  Hereinafter, the configuration of the organic EL element 30 will be described.

  On the optical element substrate 31 of each optical element, gate electrodes 11g, 12g, and 13g of the first selection transistor Tr11, the second selection transistor Tr12, and the light emission drive transistor Tr13 formed by patterning the gate conductive layer are formed. Further, on the optical element substrate 31 of each optical element, one electrode Cs1 of the capacitor Cs is formed, and a data line Ld extending along the column direction is formed. Further, a gate insulating film is formed so as to cover them. Then, an insulating film 33 that functions as a dielectric of the capacitor is formed.

  When the organic EL element 30 is a bottom emission type that emits display light from the optical element substrate 31 side, the capacitor electrode Cs1 and the optical element electrode 34 are indium thin oxide (ITO) or zinc oxide to which tin oxide is added. A transparent electrode such as doped indium oxide (Indium Zinc Oxide) is formed, and the gate electrode 13g of the light emission drive transistor Tr13 is formed to overlap the capacitor electrode Cs1 in the contact portion 44.

  The insulating film 33 is formed of an insulating material such as a silicon oxide film or a silicon nitride film, and is formed on the optical element substrate 31 so as to cover the data line Ld, the gate electrodes 12g and 13g, and the capacitor electrode Cs1. Is done. A contact portion as a contact hole is formed in the insulating film 33 to make contact between the gate conductive layer and the source / drain layer.

  The first selection transistor Tr11, the second selection transistor Tr12, and the light emission drive transistor Tr13 are each an n-channel thin film transistor (TFT). Each transistor is formed on an optical element substrate 31 as shown in FIG. As shown in FIG. 7, the second selection transistor Tr12 is made of a semiconductor layer 121 made of a-Si, a protective insulating film 122, a drain electrode 12d, a source electrode 12s, and a-Si containing an n-type impurity. Ohmic contact layers 124 and 125, and a gate electrode 12g are provided. The light emitting drive transistor Tr13 includes a semiconductor layer 131 made of a-Si, a protective insulating film 132, a drain electrode 13d, a source electrode 13s, and ohmic contact layers 134 and 135 made of a-Si containing n-type impurities. And a gate electrode 13g. Although not shown, the first selection transistor Tr11 has the same configuration as the second selection transistor Tr12.

  In each of the transistors Tr11, Tr12, and Tr13, the gate electrode is selected from at least one of, for example, a Mo film, a Cr film, an Al film, a Cr / Al laminated film, an AlTi alloy film, an AlNdTi alloy film, a MoNb alloy film, and the like. It is formed from an opaque gate conductive layer. The drain electrode and the source electrode are each formed of a source-drain conductive layer such as aluminum-titanium (AlTi) / Cr, AlNdTi / Cr, or Cr. In addition, an ohmic contact layer is formed between the drain electrode and the source electrode and the semiconductor layer for low resistance contact.

  The optical element electrode (anode electrode) 34 is made of a light-transmitting conductive material such as indium oxide (ITO) to which tin oxide is added, zinc oxide-doped indium oxide (Indium Zinc Oxide), or the like. Is done.

  The interlayer insulating film 35 is formed from an insulating material such as a silicon nitride film. An opening 35 a is formed in the interlayer insulating film 35, and a light emitting layer 38 interposed between the optical element electrode 34 and the counter electrode 40, that is, a light emitting region of the optical element 30 is defined by the opening 35 a. Further, a groove-like opening 39 b extending in the column direction (vertical direction in FIG. 3) is formed in the partition wall 39 over the plurality of optical elements 30.

  The partition 39 is formed on the interlayer insulating film 35 by curing an insulating material, for example, a photosensitive resin such as polyimide. The partition 39 is formed in a stripe shape as shown in FIG. 6 and includes an opening 39b. The partition wall 39 is partitioned so as not to flow out to the optical elements 30 that emit different colors adjacent to each other in the row direction during the manufacturing process, and prevents color mixing of the light emitting layer 38. The planar shape of the partition wall 39 is not limited to this and may be a lattice shape.

  The hole injection layer 36 is formed on the optical element electrode 34 and has a function of supplying holes to the light emitting layer 38. The hole injection layer 36 includes an organic polymer material, a low molecular material, or an inorganic compound that can inject and transport holes.

  The interlayer 37 is formed on the hole injection layer 36. The interlayer 37 has a function of suppressing the hole injection property of the hole injection layer 36 to facilitate recombination of electrons and holes in the light emitting layer 38, in order to increase the light emission efficiency of the light emitting layer 38. It is an organic compound layer provided.

  The light emitting layer 38 is formed on the interlayer 37. The light emitting layer 38 has a function of generating light by applying a voltage between the anode electrode and the cathode electrode. The light emitting layer 38 is a known polymer light emitting material capable of emitting fluorescence or phosphorescence, for example, red (R) or green (G) containing a conjugated double bond polymer such as polyparaphenylene vinylene or polyfluorene. And a blue (B) light emitting material.

  Further, in the case of the bottom emission type, the counter electrode (cathode electrode) 40 is provided on the light emitting layer 38 side, a layer made of a conductive material, for example, a material having a low work function such as Li, Mg, Ca, Ba, and the like. A laminated structure having a light-reflective conductive layer such as Al laminated thereon. In the case of the top emission type, it is provided on the light emitting layer 38 side and is extremely thin with a thickness of about 10 nm, for example, Li, Mg, Ca, Ba A transparent laminated structure having a light transmissive low work function layer made of a material having a low work function such as ITO and a light transmissive conductive layer such as ITO having a thickness of about 100 nm to 200 nm. In the present embodiment, the counter electrode 40 is composed of a single electrode layer formed across a plurality of optical elements 30, and for example, a common voltage Vss that is a ground potential is applied.

  As described above, in the display device according to the present embodiment, the test data voltage application circuit 15, the data selection circuit 16, and the gate selection circuit 17 are formed, and these are used to check the lighting without mounting the driver IC. Etc. can be performed. Further, the data voltage application circuit is composed of the data voltage supply wiring, the inspection gate wiring, the inspection wiring, and the transistors connected thereto, so that the probe can be connected to each data line without contacting the probe. A voltage can be supplied to the data line. For this reason, the number of probes can be reduced, the load on the display panel can be reduced, and inspection can be performed without using an expensive panel contact jig that supports a large number of probes. It is.

The present invention is not limited to the above-described embodiments, and various modifications and applications are possible.
In the above-described embodiment, an example in which the gate selection circuit 17 that supplies the selection signal to the gate line Lg, the data voltage supply circuit 15 that supplies the gradation signal to the data line Ld, and the data selection circuit 16 is provided. As described above, it is also possible to form any one or only two of the gate selection circuit 17, the data voltage supply circuit 15, and the data selection circuit 16 as a test circuit.
In the above-described embodiment, the organic EL element has been described as an example. However, the present invention is not limited to this, and a liquid crystal display element may be used. In that case, the optical element means a liquid crystal display element including a backlight.

  In the above-described embodiment, the bottom emission type organic EL element has been described as an example. When the organic EL element 30 is a top emission type that emits display light from the counter electrode 40 side, the counter electrode 40 is a transparent electrode such as ITO, but the capacitor electrode Cs1 does not need to be transparent, and therefore the capacitor electrode Cs1 Can be formed integrally and integrally with the gate electrode 13g of the light emission drive transistor Tr13 by patterning the gate conductive layer. Since the gate conductive layer can be patterned at once by photolithography, if it is a top emission type, the manufacturing process of these members can be simplified. Furthermore, the display device may be monochromatic.

  In the above-described embodiment, the organic EL element has been described by taking as an example a configuration including three layers of a hole injection layer, an interlayer, and a light emitting layer, but the present invention is not limited thereto, and for example, a hole injection layer and a light emitting layer. As described above, a two-layer structure may be used, a light-emitting layer may have a single-layer structure that also serves as a hole injection layer, or a four-layer structure or more.

  In the above-described embodiments, the case where the transistor is an inverted stagger type is described as an example. However, the transistor is not limited to this and may be a coplanar type.

  In each of the above-described embodiments, the lighting circuit that emits light from the organic EL element has been described as an example including three transistors. However, the present invention is not limited thereto, and includes two transistors as illustrated in FIG. Alternatively, four or more transistors may be provided.

  DESCRIPTION OF SYMBOLS 10 ... Display apparatus, 11 ... Display panel, 12 ... Gate driver, 13 ... Data driver, 14 ... Anode wiring, 15 ... Data voltage application circuit, 16 ... Data selection Circuit, 17 ... Gate selection circuit, 18 ... Voltage measurement unit, 30 ... Optical element, 31 ... Optical element substrate, 32 ... Sealing substrate, 33 ... Insulating film, 34. ..Optical element electrodes, 35... Interlayer insulating film, 36... Hole injection layer, 37 ..interlayer, 38 .. light emitting layer, 39. La ... anode line, Lg ... gate line, Ld ... data line, Ltd ... data voltage supply wiring, Ltg ... inspection gate wiring, Lt ... inspection wiring, Tr11 ... 1st selection transistor, Tr12 ... 2nd selection Transistors, Tr13 ··· emission driving transistor

Claims (5)

An optical element formed on a substrate, a driving element for driving the optical element, a selection element for selecting the driving element, a control signal wiring for supplying a control signal to the selection element, and a gradation for the driving element An optical element driving circuit including a gradation signal wiring for supplying a signal;
Formed along one side of the substrate, connected to an output circuit that outputs a voltage value or a current value from the driving element before output, and separated from the output circuit after output. A voltage for measuring a voltage by connecting a current to the gradation signal wiring by connecting a current to the gradation signal wiring; or a line for measuring a current by applying a voltage to the gradation signal wiring;
And a driver formed along the other side of the substrate. The output circuit includes a transistor formed in the same process as the drive element and the selection element in the optical element drive circuit,
The transistor includes a first wiring connected to the gradation signal wiring, a second wiring connected to a measurement unit that measures a voltage value or a current value according to element characteristics of the driving element, and a third wiring Wiring, a first electrode, a second electrode, and a control electrode,
The control electrode of the transistor is connected to a third wiring; the first electrode is connected to the first wiring; the second electrode is connected to the second wiring;
2. The display device according to claim 1, wherein a current flows or voltage is applied to the gradation signal wiring through the transistor and the first wiring at the time of output of the output circuit. The transistor includes an output control transistor,
The display device according to claim 2, wherein the output circuit further includes a selection control signal supply circuit that supplies a control signal to the first electrode of the output control transistor.   4. The display device according to claim 1, wherein the output circuit includes a control signal supply circuit that is connected to the control signal wiring and transmits a control signal to the selection element. 5. An optical element formed on a substrate, a driving element for driving the optical element, a selection element for selecting the driving element, a control signal wiring for supplying a control signal to the selection element, and a gradation for the driving element An optical element driving circuit including a gradation signal wiring for supplying a signal; a transistor formed in the same process as the driving element and the selection element in the optical element driving circuit; and along one side on the substrate A circuit forming step of forming an output circuit that is arranged and outputs a voltage value or a current value from the driving element;
After the circuit formation step, the element characteristics of the driving element are either measured by supplying a current to the gradation signal wiring and measuring the voltage, or applying a voltage to the gradation signal wiring and measuring the current. A voltage value or a current value according to the output to the measurement unit, the inspection step of inspecting the drive of the optical element drive circuit by the measurement unit,
After the inspection step, an output circuit dividing step of dividing the output circuit from the optical element driving circuit;
And a driver forming step of forming a driver along the other side of the substrate.

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