JP4748317B2 - Terminal electrodes and electronic components - Google Patents
Terminal electrodes and electronic components Download PDFInfo
- Publication number
- JP4748317B2 JP4748317B2 JP2006234798A JP2006234798A JP4748317B2 JP 4748317 B2 JP4748317 B2 JP 4748317B2 JP 2006234798 A JP2006234798 A JP 2006234798A JP 2006234798 A JP2006234798 A JP 2006234798A JP 4748317 B2 JP4748317 B2 JP 4748317B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- base
- conductor layer
- electrode
- main
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000010410 layer Substances 0.000 claims description 218
- 239000004020 conductor Substances 0.000 claims description 128
- 239000010408 film Substances 0.000 claims description 85
- 239000010949 copper Substances 0.000 claims description 67
- 239000000758 substrate Substances 0.000 claims description 48
- 238000007747 plating Methods 0.000 claims description 32
- 239000000463 material Substances 0.000 claims description 19
- 239000011651 chromium Substances 0.000 claims description 18
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 15
- 230000004888 barrier function Effects 0.000 claims description 14
- 239000002245 particle Substances 0.000 claims description 14
- 229910052802 copper Inorganic materials 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 239000002344 surface layer Substances 0.000 claims description 12
- 238000007740 vapor deposition Methods 0.000 claims description 11
- 229910052709 silver Inorganic materials 0.000 claims description 10
- 239000010409 thin film Substances 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 7
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- 229910018487 Ni—Cr Inorganic materials 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 229910052804 chromium Inorganic materials 0.000 claims description 5
- VNNRSPGTAMTISX-UHFFFAOYSA-N chromium nickel Chemical compound [Cr].[Ni] VNNRSPGTAMTISX-UHFFFAOYSA-N 0.000 claims description 5
- 239000010936 titanium Substances 0.000 claims description 5
- 239000011800 void material Substances 0.000 claims description 5
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 2
- 239000007791 liquid phase Substances 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 229910000679 solder Inorganic materials 0.000 description 16
- 238000007772 electroless plating Methods 0.000 description 15
- 238000009713 electroplating Methods 0.000 description 14
- 239000010931 gold Substances 0.000 description 14
- 239000011135 tin Substances 0.000 description 12
- 238000004544 sputter deposition Methods 0.000 description 11
- 229910052718 tin Inorganic materials 0.000 description 8
- 229910052737 gold Inorganic materials 0.000 description 7
- 230000005540 biological transmission Effects 0.000 description 6
- 239000010944 silver (metal) Substances 0.000 description 6
- 239000012528 membrane Substances 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 238000005275 alloying Methods 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 239000010419 fine particle Substances 0.000 description 2
- 238000010304 firing Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910017944 Ag—Cu Inorganic materials 0.000 description 1
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910020836 Sn-Ag Inorganic materials 0.000 description 1
- 229910020988 Sn—Ag Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000000469 dry deposition Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000011256 inorganic filler Substances 0.000 description 1
- 229910003475 inorganic filler Inorganic materials 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 239000002923 metal particle Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- JBQYATWDVHIOAR-UHFFFAOYSA-N tellanylidenegermanium Chemical compound [Te]=[Ge] JBQYATWDVHIOAR-UHFFFAOYSA-N 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Description
本発明は、端子電極および電子部品に係り、特に、外部との電気的な接続を行うため電子部品に備えられる外部接続端子の構造に関する。 The present invention relates to a terminal electrode and an electronic component, and more particularly, to a structure of an external connection terminal provided in the electronic component for electrical connection with the outside.
チップコンデンサやチップインダクタ、チップ抵抗器などの各種の個別部品、あるいは複数の能動・受動素子を組み合わせた様々な電子デバイスなどの電子部品が今日提供されているが、いずれの電子部品にあっても、外部と電気的・機械的な接続を行い、配線基板への実装を可能とするために当該電子部品には接続端子が必要となる。 Various electronic parts such as chip capacitors, chip inductors, chip resistors, and various electronic devices that combine multiple active / passive elements are provided today. In order to perform electrical and mechanical connection with the outside and enable mounting on the wiring board, the electronic component requires a connection terminal.
かかる接続端子の一例として、例えばＬＴＣＣ基板を用いた電子部品の端子電極は、ＡｇやＣｕ、或いはＡｇとＣｕ、ＡｇとＣｕとＳｎ、ＡｇとＣｕとＮｉなどを組み合わせた導電性微粒子をバインダに混ぜてペースト状にした導電性ペースト或いは導電性樹脂をベース基板に塗布し乾燥することによって下地電極を形成し、さらにその上にＮｉとＳｎ、或いはＮｉとＡｕなどの金属をめっき成長させることにより形成される。 As an example of such a connection terminal, for example, a terminal electrode of an electronic component using an LTCC substrate is made of Ag and Cu, or Ag and Cu, Ag and Cu and Sn, Ag and Cu and Ni combined with conductive fine particles as a binder. A base electrode is formed by applying a conductive paste or conductive resin mixed into a paste to a base substrate and drying, and further, a metal such as Ni and Sn, or Ni and Au is grown on the base by plating. It is formed.
ところで、従来の端子電極は、上述のように一般に導電性ペースト（又は導電性樹脂）を使用するから、これを焼成硬化させるために製造過程で５００℃以上の高温処理が必要となる。したがって、従来の電子部品においては、使用する材料に少なくともこの温度以上の耐熱性が求められ、使用可能な材料が耐熱性の高いものに限られてしまうという問題がある。 By the way, since the conventional terminal electrode generally uses a conductive paste (or conductive resin) as described above, a high-temperature treatment of 500 ° C. or higher is required in the manufacturing process in order to fire and cure the paste. Therefore, in the conventional electronic component, there is a problem that the material to be used is required to have a heat resistance of at least this temperature or more and the usable material is limited to a material having a high heat resistance.
一方、ナノペースト技術の進歩と共に導電性樹脂の開発が進み、３００℃以下の熱処理で硬化可能な材料も近年提供されてはいる。しかしながら、これらは未だ高価であり、量産品として必然的にコスト面の制約を受ける電子部品製品に使用することは難しいのが現状である。 On the other hand, with the progress of nano paste technology, the development of conductive resins has progressed, and materials that can be cured by heat treatment at 300 ° C. or lower have been provided in recent years. However, these are still expensive, and it is difficult to use them for electronic component products that are inevitably limited in cost as mass-produced products.
また、導電性ペーストを用いる端子電極の形成方法では、年々小型化する電子部品に対して十分な寸法精度をもって電極を形成することが困難になりつつある。なぜなら、ペースト材は流動性を持ち、塗布条件、例えば塗布される面の粗さや活性状態（濡れ性）、周囲環境（雰囲気）、ペースト量などの様々な要因によって塗布精度にばらつきが生じやすいからである。特に、高周波用の電子部品では、実装精度の要求から端子寸法の厳格な精度が求められ、微細な電子部品製品に備えられる複数の端子に対して均等にペーストによって電極を形成することは容易ではない。また、例えば部品左右における端子電極の形状寸法のばらつき・不均衡は、はんだリフロー実装時にチップが立って実装不良を起す所謂マンハッタン現象（ツームストーン現象）の一因ともなり得る。 Moreover, in the method of forming a terminal electrode using a conductive paste, it is becoming difficult to form an electrode with sufficient dimensional accuracy for electronic components that are becoming smaller year by year. This is because the paste material has fluidity, and the coating accuracy is likely to vary due to various factors such as coating conditions such as roughness of the surface to be applied, active state (wetting), ambient environment (atmosphere), and paste amount. It is. In particular, in high-frequency electronic components, strict accuracy of terminal dimensions is required due to the requirement of mounting accuracy, and it is not easy to form electrodes uniformly by paste for multiple terminals provided in fine electronic component products. Absent. In addition, for example, variations and imbalances in the shape of terminal electrodes on the left and right sides of a component can contribute to a so-called Manhattan phenomenon (tombstone phenomenon) in which a chip stands and causes mounting failure during solder reflow mounting.
さらに導電性ペーストは、有機成分やＳｉ系の媒体を含有する。これらは高温で焼成することによって電極から排出されるが、残った導電性材料の状態は緻密さに欠け、高温焼成によって導体材料の表面は酸化膜で覆われている。このため、端子めっき処理をその後行った場合に下地電極と端子めっきとの界面の接合状態が合金層とアンカー作用による接合からなっていると考えられ、表面の状態によっては接合性が不安定になるおそれがある。 Further, the conductive paste contains an organic component and a Si-based medium. These are discharged from the electrode by firing at a high temperature, but the state of the remaining conductive material is not dense, and the surface of the conductor material is covered with an oxide film by the high-temperature firing. For this reason, when the terminal plating process is performed afterwards, it is considered that the bonding state at the interface between the base electrode and the terminal plating is formed by bonding with the alloy layer and the anchor action, and the bonding property may be unstable depending on the surface state. There is a risk.
他方、導電性樹脂の場合には、熱処理温度が３００℃以下と比較的低温であるため、媒体材料が下地電極内に含有されたままの状態となる。したがって、下地電極の表面に導体粒子が多数露出していれば端子めっき面との界面の密着性は良好となるものの、導体粒子の露出が少ない部分については、端子めっきとの界面の接合性が低下する難がある。 On the other hand, in the case of a conductive resin, the heat treatment temperature is relatively low at 300 ° C. or lower, so that the medium material remains contained in the base electrode. Therefore, if a large number of conductor particles are exposed on the surface of the base electrode, the adhesion at the interface with the terminal plating surface will be good, but the interface with the terminal plating will not be bonded to the portion where the conductor particle exposure is small. There is a difficulty to decline.
したがって、本発明の目的は、このような従来の端子電極における問題を解決することにあり、寸法精度が高く、接合強度（ベース基板との間ならびに端子構成膜間の接合性）に優れた信頼性の高い新たな端子構造を得ることにある。 Therefore, an object of the present invention is to solve such a problem in the conventional terminal electrode, and has high dimensional accuracy and excellent reliability in bonding strength (bonding between the base substrate and the terminal component film). The object is to obtain a new terminal structure with high performance.
前記課題を解決し目的を達成するため、本発明に係る端子電極は、導電性材料を含みかつベース基板上に備えられて電気的な接続を行う端子電極であって、前記ベース基板上に形成された下地電極層と、この下地電極層の上に形成された主電極層とを備え、前記主電極層は、めっき金属からなる主導体層を含み、前記下地電極層は、当該主導体層をめっき成長させるときの通電層となる下地導体層を含む。 In order to solve the above problems and achieve the object, a terminal electrode according to the present invention is a terminal electrode that includes a conductive material and is provided on a base substrate for electrical connection, and is formed on the base substrate. A base electrode layer formed on the base electrode layer, the main electrode layer including a main conductor layer made of a plated metal, and the base electrode layer includes the main conductor layer. Including a base conductor layer that serves as an energization layer for plating growth.
本発明の端子電極は、電気的接続を行うためベース基板上に備えられる端子電極であるが、当該ベース基板上に形成した下地電極層とこの下地電極層の上に形成した主電極層とを有する。主電極層は、例えば電流を流し信号を通過させるなど電気的な接続を行う端子本来の機能を果たす主導体層を含み、電極本体となる部分である。この主導体層は、液相成膜法（湿式成膜法）、すなわち電解めっき又は無電解めっきにより形成する。ただし、製造コスト並びに生産性の点で有利な電解めっきによることが望ましい。 The terminal electrode of the present invention is a terminal electrode provided on a base substrate for electrical connection. A base electrode layer formed on the base substrate and a main electrode layer formed on the base electrode layer are provided. Have. The main electrode layer includes a main conductor layer that performs the original function of a terminal that performs electrical connection, for example, by passing a current and passing a signal, and is a portion that becomes an electrode body. The main conductor layer is formed by a liquid phase film formation method (wet film formation method), that is, electrolytic plating or electroless plating. However, it is desirable to use electrolytic plating which is advantageous in terms of manufacturing cost and productivity.
一方、上記下地電極層は、当該主電極層をめっき成長によって形成するときに通電層となる下地導体層を含み、この下地導体層の上に上記主導体層をめっき成長させる。下地導体層は、好ましくは気相成膜法（乾式成膜法）、すなわち蒸着法、スパッタ法、又は気相成長法（ＣＶＤ法）等により形成する。ベース基板との良好な接合性を得るためである。ただし、気相成膜法以外にも、無電解めっきにより形成することも可能である。 On the other hand, the base electrode layer includes a base conductor layer that becomes an energization layer when the main electrode layer is formed by plating growth, and the main conductor layer is grown by plating on the base conductor layer. The underlying conductor layer is preferably formed by vapor deposition (dry deposition), that is, vapor deposition, sputtering, or vapor deposition (CVD). This is to obtain good bondability with the base substrate. However, it can also be formed by electroless plating other than the vapor deposition method.
主導体層は、低電気抵抗で損失が少なくコスト的にも有利な銅（Ｃｕ）を主成分とする膜により構成することが望ましく、下地導体層は、当該主導体層との良好な接合性を得るために同じく銅（Ｃｕ）を主成分とする膜により構成することが好ましい。ただし本発明は、銅以外の材料の使用を排除するものではなく、他の導電材料（金属や合金）を使用することも可能である。また、ベース基板としては、例えばアルミナ基板が挙げられるが、これに限定されるものではなく、他のセラミック基板、あるいは有機材料や有機材料に無機フィラーを混合した複合材料からなる基板、シリコン基板などの半導体基板、金属基板その他であって良い。尚、半導体基板や金属基板を用いる場合には、端子電極の形成領域に対して、基板の表面を絶縁する処理を施していても良い。 The main conductor layer is preferably composed of a film mainly composed of copper (Cu), which has low electrical resistance, low loss, and is advantageous in terms of cost, and the underlying conductor layer has good bondability with the main conductor layer. In order to obtain the same, it is preferable to use a film mainly composed of copper (Cu). However, the present invention does not exclude the use of materials other than copper, and other conductive materials (metals and alloys) can also be used. Examples of the base substrate include, but are not limited to, an alumina substrate, other ceramic substrates, substrates made of organic materials or organic materials mixed with inorganic fillers, silicon substrates, and the like. It may be a semiconductor substrate, a metal substrate, or the like. When a semiconductor substrate or a metal substrate is used, a process for insulating the surface of the substrate may be performed on the terminal electrode formation region.
本発明の端子電極では、典型的には、主導体層は下地導体層より厚さ寸法が大きい。本発明の好ましい構成例として、下地導体層をベース基板との良好な接合性が得られるスパッタ等の気相成膜法による薄膜により形成し、この上に電解めっきによるいわゆる厚付めっきを施して、電気抵抗の低減と機械的強度の向上を図るためである。例えば電子部品の角部は実装工程その他のハンドリング中に損傷を受けやすい部分であるが、このように下地導体層より主導体層を厚く成膜することによって端子電極の機械的な強度を高め、衝撃を受けたとしても断線や欠損による電気抵抗の増大等の問題が発生することを防ぐことが出来る。 In the terminal electrode of the present invention, typically, the main conductor layer has a thickness dimension larger than that of the base conductor layer. As a preferred configuration example of the present invention, a base conductor layer is formed by a thin film by a vapor deposition method such as sputtering that can provide good bonding with a base substrate, and a so-called thick plating by electrolytic plating is performed thereon. This is because the electrical resistance is reduced and the mechanical strength is improved. For example, the corner of an electronic component is a part that is easily damaged during the mounting process and other handling, but by increasing the mechanical strength of the terminal electrode by forming the main conductor layer thicker than the underlying conductor layer, Even if an impact is received, it is possible to prevent problems such as an increase in electrical resistance due to disconnection or chipping.
また、下地導体層は、これを構成する金属の粒径が０．２μｍ以下（より好ましくは０．１μｍ以下）となるように成膜することが好ましい。このように粒径の細かい緻密な膜によって下地導体層を形成すれば、その上に主導体層をめっき成長させるときに下地導体層との間に界面の無い又は少ない（下地導体層と主導体層との間の少なくとも一部に界面が存在しない）接合強度に優れた電極を形成することが出来る。 The underlying conductor layer is preferably formed so that the particle diameter of the metal constituting the underlying conductor layer is 0.2 μm or less (more preferably 0.1 μm or less). If the underlying conductor layer is formed of a dense film having a fine particle size in this way, there is little or no interface between the underlying conductor layer and the underlying conductor layer when the main conductor layer is grown by plating (the underlying conductor layer and the main conductor). It is possible to form an electrode having an excellent bonding strength (there is no interface between at least part of the layers).
さらに、本発明の端子電極では、上記主導体層および下地導体層に加え、下地接合層、並びに主電極層を覆う電極表面層（外部接合層およびバリア層）を設けることが好ましい。これらにつき以下説明する。 Furthermore, in the terminal electrode of the present invention, in addition to the main conductor layer and the base conductor layer, it is preferable to provide a base bonding layer and an electrode surface layer (external bonding layer and barrier layer) covering the main electrode layer. These will be described below.
下地接合層は、ベース基板と上記下地導体層との間に介在されるように上記下地電極層に含めるもので、これにより当該端子電極のベース基板への密着性を向上させる。この下地接合層は、例えば気相成膜法により形成したクロム（Ｃｒ）を主成分とする薄膜により構成することができ、特に上記下地導体層としてＣｕを使用する場合には、ベース基板との接合性と共に当該下地導体層との間の良好な接合性も得ることが出来る。尚、この下地接合層は、クロム以外にも、チタン（Ｔｉ）、ニッケル（Ｎｉ）、ニッケル‐クロム（Ｎｉ‐Ｃｒ）、タングステン（Ｗ）、銅（Ｃｕ）、および銀（Ａｇ）のうちのいずれかを主成分とする薄膜としても良い。 The base bonding layer is included in the base electrode layer so as to be interposed between the base substrate and the base conductor layer, thereby improving the adhesion of the terminal electrode to the base substrate. This base bonding layer can be composed of, for example, a thin film mainly composed of chromium (Cr) formed by a vapor deposition method. In particular, when Cu is used as the base conductor layer, In addition to the bondability, good bondability with the underlying conductor layer can also be obtained. In addition to the chromium, the base bonding layer is made of titanium (Ti), nickel (Ni), nickel-chromium (Ni-Cr), tungsten (W), copper (Cu), and silver (Ag). It is good also as a thin film which has either.
一方、電極表面層は、端子電極の最上層に配置されて外部導体との接合性を高める外部接合層を含み、さらにこの外部接合層と前記主導体層との間に介在させるバリア層を含むことが望ましい。 On the other hand, the electrode surface layer includes an external bonding layer that is disposed on the uppermost layer of the terminal electrode and enhances the bondability with the external conductor, and further includes a barrier layer interposed between the external bonding layer and the main conductor layer. It is desirable.
ここで、「外部導体」とは、当該端子電極を他の電極等に電気的に接続するとき（或いは当該端子電極を備えた電子部品を実装するとき）に当該端子電極と他の電極等との間に介在される導電体であり、例えば、はんだバンプやＡｕバンプ、ボンディングワイヤ等が含まれる。外部接合層は、これら外部導体との接合性を高める材料からなる。一例を述べれば、例えばはんだ実装用の端子電極を構成する場合には、はんだ濡れ性を高めるはんだ接合層（例えばＳｎ膜）とし、例えばＡｕバンプ実装用の端子電極を構成する場合には、Ａｕバンプとの接合性を高めるＡｕ膜とする。 Here, the “external conductor” refers to the terminal electrode and the other electrode when the terminal electrode is electrically connected to another electrode or the like (or when an electronic component having the terminal electrode is mounted). For example, solder bumps, Au bumps, bonding wires, and the like are included. The external bonding layer is made of a material that enhances the bondability with these external conductors. For example, when a terminal electrode for solder mounting is configured, for example, a solder joint layer (for example, Sn film) that improves solder wettability is used. For example, when a terminal electrode for Au bump mounting is configured, Au An Au film that enhances the bondability with the bump is used.
また、上記バリア層は、当該端子電極を使用して電子部品を実装するときに、接合金属（例えばはんだやＡｕ等）と主導体層間における材料の拡散を防ぐもので、これら外部接合層とバリア層とを設けることにより、端子電極の接合性（例えばはんだ付け性やＡｕバンプ接合性）を向上させて確実な接続を行うと共に、電極構成層間の合金化や材料拡散を防ぐことが出来る。 The barrier layer prevents diffusion of the material between the bonding metal (for example, solder or Au) and the main conductor layer when the electronic component is mounted using the terminal electrode. By providing the layer, it is possible to improve the bondability (for example, solderability and Au bump bondability) of the terminal electrode and perform reliable connection, and to prevent alloying and material diffusion between the electrode constituent layers.
本発明の端子電極は、典型的には、当該端子電極が備えられる電子部品と外部（例えば配線基板等）との接続を行う外部接続端子であるが、必ずしもこれに限定されるものではなく、例えばＩＣや他の電子部品、電子モジュール、電子素子を実装するためにベース基板上に設けられる接続パッド（例えばフリップチップボンディング用パッド、ワイヤーボンディング用パッド等）その他の電極であっても良く、バンプやポストと言った接続電極でも良い。また、ベース基板に設ける位置についても特に問わず、ベース基板の表（おもて）面に設けられる表面端子、裏面に設けられる裏面端子、側面に設けられる側面端子（端面端子）、又はこれらの組み合わせのいずれであっても構わない。 The terminal electrode of the present invention is typically an external connection terminal that connects an electronic component provided with the terminal electrode and the outside (for example, a wiring board), but is not necessarily limited thereto. For example, it may be a connection pad (for example, a flip chip bonding pad, a wire bonding pad, etc.) or other electrode provided on the base substrate for mounting an IC, other electronic components, an electronic module, or an electronic element. Connection electrodes such as or post may be used. Moreover, it does not ask | require especially about the position provided in a base board, The surface terminal provided in the front (front) surface of a base board, the back terminal provided in a back surface, the side terminal provided in a side surface (end surface terminal), or these Any combination may be used.
一方、本発明に係る電子部品は、上記本発明に係る端子電極を備えるもので、ベース基板と、当該ベース基板に実装された１つ以上の電気的機能素子と、当該ベース基板に備えられた上記本発明に係るいずれかの端子電極を１つ以上備える。 On the other hand, an electronic component according to the present invention includes the terminal electrode according to the present invention, and includes a base substrate, one or more electrical functional elements mounted on the base substrate, and the base substrate. One or more terminal electrodes according to the present invention are provided.
上記「電子部品」には、個別部品（ディスクリート部品）またはチップ部品（例えばチップコンデンサ、チップインダクタ、チップ抵抗器、チップサーミスタ、チップバリスタ等）と、複数の電気素子（能動素子や受動素子）を組み合わせた電子デバイス（例えばフィルタやデュプレクサ、パワーアンプモジュール、高周波重畳モジュールその他の各種デバイス）との双方が含まれる。また、上記「電気的機能素子」は、トランジスタやＦＥＴ等のような能動素子と、コンデンサやインダクタ、抵抗等の受動素子の双方を含むものである。 The “electronic components” include individual components (discrete components) or chip components (for example, chip capacitors, chip inductors, chip resistors, chip thermistors, chip varistors, etc.) and a plurality of electric elements (active elements and passive elements). Both combined electronic devices (for example, filters, duplexers, power amplifier modules, high-frequency superposition modules, and other various devices) are included. The “electrical functional element” includes both active elements such as transistors and FETs and passive elements such as capacitors, inductors, and resistors.
さらに、本発明の各層について「上に（形成する）」或いは「覆う」とは、ベース基板から見て上層（外側）に位置することを意味するものであり、対象とする層同士が必ずしも接している必要はなく、対象とする層と層との間に何らかの層が介在された配置状態をも含む概念である。 Furthermore, “on (form)” or “cover” for each layer of the present invention means that it is located on the upper layer (outside) when viewed from the base substrate, and the target layers are not necessarily in contact with each other. It is a concept including an arrangement state in which a certain layer is interposed between the target layers.
本発明によれば、端子電極の寸法精度および接合強度を高め、信頼性を向上させることが出来る。 According to the present invention, the dimensional accuracy and bonding strength of the terminal electrode can be increased and the reliability can be improved.
本発明の他の目的、特徴および利点は、以下の本発明の実施の形態の説明により明らかにする。尚、本発明は下記の実施形態に限定されるものではなく、特許請求の範囲に記載の範囲内で種々の変更を行うことができることは当業者に明らかである。 Other objects, features and advantages of the present invention will become apparent from the following description of embodiments of the present invention. It should be noted that the present invention is not limited to the following embodiments, and it will be apparent to those skilled in the art that various modifications can be made within the scope of the claims.
〔全体構成〕
図１は、本発明の一実施形態に係る端子電極を示す断面図である。同図に示すようにこの端子電極１１は、電子部品１を配線基板（図示せず）に実装し電気的な接続を行うために当該電子部品１に備える外部接続端子であり、配線基板の接続パッドに対して例えばバンプを介して電気的・機械的に接続を可能とするためベース基板２の下面に配置される裏面電極と、この裏面電極と、ベース基板２の上面に設けられた各種の電気的な機能構成部から引き出された接続用の導体３（上部導体３ａおよび下部導体３ｂ）とを電気的に接続するためにベース基板２の側面に形成される側面電極とを含み、図示の例ではベース基板２の側面から底面に亘って連続しかつ後に述べる各層を備えた多層膜として形成している。
〔overall structure〕
FIG. 1 is a cross-sectional view showing a terminal electrode according to an embodiment of the present invention. As shown in the figure, the terminal electrode 11 is an external connection terminal provided in the electronic component 1 for mounting the electronic component 1 on a wiring board (not shown) and making an electrical connection. For example, a back electrode disposed on the lower surface of the base substrate 2 to enable electrical and mechanical connection to the pad via a bump, for example, the back electrode, and various types of electrodes provided on the upper surface of the base substrate 2 A side electrode formed on the side surface of the base substrate 2 for electrically connecting the connecting conductors 3 (upper conductor 3a and lower conductor 3b) drawn from the electrical functional component, In the example, the base substrate 2 is formed as a multilayer film that is continuous from the side surface to the bottom surface and includes each layer described later.
すなわち、端子電極１１は、ベース基板２の表面に形成した下地電極層２１と、この下地電極層２１の表面に形成した主電極層２２と、主電極層２２の表面を覆う電極表面層２３とからなる。ベース基板２は、この例ではアルミナ基板とし、構成するデバイスに対応してその上面に酸化アルミニウム（Ａｌ2Ｏ3）からなる平坦化膜４や誘電体膜５、絶縁膜６、保護膜７等の各種の機能膜を設け、種々の電気的な機能素子を形成しあるいはＩＣやチップ状の電子素子を実装する。 That is, the terminal electrode 11 includes a base electrode layer 21 formed on the surface of the base substrate 2, a main electrode layer 22 formed on the surface of the base electrode layer 21, and an electrode surface layer 23 covering the surface of the main electrode layer 22. Consists of. The base substrate 2 is an alumina substrate in this example, and a flattening film 4 made of aluminum oxide (Al 2 O 3 ), a dielectric film 5, an insulating film 6, a protective film 7, etc. are formed on the upper surface corresponding to the device to be configured. These various functional films are provided, various electric functional elements are formed, or an IC or chip-shaped electronic element is mounted.
〔下地電極層〕
下地電極層２１は、下地接合層１２とその表面に形成した下地導体層１３とからなる。下地接合層１２は、ベース基板であるアルミナ基板２と強固な接合を得るため、スパッタにより形成したクロム（Ｃｒ）からなる薄膜であり、その表面に形成する下地導体層１３は、同じくスパッタにより形成した銅（Ｃｕ）からなる薄膜である。ベース基板２上にＣｒ膜をスパッタ成膜することにより、Ｃｒ粒子がベース基板の内部に入り込んだ（打ち込まれた）強固な接合が得られる。また、このＣｒ膜の表面に成膜するＣｕ膜はＣｒとの密着性が良く、さらに次にＣｕめっきにより形成する主導体層１４（後述する）との接合性も高いから、ベース基板２に主導体層１４を強固に固定することが出来る。
[Base electrode layer]
The base electrode layer 21 includes a base bonding layer 12 and a base conductor layer 13 formed on the surface thereof. The ground bonding layer 12 is a thin film made of chromium (Cr) formed by sputtering in order to obtain a strong bond with the alumina substrate 2 as a base substrate, and the ground conductor layer 13 formed on the surface thereof is also formed by sputtering. A thin film made of copper (Cu). By forming a Cr film on the base substrate 2 by sputtering, a strong bond in which Cr particles have entered (implanted) the base substrate can be obtained. Further, since the Cu film formed on the surface of the Cr film has good adhesion to Cr, and further has high bondability with a main conductor layer 14 (described later) formed by Cu plating, The main conductor layer 14 can be firmly fixed.
尚、下地電極層２１として、下地導体層１３（Ｃｕ膜）を設けずに下地接合層（Ｃｒ膜）のみを設けてこれを通電層としてＣｒ膜の上に後述の主導体層１４を形成することも考えられるが、このようにすると、Ｃｒ膜の厚さが薄く抵抗値が高いために供給される電流量が少なく、Ｃｕめっき（主導体層）の成長が遅い上に、不均一な膜厚分布となってしまう難がある。これに対して、本実施形態のように下地導体層１３（スパッタＣｕ膜）を設ければ、これが主導体層１３をめっき成長させるときの良好な下地給電膜となって、Ｃｕめっきの膜成長を安定化することができ、電極の膜厚分布を均一にすることが可能となる。 In addition, as the base electrode layer 21, the base conductor layer 13 (Cu film) is not provided, but only the base bonding layer (Cr film) is provided, and this is used as a current-carrying layer to form a main conductor layer 14 described later on the Cr film. In this case, since the Cr film is thin and the resistance value is high, the amount of current supplied is small, the growth of the Cu plating (main conductor layer) is slow, and the film is not uniform. There is a difficulty in having a thickness distribution. On the other hand, if the base conductor layer 13 (sputtered Cu film) is provided as in the present embodiment, this becomes a good base power supply film when the main conductor layer 13 is grown by plating, and Cu plating film growth Can be stabilized, and the film thickness distribution of the electrodes can be made uniform.
尚、接続用導体３と主導体層１４との間にはＣｕに比べ電気抵抗が大きいＣｒ層（下地接合層）１２が介在されることとなるが、このＣｒ層１２をスパッタにより形成した十分に薄い膜（後に述べるように例えば０．２μｍ程度）とすることにより、信号損失の問題を回避することができ、同時にベース基板２との強固な接合を実現することが出来る。 A Cr layer (underlying junction layer) 12 having a larger electric resistance than Cu is interposed between the connecting conductor 3 and the main conductor layer 14, but this Cr layer 12 is sufficiently formed by sputtering. By using a very thin film (for example, about 0.2 μm as will be described later), the problem of signal loss can be avoided, and at the same time, strong bonding with the base substrate 2 can be realized.
また、下地接合層１２と下地導体層１３とを形成する材料は、この例のほかにもそれぞれ、例えばＴｉとＣｕ、 Ｎｉ‐ＣｒとＣｕ、ＣｒとＡｇ、ＴｉとＡｇ、Ｎｉ‐ＣｒとＡｇ等としても良い。また、本実施形態では下地接合層１２と下地導体層１３をいずれもスパッタにより形成したが、他の気相成膜法（例えば蒸着法やＣＶＤ法等）によっても良く、さらに無電解めっきにより形成することも可能である。 In addition to this example, materials for forming the base bonding layer 12 and the base conductor layer 13 are, for example, Ti and Cu, Ni—Cr and Cu, Cr and Ag, Ti and Ag, Ni—Cr and Ag, respectively. And so on. In the present embodiment, both the base bonding layer 12 and the base conductor layer 13 are formed by sputtering, but other vapor deposition methods (for example, vapor deposition method, CVD method, etc.) may be used, and further, electroless plating may be used. It is also possible to do.
〔主電極層〕
主電極層２２は、Ｃｕめっき膜である主導体層１４からなる。すなわち、主導体層１４は、前記下地導体層１３を通電層として電解めっき（例えばバレルめっき）を行い、下地導体層１３の表面にＣｕを析出させ、めっき成長させることにより成膜する。これにより、Ｃｕ同士の金属間接合によって下地電極層に強固に接合された電極本体（主電極層）を形成することが出来る。また、かかる主電極層の下地となる前記下地導体層のＣｕの粒径はスパッタ成膜によるから非常に小さく緻密であり、このＣｕ粒を核としてＣｕ膜が良好にめっき成長するから、界面の無い（又は部分的にしか存在しない）十分に厚さのある電気抵抗の低い機械強度優れた電極膜を形成することが出来る。尚、主導体層の成膜は、本実施形態では、製造コストおよび生産性の点で有利な電解めっきを用いるが、無電解めっきによることも可能である。
[Main electrode layer]
The main electrode layer 22 is composed of the main conductor layer 14 which is a Cu plating film. That is, the main conductor layer 14 is formed by performing electrolytic plating (for example, barrel plating) using the base conductor layer 13 as an energization layer, depositing Cu on the surface of the base conductor layer 13, and growing the plating. Thereby, the electrode main body (main electrode layer) firmly joined to the base electrode layer by intermetallic joining of Cu can be formed. In addition, the Cu particle size of the underlying conductor layer, which is the base of the main electrode layer, is very small and dense because of sputter film formation, and the Cu film grows well with this Cu particle as a nucleus. It is possible to form an electrode film having a sufficient thickness and a low electrical resistance and excellent mechanical strength that is absent (or only partially present). In this embodiment, the main conductor layer is formed by electrolytic plating, which is advantageous in terms of manufacturing cost and productivity. However, electroless plating can also be used.
〔電極表面層〕
電極表面層２３は、はんだ接合層（外部接合層）１６とバリア層１５とからなる。はんだ接合層１６は、錫（Ｓｎ）めっき膜とし、バリア層１５の表面に電解めっき（例えばバレルめっき）を施すことにより成膜する。はんだ接合層１６を設けることにより、端子電極１１のはんだ濡れ性を向上させ、リフロー実装時のはんだ付け性を良好にすることが出来る。
(Electrode surface layer)
The electrode surface layer 23 includes a solder bonding layer (external bonding layer) 16 and a barrier layer 15. The solder bonding layer 16 is a tin (Sn) plating film, and is formed by performing electrolytic plating (for example, barrel plating) on the surface of the barrier layer 15. By providing the solder bonding layer 16, the solder wettability of the terminal electrode 11 can be improved, and the solderability during reflow mounting can be improved.
一方、バリア層１５はニッケル（Ｎｉ）めっき膜であり、前記主導体層（Ｃｕめっき膜）１４の表面に電解めっき（例えばバレルめっき）を施すことにより成膜する。バリア層１５を設けることにより、下層の主導体層（Ｃｕ膜）１４と上記はんだ接合層（Ｓｎ膜）との間で互いの材料が拡散したり合金化することを防ぐことが出来る。 On the other hand, the barrier layer 15 is a nickel (Ni) plating film, and is formed by performing electrolytic plating (for example, barrel plating) on the surface of the main conductor layer (Cu plating film) 14. By providing the barrier layer 15, it is possible to prevent the mutual material from diffusing or alloying between the lower main conductor layer (Cu film) 14 and the solder joint layer (Sn film).
尚、上記外部接合層１６は、当該端子電極の実装時に使用する接合材料に対応した様々な他の材料、例えば金（Ａｕ）や銀（Ａｇ）、Ｓｎ‐Ａｇ、Ｓｎ‐Ａｇ‐Ｃｕ、或いは亜鉛（Ｚｎ）を含有する導体その他からなるものであって良い。 The external bonding layer 16 is made of various other materials corresponding to the bonding material used when mounting the terminal electrode, such as gold (Au), silver (Ag), Sn-Ag, Sn-Ag-Cu, or It may be made of a conductor containing zinc (Zn) or the like.
また、上記バリア層１５およびはんだ接合層１６は、無電解めっきによって形成することも可能である。さらに電極表面層２３（バリア層１５／はんだ接合層１６）の材料については、上記以外にも様々な材料・成膜方法を使用した膜とすることが出来る。例えば、バリア層／外部接合層の組み合わせとして、Ｎｉ電解めっき膜／Ｓｎ又はＡｕ電解めっき膜、Ｎｉ無電解めっき膜／Ｓｎ又はＡｕ無電解めっき膜、Ｎｉ無電解めっき膜／Ｐｄ無電解めっき膜およびＳｎ又はＡｕ無電解めっき膜、Ｎｉ無電解めっき膜／Ｓｎ又はＡｕ無電解めっき膜、Ｎｉ無電解めっき膜／Ｐｄ無電解めっき膜およびＳｎ又はＡｕ無電解めっき膜等としても良い。 The barrier layer 15 and the solder bonding layer 16 can also be formed by electroless plating. Further, the material of the electrode surface layer 23 (barrier layer 15 / solder bonding layer 16) may be a film using various materials and film forming methods other than those described above. For example, as a combination of barrier layer / external bonding layer, Ni electroplating film / Sn or Au electroplating film, Ni electroless plating film / Sn or Au electroless plating film, Ni electroless plating film / Pd electroless plating film and Sn or Au electroless plating film, Ni electroless plating film / Sn or Au electroless plating film, Ni electroless plating film / Pd electroless plating film and Sn or Au electroless plating film may be used.
端子電極の各層の厚さは、下地接合層（Ｃｒスパッタ膜）を０．０１から１μｍ（より好ましくは０．１から０．５μｍ／例えば約０．２μｍ）、下地導体層（Ｃｕスパッタ膜）を０．０１から１０μｍ（より好ましくは０．１から１μｍ／例えば約０．５μｍ）、主導体層（Ｃｕ電気めっき膜）を０．１から２０μｍ（より好ましくは０．５から１０μｍ／例えば約２．０μｍ）、バリア層（Ｎｉめっき膜）を０．１から３０μｍ（より好ましくは０．５から５μｍ／例えば約１．５μｍ）、外部接合層（Ｓｎめっき膜）を０．５から３０μｍ（より好ましくは１から１０μｍ／例えば約５．０μｍ）とすることが望ましい。 The thickness of each layer of the terminal electrode is 0.01 to 1 μm (more preferably 0.1 to 0.5 μm / for example, about 0.2 μm) for the base bonding layer (Cr sputtered film), and the base conductor layer (Cu sputtered film). 0.01 to 10 μm (more preferably 0.1 to 1 μm / for example about 0.5 μm), and the main conductor layer (Cu electroplated film) 0.1 to 20 μm (more preferably 0.5 to 10 μm / for example about 2.0 μm), the barrier layer (Ni plating film) is 0.1 to 30 μm (more preferably 0.5 to 5 μm / for example about 1.5 μm), and the external bonding layer (Sn plating film) is 0.5 to 30 μm ( More preferably, the thickness is 1 to 10 μm / for example, about 5.0 μm.
また、下地導体層（Ｃｕスパッタ膜）を構成するＣｕの平均粒径は、０．００５から０．５μｍ（より好ましくは０．０５から０．３μｍ）とし、その上に形成する主導体層（Ｃｕめっき膜）のＣｕの平均粒径は、０．０１から３μｍ（より好ましくは０．１から１μｍ）とすることが好ましい。 The average particle diameter of Cu constituting the underlying conductor layer (Cu sputtered film) is 0.005 to 0.5 μm (more preferably 0.05 to 0.3 μm), and the main conductor layer ( The average particle diameter of Cu in the (Cu plating film) is preferably 0.01 to 3 μm (more preferably 0.1 to 1 μm).
図２から図５は、本実施形態に係る端子電極をＴＥＭ（透過型電子顕微鏡）により観察した写真画像を示すものであり、図２および図３においてＸ‐Ｘ線は下地導体層（スパッタＣｕ膜）１３と主導体層（めっきＣｕ膜）１４との境界を、図４において符号８は下地導体層（スパッタＣｕ膜）１３と主導体層（めっきＣｕ膜）１４間の界面を、また図５において符号９はボイドをそれぞれ示している。 2 to 5 show photographic images obtained by observing the terminal electrode according to the present embodiment with a TEM (transmission electron microscope). In FIGS. 2 and 3, the XX line indicates the underlying conductor layer (sputtered Cu layer). 4 is a boundary between the base conductor layer (sputtered Cu film) 13 and the main conductor layer (plated Cu film) 14. In FIG. 5, reference numeral 9 denotes a void.
これらの画像から明らかなように、端子電極の本体部分となるめっきＣｕ膜（主導体層）１４は、一部に界面８が見られ（図４参照）、また下地導体層１３と主導体層１４との境界部（当該境界近傍の主導体層１４）の金属粒と金属粒との間や金属粒の内部にボイドが観察されるところがあるものの（図５参照）、スパッタＣｕ膜（下地導体層）１３からスパッタＣｕ粒を核にして粒成長した界面のほとんど無い（所々一部にのみある）連続的な膜となっており、下地導体層１３と主導体層１４との間に強固な接合が得られている。 As is clear from these images, the plating Cu film (main conductor layer) 14 which is the main body portion of the terminal electrode has a part of the interface 8 (see FIG. 4), and the underlying conductor layer 13 and the main conductor layer. 14 (see FIG. 5), although there are places where voids are observed between and inside the metal grains of the boundary part (the main conductor layer 14 in the vicinity of the boundary) (see FIG. 5). Layer) 13 is a continuous film having almost no interface (partially only in some parts) grown from sputtered Cu grains as a nucleus, and is strong between the underlying conductor layer 13 and the main conductor layer 14. Bonding is obtained.
さらに、図６（ａ）は、本実施形態の端子電極を透過型電子顕微鏡（ＴＥＭ）により観察した別の写真画像を示すものであり、同図（ｂ）は（ａ）の画像においてＣｕ粒の外形線を書き加えたものである。また、図７は下地導体層（スパッタＣｕ膜）と主導体層（Ｃｕ電気めっき膜）との境界部の金属粒の成長状態を模式的に示す概念図である。またこれらの図において、符号８は界面を、９はボイドをそれぞれ示す。また、１２、１３および１４はそれぞれ下地接合層（スパッタＣｒ膜）、下地導体層（スパッタＣｕ膜）および主導体層（Ｃｕめっき膜）を示し、１３ａは下地導体層１３を形成するスパッタＣｕ粒を、１４ａと１４ｂは主導体層１４を形成するバレルめっきによるＣｕ粒をそれぞれ示している。 Further, FIG. 6A shows another photographic image obtained by observing the terminal electrode of the present embodiment with a transmission electron microscope (TEM), and FIG. 6B shows the Cu particles in the image of FIG. The outline is added. FIG. 7 is a conceptual diagram schematically showing the growth state of metal grains at the boundary between the base conductor layer (sputtered Cu film) and the main conductor layer (Cu electroplated film). In these figures, reference numeral 8 denotes an interface, and 9 denotes a void. Reference numerals 12, 13 and 14 denote a base bonding layer (sputtered Cr film), a base conductor layer (sputtered Cu film) and a main conductor layer (Cu plated film), respectively, and 13a denotes sputtered Cu particles forming the base conductor layer 13. 14a and 14b respectively indicate Cu grains formed by barrel plating for forming the main conductor layer 14.
これらの図に示すように本実施形態の端子電極では、下地導体層１３のスパッタＣｕ粒１３ａを核としてＣｕ電解めっきによって縦方向に（下地導体層１３と主導体層１４との境界線に対して交差する（特に略直交する）方向に、又は上層方向に）粒成長した縦長のＣｕ粒１４ａが、下地導体層１３と主導体層１４とに跨るように両層の境界部に存在する。言い換えれば、これら下地導体層１３と主導体層１４との間に多数の楔状の（あるいは支柱状の）金属粒１４ａが両層に打ち込まれるように存在し、それらの周囲を細かいＣｕ粒１３ａ，１４ｂが埋めるように配されている。したがって、たとえ一部に界面８やボイド９が存在しても結果として、高強度の、また膜内でのバルク破壊に対する耐性が大きな導電膜が得られる。 As shown in these figures, in the terminal electrode of the present embodiment, the Cu Cu plating 13a of the base conductor layer 13 is used as a nucleus to perform vertical electroplating (with respect to the boundary line between the base conductor layer 13 and the main conductor layer 14). The vertically elongated Cu grains 14a that have grown in a direction intersecting (particularly substantially orthogonal to each other) or in an upper layer direction are present at the boundary between both layers so as to straddle the underlying conductor layer 13 and the main conductor layer 14. In other words, a large number of wedge-shaped (or pillar-shaped) metal particles 14a exist between the base conductor layer 13 and the main conductor layer 14 so as to be driven into both layers. 14b is arranged to fill. Therefore, even if the interface 8 and the void 9 exist in part, a conductive film having high strength and high resistance to bulk breakdown in the film can be obtained.
本発明ないし本実施形態の端子電極による利点をまとめて述べれば次のとおりである。
（１） 気相成膜法による下地膜（下地電極層）をまず成膜しその上にめっき成長によって主導体層を形成するから、電極を寸法精度良く形成することが出来る。
（２） 電解めっきにより主導体層を厚付けする。したがって、端子の機械的強度（耐衝撃性や耐熱衝撃性）を増すことができ、損傷を受けやすい部品角部の補強も図ることが出来る。また、電気抵抗を小さく信号損失を低減することができ、電子部品の特性向上（例えばフィルタであれば挿入損失の低減、インダクタであればＱ特性の向上、各種デバイスの温度特性の改善等）を図ることが出来る。
（３） スパッタ等で下地電極層を形成した後にその上に主電極層をめっき成長させるから、段差部や突起部等の凹凸部への電極膜の追従性も良く、凹凸部における機械的接合性ならびに電気的接続性を向上させることが出来る。
（４） ベース基板から電極表面層までに順に配される各層間の接合性・密着性が高く、電極全体としてベース基板に対する強固な接合を得ることが出来る。特に、下地導体層とその表面に配する主導体層とを同一の導体材料（例えばＣｕ）で構成することにより良好な接合を実現することが出来る。
（５） 電極表面層（バリア層及びはんだ接合層）を設けることにより、電極各層導体間の合金化・金属拡散を抑えてはんだ耐熱性を高めることが出来ると共に、はんだ付け性を向上させることが出来る。
The advantages of the terminal electrode according to the present invention or the embodiment will be described as follows.
(1) Since a base film (base electrode layer) is first formed by vapor deposition, and the main conductor layer is formed thereon by plating growth, the electrode can be formed with high dimensional accuracy.
(2) Thicken the main conductor layer by electrolytic plating. Therefore, the mechanical strength (impact resistance and thermal shock resistance) of the terminal can be increased, and the corners of parts that are easily damaged can be reinforced. In addition, electrical resistance can be reduced, signal loss can be reduced, and characteristics of electronic components can be improved (for example, reduction of insertion loss for filters, improvement of Q characteristics for inductors, improvement of temperature characteristics of various devices). I can plan.
(3) After the base electrode layer is formed by sputtering or the like, the main electrode layer is grown by plating. Therefore, the electrode film has good followability to uneven portions such as stepped portions and protruding portions, and mechanical bonding at the uneven portions is performed. And electrical connectivity can be improved.
(4) Bondability and adhesion between the layers arranged in order from the base substrate to the electrode surface layer are high, and the entire electrode can be firmly bonded to the base substrate. In particular, good bonding can be realized by configuring the base conductor layer and the main conductor layer disposed on the surface thereof with the same conductor material (for example, Cu).
(5) By providing the electrode surface layer (barrier layer and solder joint layer), it is possible to suppress the alloying / metal diffusion between the electrode conductors of the electrodes and to increase the solder heat resistance, and to improve the solderability. I can do it.
１ 電子部品
２ ベース基板
３ 接続用導体
３ａ 上部導体
３ｂ 下部導体
４ 平坦化膜
５ 誘電体膜
６ 絶縁膜
７ 保護膜
８ 界面
９ ボイド
１１ 端子電極
１２ 下地接合層
１３ 下地導体層
１３ａ スパッタＣｕ粒
１４ 主導体層
１４ａ スパッタＣｕ粒を核として粒成長したバレルめっきＣｕ粒
１４ｂ バレルめっきＣｕ粒
１５ バリア層
１６ 外部接合層（はんだ接合層）
２１ 下地電極層
２２ 主電極層
２３ 電極表面層
DESCRIPTION OF SYMBOLS 1 Electronic component 2 Base substrate 3 Connection conductor 3a Upper conductor 3b Lower conductor 4 Planarizing film 5 Dielectric film 6 Insulating film 7 Protective film 8 Interface 9 Void 11 Terminal electrode 12 Base bonding layer 13 Base conductor layer 13a Sputtered Cu grain 14 Main conductor layer 14a Barrel-plated Cu particles grown with sputtered Cu particles as nuclei 14b Barrel-plated Cu particles 15 Barrier layer 16 External bonding layer (solder bonding layer)
21 Base electrode layer 22 Main electrode layer 23 Electrode surface layer
Claims (2)
前記ベース基板上に形成された下地電極層と、
この下地電極層の上に形成された主電極層と、
を備え、
前記主電極層は、めっき金属からなる主導体層を含み、
前記下地電極層は、当該主導体層をめっき成長させるときの通電層となる下地導体層を含み、
前記主導体層は、前記下地導体層より厚さ寸法が大きく、
前記下地電極層は、前記ベース基板と前記下地導体層との間に介在されて当該端子電極の前記ベース基板への密着性を高める下地接合層をさらに含み、
前記下地接合層は、気相成膜法により形成されかつクロム、チタン、ニッケル、ニッケル‐クロム、タングステン、銅、および銀のうちのいずれかを主成分とする薄膜からなり、
前記主電極層を覆う電極表面層をさらに備え、
当該電極表面層は、当該端子電極の最上層に配置されて外部導体との接合性を高める外部接合層を有し、
前記電極表面層は、前記主導体層と前記外部接合層との間に介在されて前記主導体層および前記外部接合層間における材料の拡散を阻止するバリア層をさらに有し、
前記下地導体層は、気相成膜法により形成された薄膜からなり、かつ平均粒径が０．２μｍ以下であり、
前記主導体層は、液相成膜法により形成されためっき膜からなり、
前記下地導体層および前記主導体層は、共に、銅を主成分とする膜により形成されかつこれら導体層の境界を跨ぐように粒成長した金属粒を含み、
前記下地導体層と前記主導体層との間の少なくとも一部に界面が存在せずかつボイドが存在する
ことを特徴とする端子電極。 A terminal electrode comprising a conductive material and provided on the base substrate for electrical connection,
A base electrode layer formed on the base substrate;
A main electrode layer formed on the base electrode layer;
With
The main electrode layer includes a main conductor layer made of a plated metal,
The base electrode layer includes a base conductor layer that serves as an energization layer when the main conductor layer is grown by plating.
The main conductor layer has a thickness dimension larger than that of the base conductor layer,
The base electrode layer further includes a base bonding layer that is interposed between the base substrate and the base conductor layer to improve adhesion of the terminal electrode to the base substrate,
The base bonding layer is formed of a thin film mainly formed of any one of chromium, titanium, nickel, nickel-chromium, tungsten, copper, and silver, formed by a vapor deposition method.
An electrode surface layer covering the main electrode layer;
The electrode surface layer has an external bonding layer that is disposed on the uppermost layer of the terminal electrode and enhances the bonding property with an external conductor,
The electrode surface layer further includes a barrier layer interposed between the main conductor layer and the outer bonding layer to prevent diffusion of material between the main conductor layer and the outer bonding layer,
The base conductor layer is made of a thin film formed by a vapor deposition method and has an average particle size of 0.2 μm or less.
The main conductor layer is composed of a plating film formed by a liquid phase film formation method,
Both the base conductor layer and the main conductor layer include metal grains formed by a film containing copper as a main component and grain-grown so as to straddle the boundary of these conductor layers,
A terminal electrode, wherein an interface does not exist and a void exists in at least a part between the base conductor layer and the main conductor layer.
当該ベース基板に実装された１つ以上の電気的機能素子と、
当該ベース基板に備えられた前記請求項１に記載の１つ以上の端子電極と、
を備えた電子部品。 A base substrate;
One or more electrical functional elements mounted on the base substrate;
One or more terminal electrode according to the claim 1 provided on the base substrate,
With electronic components.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006234798A JP4748317B2 (en) | 2006-08-31 | 2006-08-31 | Terminal electrodes and electronic components |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006234798A JP4748317B2 (en) | 2006-08-31 | 2006-08-31 | Terminal electrodes and electronic components |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2008060287A JP2008060287A (en) | 2008-03-13 |
| JP4748317B2 true JP4748317B2 (en) | 2011-08-17 |
Family
ID=39242690
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2006234798A Expired - Fee Related JP4748317B2 (en) | 2006-08-31 | 2006-08-31 | Terminal electrodes and electronic components |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4748317B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20190007631A (en) | 2017-07-13 | 2019-01-23 | 삼성전기주식회사 | Multilayer ceramic capacitor |
| KR20190024084A (en) | 2017-08-31 | 2019-03-08 | 삼성전기주식회사 | Capacitor component |
| KR20190024083A (en) | 2017-08-31 | 2019-03-08 | 삼성전기주식회사 | Multilayer ceramic capacitor and method of manufacturing the same |
| KR20190027452A (en) | 2017-09-07 | 2019-03-15 | 삼성전기주식회사 | Multilayer ceramic capacitor and method of manufacturing the same |
| KR20200025049A (en) | 2018-08-29 | 2020-03-10 | 삼성전기주식회사 | Capacitor component |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5476926B2 (en) * | 2009-10-29 | 2014-04-23 | 富士通株式会社 | Manufacturing method of semiconductor device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2678393B2 (en) * | 1990-03-31 | 1997-11-17 | ティーディーケイ株式会社 | Chip capacitor manufacturing method |
| JP3459372B2 (en) * | 1999-03-18 | 2003-10-20 | 株式会社神戸製鋼所 | Method of forming wiring film |
| JP2002252101A (en) * | 2001-02-22 | 2002-09-06 | Matsushita Electric Ind Co Ltd | Electronic component |
| US7884698B2 (en) * | 2003-05-08 | 2011-02-08 | Panasonic Corporation | Electronic component, and method for manufacturing the same |
-
2006
- 2006-08-31 JP JP2006234798A patent/JP4748317B2/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20190007631A (en) | 2017-07-13 | 2019-01-23 | 삼성전기주식회사 | Multilayer ceramic capacitor |
| KR20190024084A (en) | 2017-08-31 | 2019-03-08 | 삼성전기주식회사 | Capacitor component |
| KR20190024083A (en) | 2017-08-31 | 2019-03-08 | 삼성전기주식회사 | Multilayer ceramic capacitor and method of manufacturing the same |
| US10573462B2 (en) | 2017-08-31 | 2020-02-25 | Samsung Electro-Mechanics Co., Ltd. | Capacitor component |
| US10763041B2 (en) | 2017-08-31 | 2020-09-01 | Samsung Electro-Mechanics Co., Ltd. | Multilayer ceramic capacitor and method of manufacturing the same |
| KR20190027452A (en) | 2017-09-07 | 2019-03-15 | 삼성전기주식회사 | Multilayer ceramic capacitor and method of manufacturing the same |
| US10580579B2 (en) | 2017-09-07 | 2020-03-03 | Samsung Electro-Mechanics Co., Ltd. | Multilayer ceramic capacitor and method of manufacturing the same |
| KR20200025049A (en) | 2018-08-29 | 2020-03-10 | 삼성전기주식회사 | Capacitor component |
| US11031184B2 (en) | 2018-08-29 | 2021-06-08 | Samsung Electro-Mechanics Co., Ltd. | Capacitor component including external electrode having extended pattern and connection pattern extending from extended pattern |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2008060287A (en) | 2008-03-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7135770B2 (en) | Semiconductor element with conductive columnar projection and a semiconductor device with conductive columnar projection | |
| CN100495694C (en) | Semiconductor device | |
| US8130485B2 (en) | Ceramic electronic component and method for manufacturing the same | |
| WO2008062602A1 (en) | Laminated electronic component and method for manufacturing the same | |
| JP4748317B2 (en) | Terminal electrodes and electronic components | |
| JP2012099779A (en) | Power module using burning join and manufacturing method of the power module | |
| TWI536521B (en) | Installation structure and manufacturing method thereof | |
| JP5293185B2 (en) | Manufacturing method of electronic parts | |
| TW201104817A (en) | Semiconductor device and manufacturing method of the same | |
| TW201225209A (en) | Semiconductor device and method of confining conductive bump material with solder mask patch | |
| JP5848139B2 (en) | Wiring board, wiring board with solder bump, and semiconductor device | |
| JP5494559B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP6154110B2 (en) | Mounting board | |
| JP2006210369A (en) | Semiconductor apparatus and manufacturing method thereof | |
| JP2014078627A (en) | Wiring board, wiring board with solder bumps and semiconductor device | |
| JP4508558B2 (en) | Electronic component and its manufacturing method | |
| JP3658156B2 (en) | Mounted body and manufacturing method thereof | |
| JP4775369B2 (en) | Semiconductor chip, semiconductor device, and manufacturing method | |
| JP3808357B2 (en) | Wiring board | |
| JP2010278193A (en) | Electronic component, electronic component device using the same and method of manufacturing them | |
| JP3808358B2 (en) | Wiring board | |
| JP3854177B2 (en) | Wiring board for mounting semiconductor element and method for manufacturing the same | |
| JPH0810197Y2 (en) | Package for storing semiconductor devices | |
| JP3881542B2 (en) | Wiring board | |
| JP3370540B2 (en) | Wiring board |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100414 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100527 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20101117 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110214 |
|
| A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20110221 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20110420 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20110503 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 4748317 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140527 Year of fee payment: 3 |
|
| LAPS | Cancellation because of no payment of annual fees |