JP2678393B2 - Chip capacitor manufacturing method - Google Patents

Description

TECHNICAL FIELD The present invention relates to a method of manufacturing a leadless chip capacitor suitable for mounting as a chip-shaped electronic component on a printed circuit board.

(Prior Art) A conventional chip capacitor is obtained by stacking and pressing unfired dielectric sheets, cutting them into chip shapes, firing them, and printing and baking Ag-Pd material on each fired chip. This is a manufacturing method in which end electrodes are formed and electroplating is performed thereon.

A method of forming an end electrode by this kind of thick film technique and electroplating is proposed in Japanese Patent Laid-Open No. 62-274614 proposed by the present applicant.

Figure 10 shows the external shape of a chip capacitor manufactured by the conventional method. In this case, the end electrode 15A is formed so as to surround the end of the chip-shaped dielectric plate 16A having the internal capacitance electrode.

(Problems to be solved by the invention) By the way, when an end electrode such as a conventional one is made of a thick film of Ag-Pd material, it is difficult to manage the thickness, and there is a tendency that variation in external dimensions easily occurs. There is also a drawback that the material cost is high. Also, in terms of the manufacturing method, since the unfired ceramic dielectric sheet is cut into chips and then fired, the step of forming the end electrodes may be troublesome. Furthermore, since the appearance selection after electroplating on the thick film electrode made of Ag-Pd material is in a state where it is separated into individual chips, it is inevitable to rely on human hands and it is not possible to automate the appearance selection. There were also problems that were not suitable.

In view of the above points, the present invention eliminates the variation in product dimensional accuracy by forming the end electrodes by a metal thin film by thin film technology and metal plating formed thereon, and further, formation of the end electrodes and An object of the present invention is to provide a method for manufacturing a chip capacitor that enables efficient appearance selection.

(Means for Solving the Problems) In order to achieve the above object, a method for manufacturing a chip capacitor according to the present invention is such that an unfired ceramic dielectric sheet provided with a required capacitance electrode is laminated, pressure-treated and unfired. Of the monolithic ceramic substrate and forming slit holes in the unfired laminated ceramic substrate to form rod-shaped portions between the parallel slit holes, followed by firing, and the capacitance electrodes are provided on the rod-shaped portions. And a bottom thin film layer having good adhesion to the dielectric substrate so as to surround the end of the rod-shaped portion of the perforated ceramic dielectric substrate in a substantially U-shape, and A metal thin film having a multi-layer structure having at least a low resistance thin film layer provided on the upper side of the lowermost thin film layer is formed by a thin film technique, and a soldering resistant plating layer and a solder bonding uppermost layer. Plating A metal plating film having a multi-layer structure having a layer is formed on the metal thin film to form an end electrode connected to the capacitance electrode, and then the rod-shaped portion is cut into a plurality of pieces.

(Operation) In the present invention, the end electrode is composed of the metal thin film and the metal plating film by the thin film technology such as ion plating, sputtering, P-CVD, etc., and the thickness of the end electrode is controlled with high accuracy. This makes it easy to reduce variations in product shape. Then, the metal thin film has a multi-layer structure having at least a lowermost thin film layer having good adhesion to the ceramic dielectric substrate and a low resistance thin film layer provided on the upper side of the lowermost thin film layer. Since the metal plating film has a multi-layer structure having a solder-resistant plating layer and a solder-adhesive uppermost plating layer, adhesion to a dielectric substrate as an end electrode, conductivity,
Sufficient solder corrosion resistance and solder adhesion can be secured. Also, using a perforated dielectric substrate that integrally has a rod-shaped portion,
In this state of the substrate, a metal thin film is formed by a thin film technique and a metal plated film is formed by electroplating, electroless plating, or the like, so that the manufacturing process for forming the end electrodes can be simplified. Furthermore, even when each rod-shaped part is cut and separated into chips, the appearance is selected by image processing while maintaining the mutual positional relationship, and automation of appearance selection is achieved, and the manufacturing process is made continuous and online. Is possible.

(Example) Hereinafter, an example of a method for manufacturing a chip capacitor according to the present invention will be described with reference to the drawings.

FIG. 1 is a process diagram showing a manufacturing process of a chip capacitor. First, an unfired ceramic dielectric sheet provided with a required internal capacitance electrode pattern by printing a conductor paste or the like is received, laminated in the laminating step 1, and uniformly pressed in the stacking (pressing) step 2 to be unfired. To produce a laminated ceramic dielectric substrate. Then, in the slit forming step 3, as shown in FIG. 2, slit holes 11 are formed in the unfired laminated ceramic dielectric substrate 10 by laser processing or the like to form rod-shaped portions 12 between the parallel slit holes, and thereafter. In firing step 4, the unfired monolithic ceramic dielectric substrate 10 is fired to form a plurality of slit holes 11 as shown in FIG. 3, thereby forming a ceramic dielectric substrate 20 in which a plurality of rod-shaped portions 12 are integrated. To do. At that time, a V to U-shaped groove, which serves as a cutting margin Z when the chips are separated, may be formed in advance in the stacking step 2 or the slit forming step 3 and baked.

FIG. 4 shows a cross section of each rod-shaped portion 12, showing that the internal capacitance electrodes 21 are still facing each other and one end of the internal capacitance electrode 21 is exposed on the end face of the rod-shaped portion 12. There is.

Then, in an end electrode film forming step 5, as shown in FIG. 5, a metal thin film 22 as a base of the end electrode is formed by sputtering in the state of the perforated ceramic dielectric substrate 20,
The metal thin film 22 is formed so as to surround both ends of each rod-shaped portion 12 in a substantially U-shape. Here, the metal thin film 22 is to be connected to the end portion of the internal capacitance electrode 21, and has a two-layer structure, for example, and the bottom layer directly formed on the ceramic dielectric substrate is NiCr, which has good adhesion to the ceramic. The Ti or Cr sputtered film and the upper layer is a low resistance Cu sputtered film.

Further, in the electroplating step 6, electroplating is performed on the metal thin film 22 of each rod-shaped portion 12 with the perforated ceramic dielectric substrate 20 as it is, and the metal plating film 23 is formed as shown in FIG.
The end electrodes 15 are formed by directly depositing on 22. Here, in the metal plating film 23, the lower layer directly formed on the metal thin film 22 is a Ni plating film having solder resistance (solder diffusion prevention and solder heat resistance), and the uppermost layer exposed to the outside is solder adhesion. It is a good Pb-Sn or Sn plating film.

After that, the perforated ceramic dielectric substrate 20 is placed on an adhesive sheet, and in the cutting step 7, each rod-shaped portion is used at the cutting margin Z (see FIGS. 3 and 5) using a dicing saw or the like. 12 is cut and divided into a plurality of chip-shaped dielectrics 16 as shown in FIG. However, the mutual planar positional relationship is not changed by the adhesive tape on the back surface, and in this state, in the next appearance selection step 8, the appearance selection is automatically performed using image processing. Those that are determined to have a poor appearance by image processing are selectively removed. Products that are judged to be good in appearance are products.

FIG. 8 and FIG. 9 show a finished chip capacitor obtained by the above manufacturing method, and a chip-shaped dielectric plate having internal capacitance electrodes 21 facing each other to form a capacitance.
The structure is such that an end electrode 15 composed of a metal thin film 22 by a thin film technique and a metal plating film 23 covering the metal thin film 22 is provided so as to surround the end of 16 in a substantially U-shape. However, as is apparent from the perspective view of FIG. 9, the end electrode 15 has a shape that does not cover the side surface of the chip-shaped dielectric 16. This is an advantage that the variation in product size can be reduced in combination with the fact that the combination of the metal thin film and the metal plating film by the thin film technology is adopted as the end electrode 15.

In the above embodiment, the metal thin film 22 was formed of a two-layer sputtered film, but the bottom layer was a NiCr sputtered film and the intermediate layer was a sputtered film.
It is also possible to have a three-layer structure in which a CuNi sputtered film and an upper layer are Cu sputtered films, and the lower layer of the metal plating film 23 is Ni and the uppermost layer is Pb-Sn.

Further, the metal plating film may be formed by electroless plating instead of electroplating.

Further, the metal thin film may be formed by ion plating, sputtering, P-CVD or the like instead of sputtering.

Further, an external capacitance electrode for forming an electrostatic capacitance may be formed on the surface of the dielectric substrate.

Further, an inductor, a microchip bead, a wide band choke, etc. may be mounted on the chip-shaped dielectric material to form a composite component.

(Effects of the Invention) As described above, according to the present invention, the end electrode is composed of a metal thin film by a thin film technique and a metal plating film deposited thereon, and further, the metal thin film is the dielectric film. A multi-layer structure having at least a lowermost thin film layer having good adhesion to a body plate and a low resistance thin film layer provided on the uppermost side of the lowermost thin film layer, wherein the metal plating film is solder-resistant. Since it has a multi-layer structure with a conductive plating layer and the uppermost plating layer with good solder adhesion, the adhesion to the dielectric plate as the end electrode, conductivity, solder corrosion resistance, and solder adhesion In addition, it is possible to sufficiently secure the product size, reduce the variation in product size, improve the mounting rate, and sufficiently support small chips. Further, it is not necessary to use the Ag-Pd paste for the end electrodes, and the electrode material cost can be reduced. In addition, in manufacturing, a substrate processing method using a perforated dielectric substrate can be adopted, the process can be made continuous, the end electrodes can be formed in the state of the substrate, and the end electrodes can be formed. In addition to simplifying the process, the appearance selection can be automated by performing the appearance selection while maintaining the mutual positional relationship between the chips even after cutting the substrate into the chips.

[Brief description of the drawings]

FIG. 1 is a process diagram showing a manufacturing process of an embodiment of the present invention, and FIG.
FIG. 4 is a perspective view for explaining the slit forming process, FIG. 3 is a plan view showing a perforated ceramic dielectric substrate used in the embodiment, FIG. 4 is a cross-sectional view of a rod-shaped portion of the ceramic dielectric substrate, and FIG. Is a plan view showing an end electrode film forming step, FIG. 6 is a cross-sectional view of the same, FIG. 7 is a plan view illustrating a cutting step, and FIG.
FIG. 9 is a front view showing a finished chip capacitor, FIG. 9 is a perspective view thereof, and FIG. 10 is a perspective view showing a conventional chip capacitor. 1 ... Laminating process, 2 ... Stacking process, 3 ... Slit forming process, 4 ... Firing process, 5 ... End electrode film forming process,
6 ... Electroplating process, 7 ... Cutting process, 10 ... Unfired monolithic ceramic dielectric substrate, 11 ... Slit hole, 12 ...
… Rod-shaped part, 15 …… End electrode, 16… Chip-shaped dielectric plate,
20 …… Perforated ceramic dielectric substrate, 21 …… Internal capacitance electrode, 22 …… Metal thin film, 23 …… Metal plating film.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Akira Onodera 1-13-1 Nihonbashi, Chuo-ku, Tokyo TDK Corporation (72) Inventor Hiroshi Ikeda 1-13-1 Nihonbashi, Chuo-ku, Tokyo TDK (72) Inventor Shinya Yoshihara 1-13-1 Nihonbashi, Chuo-ku, Tokyo TDK Corporation (72) Inventor Kenichi Saito 1-13-1 Nihonbashi, Chuo-ku, Tokyo TDK Corporation ( 56) References JP-A 1-221912 (JP, A) JP-A 62-195111 (JP, A) JP-B 60-7363 (JP, B1)

Claims (1)

(57) [Claims] 1. A method for stacking unfired ceramic dielectric sheets provided with required capacitance electrodes, applying pressure treatment to produce an unfired laminated ceramic substrate, and forming slit holes in the unfired laminated ceramic substrate. After forming a rod-shaped portion between the slit holes parallel to each other, it is fired to form a perforated ceramic dielectric substrate in which the capacitance electrode is provided on the rod-shaped portion, and the end of the rod-shaped portion of the perforated ceramic dielectric substrate. A plurality of at least a thin film layer of the lowermost layer having good adhesion to the dielectric substrate and a low resistance thin film layer provided on the upper side of the thin film layer of the lowermost layer so as to surround the portion in a substantially U shape. A metal thin film having a layer structure is formed by a thin film technique, and a metal plating film having a multi-layer structure having a solder resistant plating layer and a top plating layer having good solder adhesion is formed on the metal thin film. With the capacitance electrode After the formation of the end electrodes to be connected, the manufacturing method of the chip capacitor, which comprises cutting and separating the rod-shaped portion into a plurality.