JP4604553B2 - Multilayer ceramic electronic component and manufacturing method thereof - Google Patents

Multilayer ceramic electronic component and manufacturing method thereof Download PDF

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JP4604553B2
JP4604553B2 JP2004154932A JP2004154932A JP4604553B2 JP 4604553 B2 JP4604553 B2 JP 4604553B2 JP 2004154932 A JP2004154932 A JP 2004154932A JP 2004154932 A JP2004154932 A JP 2004154932A JP 4604553 B2 JP4604553 B2 JP 4604553B2
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ceramic laminate
thick film
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JP2005340371A (en
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哲久 松本
重克 山本
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Murata Manufacturing Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/002Details
    • H01G4/018Dielectrics
    • H01G4/06Solid dielectrics
    • H01G4/08Inorganic dielectrics
    • H01G4/12Ceramic dielectrics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/30Stacked capacitors

Description

本発明は、積層セラミック電子部品、特に、三端子型積層コンデンサや積層LC部品などの積層セラミック電子部品およびその製造方法に関する。   The present invention relates to a multilayer ceramic electronic component, in particular, a multilayer ceramic electronic component such as a three-terminal multilayer capacitor or a multilayer LC component, and a method for manufacturing the same.

一般に、三端子型積層コンデンサなどの積層セラミック電子部品の製造は、多数のセラミック積層体が集合したマザーセラミック積層体ブロックを形成した後に、このマザーセラミック積層体ブロックをコンデンサ導体などの内部導体の配置に合わせてカットし、個々のセラミック積層体を切り出す。そして、切り出されたセラミック積層体は焼成された後、表面に外部電極が形成され、製品とされる。   In general, in the manufacture of multilayer ceramic electronic components such as three-terminal multilayer capacitors, a mother ceramic multilayer block in which a large number of ceramic multilayer bodies are assembled is formed, and then this mother ceramic multilayer block is arranged as an inner conductor such as a capacitor conductor. And cut out individual ceramic laminates. Then, after the cut ceramic laminate is fired, an external electrode is formed on the surface to obtain a product.

ところで、三端子型積層コンデンサは、二端子型積層コンデンサと比較して等価直列インダクタンスが小さいため、たとえば電源ラインからの高周波ノイズをバイパス経路を設けて除去するバイパスコンデンサに適している。高周波帯域における挿入損失特性の劣化を少なくすることができるからである。   By the way, the three-terminal multilayer capacitor has a smaller equivalent series inductance than the two-terminal multilayer capacitor, and is therefore suitable as a bypass capacitor that removes high-frequency noise from a power supply line by providing a bypass path, for example. This is because the deterioration of the insertion loss characteristic in the high frequency band can be reduced.

ところが、近年、ノイズがより一層高周波化しており、三端子型積層コンデンサにおいても高周波帯域における挿入損失特性の劣化を防ぐために、等価直列インダクタンスをさらに小さくする必要がある。また、周波数および強さが様々なノイズに対応するためには、コンデンサ容量を任意に設定できる必要があるので、大きいコンデンサ容量を確保できることが必要となる。   However, in recent years, noise has been further increased in frequency, and it is necessary to further reduce the equivalent series inductance in order to prevent deterioration of insertion loss characteristics in a high frequency band even in a three-terminal multilayer capacitor. Further, in order to cope with noise having various frequencies and strengths, it is necessary to be able to arbitrarily set the capacitor capacity, so it is necessary to ensure a large capacitor capacity.

この対策として、たとえば特許文献1に示す三端子型積層コンデンサが知られている。図10に示すように、この三端子型積層コンデンサ61は、広面積の内部信号導体63を表面に設けた誘電体シート62と、広面積の内部グランド導体64を表面に設けた誘電体シート62とを交互に任意の枚数積み重ねた後、さらにその上下に外層用誘電体シート62を積層したものである。このように、内部信号導体63と内部グランド導体64とが、誘電体シート62を間に挟むことでコンデンサ容量を形成している。   As a countermeasure, for example, a three-terminal multilayer capacitor disclosed in Patent Document 1 is known. As shown in FIG. 10, this three-terminal multilayer capacitor 61 includes a dielectric sheet 62 provided with a large area internal signal conductor 63 on the surface and a dielectric sheet 62 provided with a large area internal ground conductor 64 on the surface. Are stacked alternately, and then outer layer dielectric sheets 62 are stacked on the upper and lower sides thereof. In this way, the internal signal conductor 63 and the internal ground conductor 64 form a capacitor capacity by sandwiching the dielectric sheet 62 therebetween.

図11に示すように、誘電体シート62を積層して構成されたセラミック積層体70の左右の側面には、外部信号電極71,72が形成され、手前側および奥側の側面全面には、外部グランド電極73,74が形成されている。   As shown in FIG. 11, external signal electrodes 71 and 72 are formed on the left and right side surfaces of the ceramic laminate 70 formed by laminating the dielectric sheets 62, and on the entire side surfaces on the near side and the back side, External ground electrodes 73 and 74 are formed.

以上の構成からなる三端子型積層コンデンサ61は、内部信号導体63と内部グランド導体64との対向面積が大きくとれるため、大きいコンデンサ容量を確保することができる。しかも、セラミック積層体70の手前側および奥側の側面全面には、外部グランド電極73,74が形成されているため、外部グランド電極73,74から内部信号導体63と内部グランド導体64との対向部分までの距離を全体的に短くでき、等価直列インダクタンスを小さくできる。   The three-terminal multilayer capacitor 61 having the above configuration can secure a large capacitor capacity because the facing area between the internal signal conductor 63 and the internal ground conductor 64 can be increased. Moreover, since the external ground electrodes 73 and 74 are formed on the entire front and back side surfaces of the ceramic laminate 70, the internal signal conductor 63 and the internal ground conductor 64 are opposed to each other from the external ground electrodes 73 and 74. The distance to the part can be shortened as a whole, and the equivalent series inductance can be reduced.

しかしながら、このように外部グランド電極73,74を、セラミック積層体70の手前側および奥側の側面全面に形成すると、外部グランド電極73,74と外部信号電極71,72相互の間隔が狭くなり、マイグレーションやはんだブリッジなどの問題が発生する。また、外部信号電極71,72や外部グランド電極73,74を折り返し部のない構造にすると、はんだの濡れ上がりやセルフアライメント性が悪くなり、実装性に問題が出てくる。さらに、外部グランド電極73,74の塗布位置ずれも、外部電極間の距離を小さくしてしまう。
特開2003−100552号公報
However, when the external ground electrodes 73 and 74 are formed on the entire front and back side surfaces of the ceramic laminate 70 as described above, the distance between the external ground electrodes 73 and 74 and the external signal electrodes 71 and 72 is reduced. Problems such as migration and solder bridges occur. Further, if the external signal electrodes 71 and 72 and the external ground electrodes 73 and 74 have a structure without a folded portion, solder wet-up and self-alignment properties are deteriorated, resulting in problems in mountability. Furthermore, the application position shift of the external ground electrodes 73 and 74 also reduces the distance between the external electrodes.
Japanese Patent Laid-Open No. 2003-100552

そこで、本発明の目的は、高周波特性を維持しつつ、外部電極相互の間隔を充分確保した、マイグレーションなどの信頼性に対して強い積層セラミック電子部品およびその製造方法を提供することにある。   SUMMARY OF THE INVENTION An object of the present invention is to provide a multilayer ceramic electronic component that is strong in reliability such as migration and maintains a high frequency characteristic while maintaining a sufficient interval between external electrodes, and a method for manufacturing the same.

前記目的を達成するため、本発明に係る積層セラミック電子部品は、複数の内部導体と複数のセラミック層を積層して構成した矩形体状のセラミック積層体と、前記セラミック積層体の表面に設けられ、かつ、セラミック積層体の側面に導出した前記内部導体の引出し部に電気的に接続している外部電極とを備え、前記外部電極が、前記セラミック積層体の上面、側面および下面に延在し、かつ、セラミック積層体の側面に導出した前記内部導体の引出し部のそれぞれの一部分に、該引出し部の中央部を帯状に覆いかつ該中央部以外を覆わないように、接続している帯状の厚膜導体と、前記厚膜導体を覆い、かつ、セラミック積層体の側面に導出した前記内部導体の引出し部であって前記厚膜導体で覆われた部分以外の部分および前記内部導体の引出し部相互間の隙間を直接覆った状態で、前記セラミック積層体の側面に設けられているめっき膜とからなることを特徴とする。 In order to achieve the above object, a multilayer ceramic electronic component according to the present invention is provided on a surface of a rectangular ceramic laminate formed by laminating a plurality of internal conductors and a plurality of ceramic layers, and on the surface of the ceramic laminate. And an external electrode electrically connected to the lead portion of the internal conductor led to the side surface of the ceramic laminate, and the external electrode extends to the upper surface, the side surface, and the lower surface of the ceramic laminate. In addition, the strips connected to the respective portions of the lead portions of the inner conductor led out to the side surface of the ceramic laminate so as to cover the central portion of the lead portion in a strip shape and not to cover other portions than the central portion . A thick film conductor, and a portion of the internal conductor that extends to the side surface of the ceramic laminate and covers the thick film conductor, other than the portion covered with the thick film conductor, and the internal conductor While covering the gap between the lead portions cross directly, characterized in that comprising a plating film provided on a side surface of the ceramic laminate.

以上の構成により、帯状厚膜導体がセラミック積層体の上面および下面に延在しているため、外部電極は折り返し部のある構造になる。また、セラミック積層体の側面に導出した内部導体の引出し部のそれぞれが帯状厚膜導体によって電気的に接続されているため、帯状厚膜導体および内部導体の引出し部を全て覆うめっき膜が、セラミック積層体の側面に広面積に位置精度良く形成される。   With the above configuration, since the strip-shaped thick film conductor extends on the upper surface and the lower surface of the ceramic laminate, the external electrode has a structure with a folded portion. In addition, since each of the lead portions of the inner conductor led out to the side surface of the ceramic laminate is electrically connected by the strip-shaped thick film conductor, the plating film covering all of the strip-shaped thick film conductor and the lead portion of the inner conductor is ceramic. It is formed on the side surface of the laminate with a large area and high positional accuracy.

また、本発明に係る積層セラミック電子部品の製造方法は、複数の内部導体と複数のセラミック層を積層して矩形体状のセラミック積層体を形成する工程と、前記セラミック積層体の上面、側面および下面に延在し、かつ、セラミック積層体の側面に導出した前記内部導体の引出し部のそれぞれの一部分に、該引出し部の中央部を帯状に覆いかつ該中央部以外を覆わないように、接続する帯状の厚膜導体を形成する工程と、電解めっき法にて、前記厚膜導体およびセラミック積層体の側面に導出した前記内部導体の引出し部であって前記厚膜導体で覆われた部分以外の部分を直接めっき膜で覆うとともに、前記内部導体の引出し部に析出しためっき膜の成長によって、前記内部導体の引出し部相互間の隙間をめっき膜で直接覆って、前記セラミック積層体の側面にめっき膜を形成し、前記厚膜導体と前記めっき膜からなる外部電極を形成する工程とを備えたことを特徴とする。 Further, the method for manufacturing a multilayer ceramic electronic component according to the present invention includes a step of laminating a plurality of internal conductors and a plurality of ceramic layers to form a rectangular ceramic laminate, an upper surface, a side surface of the ceramic laminate, and Connected to each of the lead portions of the inner conductor extended to the lower surface and led to the side surface of the ceramic laminate so as to cover the central portion of the lead portion in a band shape and not to cover other portions than the central portion. Forming a strip-shaped thick film conductor, and a lead-out portion of the inner conductor led out to a side surface of the thick film conductor and the ceramic laminate by electrolytic plating, other than a portion covered with the thick film conductor And the gap between the lead portions of the inner conductor is directly covered with the plating film by the growth of the plating film deposited on the lead portion of the inner conductor. Tsu forming a plated film on the side surface of the click laminate characterized by comprising a step of forming an external electrode composed of the plating film and the thick film conductor.

以上の方法により、高周波特性を維持しつつ、外部電極相互の間隔を充分確保した、マイグレーションなどの信頼性に対して強い積層セラミック電子部品が容易に製造される。   By the above method, a multilayer ceramic electronic component that is strong in reliability such as migration and that maintains a high frequency characteristic and sufficiently secures an interval between external electrodes is easily manufactured.

本発明によれば、外部電極が、セラミック積層体の上面、側面および下面に延在し、かつ、セラミック積層体の側面に導出した内部導体の引出し部のそれぞれの一部分に、該引出し部の中央部を帯状に覆いかつ該中央部以外を覆わないように、接続している帯状の厚膜導体と、厚膜導体を覆い、かつ、セラミック積層体の側面に導出した内部導体の引出し部であって厚膜導体で覆われた部分以外の部分および前記内部導体の引出し部相互間の隙間を直接覆った状態で、前記セラミック積層体の側面に設けられているめっき膜とからなる。従って、折り返し部のある構造の外部電極を、セラミック積層体の側面に広面積に位置精度良く形成することができる。この結果、高周波特性を維持しつつ、外部電極相互の間隔を充分確保した、マイグレーションなどの信頼性に対して強い積層セラミック電子部品を得ることができる。 According to the present invention, the external electrode extends on the upper surface, the side surface, and the lower surface of the ceramic laminate, and the central portion of the lead portion is provided on each part of the lead portion of the internal conductor led to the side surface of the ceramic laminate. This is a strip-shaped thick film conductor connected so as to cover the portion in a strip shape and not cover the other than the central portion , and an inner conductor lead-out portion that covers the thick film conductor and is led out to the side surface of the ceramic laminate. And a plating film provided on the side surface of the ceramic laminate in a state in which a portion other than the portion covered with the thick film conductor and a gap between the lead portions of the inner conductor are directly covered. Accordingly, the external electrode having a structure with the folded portion can be formed on the side surface of the ceramic laminate with a large area and with high positional accuracy. As a result, it is possible to obtain a multilayer ceramic electronic component that is strong in reliability such as migration and that maintains a high frequency characteristic and sufficiently secures an interval between external electrodes.

以下に、本発明に係る積層セラミック電子部品およびその製造方法の実施例について添付の図面を参照して説明する。なお、以下の実施例では1個のセラミック積層体しか表示していないが、実際には、多数のセラミック積層体が集合したマザーセラミック積層体ブロックを形成した後に、このマザーセラミック積層体ブロックを内部導体の配置に合わせてカットし、個々のセラミック積層体を切り出している。   Embodiments of a multilayer ceramic electronic component and a method for manufacturing the same according to the present invention will be described below with reference to the accompanying drawings. In the following examples, only one ceramic laminate is shown, but actually, after forming a mother ceramic laminate block in which a large number of ceramic laminates are assembled, It cuts according to arrangement | positioning of a conductor, and cuts out each ceramic laminated body.

[第1実施例、図1〜図6]
図1に示すように、三端子型積層コンデンサ1は、広面積の内部信号導体2を表面に設けた誘電体セラミックグリーンシート12と、広面積の内部グランド導体3を表面に設けた誘電体セラミックグリーンシート12とを交互に任意の枚数積み重ねた後、さらにその上下に保護用誘電体セラミックグリーンシート13を積層したものである。このように、内部信号導体2と内部グランド導体3とが、誘電体セラミックグリーンシート12を間に挟むことでコンデンサ容量を形成している。
[First embodiment, FIGS. 1 to 6]
As shown in FIG. 1, a three-terminal multilayer capacitor 1 includes a dielectric ceramic green sheet 12 having a large area internal signal conductor 2 on the surface and a dielectric ceramic having a large area internal ground conductor 3 on the surface. An arbitrary number of green sheets 12 are alternately stacked, and a protective dielectric ceramic green sheet 13 is further stacked on the top and bottom thereof. As described above, the internal signal conductor 2 and the internal ground conductor 3 form a capacitor capacitance by sandwiching the dielectric ceramic green sheet 12 therebetween.

誘電体セラミックグリーンシート12,13は、例えばBaTiO3を主成分とするセラミック粉末を結合剤などと一緒に混練したものをドクターブレード法などの方法でシート状(厚さは2〜6μm)にしたものである。内部信号導体2および内部グランド導体3はそれぞれ、誘電体セラミックグリーンシート12上にスクリーン印刷法などの方法で形成される。これらの導体2,3は、Ni,Ag,Pd,Cu,Auやこれらの合金などからなる。導体2,3の厚みは0.5〜1.5μm程度としている。 The dielectric ceramic green sheets 12 and 13 are formed into a sheet shape (thickness: 2 to 6 μm) by a method such as a doctor blade method obtained by kneading ceramic powder mainly composed of BaTiO 3 together with a binder, for example. Is. The internal signal conductor 2 and the internal ground conductor 3 are each formed on the dielectric ceramic green sheet 12 by a method such as screen printing. These conductors 2 and 3 are made of Ni, Ag, Pd, Cu, Au, alloys thereof, or the like. The thickness of the conductors 2 and 3 is about 0.5 to 1.5 μm.

内部信号導体2の一方の引出し部2aはシート12の手前側の辺に露出し、他方の引出し部2aはシート12の奥側の辺に露出している。また、内部グランド導体3の一方の引出し部3aはシート12の左辺に露出し、他方の引出し部3aはシート12の右辺に露出している。   One lead portion 2 a of the internal signal conductor 2 is exposed on the front side of the sheet 12, and the other lead portion 2 a is exposed on the back side of the sheet 12. One lead portion 3 a of the internal ground conductor 3 is exposed on the left side of the sheet 12, and the other lead portion 3 a is exposed on the right side of the sheet 12.

以上の構成からなる誘電体セラミックグリーンシート12,13を積層した後、圧着して一体的に焼成することにより、図2に示すような直方体形状を有する積層体20とされる。積層体20の四つの側面には、内部グランド導体2および内部グランド導体3のそれぞれの引出し部2a,3aが露出している。内部信号導体2の引出し部2a相互の間隔および内部グランド導体3の引出し部3a相互の間隔は、それぞれ後述の外部電極21〜24のめっき膜46の厚さの2倍以下に設定されている。   After the dielectric ceramic green sheets 12 and 13 having the above-mentioned configuration are laminated, they are pressed and integrally fired to obtain a laminated body 20 having a rectangular parallelepiped shape as shown in FIG. On the four side surfaces of the multilayer body 20, the lead portions 2 a and 3 a of the internal ground conductor 2 and the internal ground conductor 3 are exposed. The distance between the lead portions 2a of the internal signal conductor 2 and the distance between the lead portions 3a of the internal ground conductor 3 are set to be not more than twice the thickness of the plating film 46 of the external electrodes 21 to 24 described later.

次に図3に示すように、積層体20を横倒しの状態でスリット状の開口41を設けたプレート40上に配置し、導電性ペースト45を積層体20の側面に塗布する。すなわち、Cuなどを主成分とした導電性ペースト45を内部に溜めた金属槽の上面に、スリット状の開口41を設けたプレート40を配置し、導電性ペースト45を下から押し上げることにより、開口41から導電性ペースト45をプレート40上に押出す。次に、積層体20の側面を、押出された導電性ペーストにディップすることにより、積層体20の側面に導電性ペースト45を付与した後、乾燥、焼結し固着させる。   Next, as shown in FIG. 3, the laminate 20 is placed on a plate 40 provided with slit-like openings 41 in a laid state, and a conductive paste 45 is applied to the side surface of the laminate 20. That is, the plate 40 provided with the slit-shaped opening 41 is arranged on the upper surface of the metal tank in which the conductive paste 45 mainly containing Cu or the like is stored, and the conductive paste 45 is pushed up from below to open the opening. From 41, conductive paste 45 is extruded onto plate 40. Next, the side surface of the laminated body 20 is dipped into the extruded conductive paste so that the conductive paste 45 is applied to the side surface of the laminated body 20, and then dried, sintered, and fixed.

こうして、図4に示すように、積層体20の上面、側面および下面に延在し、かつ、積層体20の側面に導出した内部信号導体2や内部グランド導体3の引出し部2a,3aのそれぞれに電気的に接続する帯状の厚膜導体45(厚さは20〜80μm)を形成する。ここで、内部信号導体2の引出し部2aに接続する厚膜導体45は、内部信号導体2の引出し部2a全体を覆っている。一方、内部グランド導体3の引出し部3aに接続する厚膜導体45は、内部グランド導体3の引出し部3aの中央部に配置され、内部グランド導体3の引出し部3aの一部しか覆っていない。   Thus, as shown in FIG. 4, each of the lead portions 2 a and 3 a of the internal signal conductor 2 and the internal ground conductor 3 extending to the top surface, the side surface, and the bottom surface of the multilayer body 20 and leading to the side surface of the multilayer body 20. A strip-shaped thick film conductor 45 (having a thickness of 20 to 80 μm) is formed so as to be electrically connected to. Here, the thick film conductor 45 connected to the lead portion 2 a of the internal signal conductor 2 covers the whole lead portion 2 a of the internal signal conductor 2. On the other hand, the thick film conductor 45 connected to the lead portion 3 a of the internal ground conductor 3 is disposed at the center of the lead portion 3 a of the internal ground conductor 3 and covers only a part of the lead portion 3 a of the internal ground conductor 3.

次に、積層体20をめっき浴槽に入れて湿式めっき(電解めっき)を行い、それぞれの膜厚が2〜15μm程度のNiおよびSnのめっき膜を形成する。このとき、図5(A)に示すように、めっき浴槽内で通電媒体として機能するスチールボール50が、厚膜導体45の表面に接触して厚膜導体45の表面にめっき膜46を形成させる。   Next, the laminate 20 is put in a plating bath and wet plating (electrolytic plating) is performed to form a Ni and Sn plating film having a thickness of about 2 to 15 μm. At this time, as shown in FIG. 5A, the steel ball 50 functioning as a current-carrying medium in the plating bath is brought into contact with the surface of the thick film conductor 45 to form a plating film 46 on the surface of the thick film conductor 45. .

さらに、積層体20の側面に導出した内部グランド導体3の引出し部3aに厚膜導体45が電気的に接続しているので、図5(B)に示すように、厚膜導体45に覆われていない引出し部3aの露出部分にも、めっき膜46が析出する。めっき膜46は、四方にめっき膜の厚み程度成長するため、引出し部3a相互の間隔d1をめっき膜46の厚みd2の2倍以下に設定しておくことにより、引出し部3aの両サイドから成長しためっき膜46が、引出し部3a相互間の隙間を覆う。   Further, since the thick film conductor 45 is electrically connected to the lead portion 3a of the internal ground conductor 3 led out to the side surface of the multilayer body 20, it is covered with the thick film conductor 45 as shown in FIG. The plating film 46 is also deposited on the exposed portion of the undrawn portion 3a. Since the plating film 46 grows to the thickness of the plating film in all directions, it is grown from both sides of the drawing portion 3a by setting the distance d1 between the drawing portions 3a to be not more than twice the thickness d2 of the plating film 46. The plated film 46 thus covered covers the gap between the drawn portions 3a.

なお、厚膜導体45で引出し部2a相互および引出し部3a相互を電気的に接続していない状態の場合、図5(C)に示すように、スチールボール50が引出し部2a,3aに接触し難いため、引出し部2a,3aの表面に均一にめっきが析出しない。   When the thick film conductor 45 is not in an electrical connection between the lead portions 2a and the lead portions 3a, the steel ball 50 comes into contact with the lead portions 2a and 3a as shown in FIG. Since it is difficult, plating does not deposit uniformly on the surfaces of the drawn portions 2a and 3a.

こうして、図6に示すように、積層体20の四つの側面に、厚膜導体45とめっき膜46とからなる外部信号電極21,22および外部グランド電極23,24が形成される。外部信号電極21は内部信号導体2の一方の引出し部2aに電気的に接続され、外部信号電極22は内部信号導体2の他方の引出し部2aに電気的に接続されている。外部グランド電極23は内部グランド導体3の一方の引出し部3aに電気的に接続され、外部グランド電極24は内部グランド導体3の他方の引出し部3aに電気的に接続されている。   Thus, as shown in FIG. 6, the external signal electrodes 21 and 22 and the external ground electrodes 23 and 24 composed of the thick film conductor 45 and the plating film 46 are formed on the four side surfaces of the multilayer body 20. The external signal electrode 21 is electrically connected to one lead portion 2 a of the internal signal conductor 2, and the external signal electrode 22 is electrically connected to the other lead portion 2 a of the internal signal conductor 2. The external ground electrode 23 is electrically connected to one lead portion 3 a of the internal ground conductor 3, and the external ground electrode 24 is electrically connected to the other lead portion 3 a of the internal ground conductor 3.

ここで、外部グランド電極23,24において、内部グランド導体3の引出し部3a上にめっき成長で形成されためっき膜46と積層体20の底面との間隔d3は、この三端子型積層コンデンサ1をプリント基板などに実装する際に使用するはんだペーストの厚さの半分以下に設定することが好ましい。間隔d3がこれ以上大きくなると、実装時に、はんだの濡れ上がりが悪くなる場合があり、高周波特性に影響がでるからである。例えば、はんだペーストの厚さが約50μmの場合、間隔d3は25μm以下とする。   Here, in the external ground electrodes 23 and 24, the distance d3 between the plating film 46 formed by plating growth on the lead portion 3a of the internal ground conductor 3 and the bottom surface of the multilayer body 20 is determined by the three-terminal multilayer capacitor 1. It is preferable to set it to half or less of the thickness of the solder paste used when mounting on a printed circuit board. This is because if the distance d3 is larger than this, the solder wet-up may be deteriorated during mounting, which affects the high-frequency characteristics. For example, when the thickness of the solder paste is about 50 μm, the interval d3 is set to 25 μm or less.

以上の構成からなる三端子型積層コンデンサ1は、内部信号導体2と内部グランド導体3との対向面積が大きくとれるため、大きいコンデンサ容量を確保することができる。しかも、帯状厚膜導体45が積層体20の上面、側面および下面に延在しているため、外部信号電極21,22および外部グランド電極23,24は折り返し部のある構造をしている。従って、この三端子型積層コンデンサ1をプリント基板などに実装する際、はんだの濡れ上がりやセルフアライメント性が問題になる心配は殆どない。   The three-terminal multilayer capacitor 1 having the above configuration can secure a large capacitor capacity because the facing area between the internal signal conductor 2 and the internal ground conductor 3 can be increased. In addition, since the strip-shaped thick film conductor 45 extends to the upper surface, the side surface, and the lower surface of the multilayer body 20, the external signal electrodes 21 and 22 and the external ground electrodes 23 and 24 have a structure with a folded portion. Therefore, when mounting the three-terminal multilayer capacitor 1 on a printed circuit board or the like, there is almost no concern that solder wetting or self-alignment will be a problem.

また、外部グランド電極23,24は、積層体20の側面に導出した内部グランド導体3の引出し部3aのそれぞれの一部分が帯状厚膜導体45によって電気的に接続されているため、厚膜導体45および積層体20の側面に導出した内部グランド導体3の引出し部3aを全て覆うめっき膜46が、積層体20の手前側および奥側の側面に広面積に位置精度良く形成することができる。このため、外部グランド電極23,24から内部信号導体2と内部グランド導体3との対向部分までの距離を全体的に短くでき、等価直列インダクタンスを小さくできる。   In addition, since the external ground electrodes 23 and 24 are electrically connected to each other by the strip-shaped thick film conductor 45 in the lead portions 3a of the internal ground conductor 3 led out to the side surface of the multilayer body 20, the thick film conductor 45 In addition, the plating film 46 that covers all the lead portions 3 a of the internal ground conductor 3 led out to the side surface of the multilayer body 20 can be formed on the front and back side surfaces of the multilayer body 20 in a wide area with high positional accuracy. For this reason, the distance from the external ground electrodes 23 and 24 to the facing portion between the internal signal conductor 2 and the internal ground conductor 3 can be shortened as a whole, and the equivalent series inductance can be reduced.

さらに、外部グランド電極23,24の折り返し部は必要最小限の大きさで形成され、積層体20の側面には広面積で外部グランド電極23,24を形成することができるので、高周波特性を維持しつつ、外部電極21〜24相互の間隔を充分確保することができ、マイグレーションやはんだブリッジなどの信頼性に対して強い三端子型積層コンデンサ1を得ることができる。   Further, the folded portions of the external ground electrodes 23 and 24 are formed with the minimum necessary size, and the external ground electrodes 23 and 24 can be formed on the side surface of the laminate 20 with a large area, so that high frequency characteristics are maintained. However, the space between the external electrodes 21 to 24 can be sufficiently secured, and the three-terminal multilayer capacitor 1 strong against reliability such as migration and solder bridge can be obtained.

[第2実施例、図7〜図9]
図7に示すように、第2実施例の三端子型積層コンデンサ1Aは、前記第1実施例の三端子型積層コンデンサ1において、内部信号導体2の導体幅を広くして、より一層大きなコンデンサ容量を得ることができるようにしたものである。さらに、三端子型積層コンデンサ1Aは、所定の保護用誘電体セラミックグリーンシート13の表面にダミー導体4,5を設けて、内部グランド導体3の引出し部3a上にめっき成長で形成されためっき膜と積層体20の底面との間隔d3が、この三端子型積層コンデンサ1Aをプリント基板などに実装する際に使用するはんだペーストの厚さの半分以下に確実になるようにしている。
[Second Embodiment, FIGS. 7 to 9]
As shown in FIG. 7, the three-terminal multilayer capacitor 1A according to the second embodiment is the same as the three-terminal multilayer capacitor 1 according to the first embodiment except that the internal signal conductor 2 is made wider and the capacitor is larger. The capacity can be obtained. Further, the three-terminal multilayer capacitor 1A is provided with dummy conductors 4 and 5 on the surface of a predetermined protective dielectric ceramic green sheet 13, and a plating film formed by plating growth on the lead portion 3a of the internal ground conductor 3. The distance d3 between the multilayer body 20 and the bottom surface of the multilayer body 20 is ensured to be less than half the thickness of the solder paste used when the three-terminal multilayer capacitor 1A is mounted on a printed circuit board or the like.

以上の構成からなる誘電体セラミックグリーンシート12,13を積層した後、圧着して一体的に焼成することにより、図8に示すような直方体形状を有する積層体20とされる。積層体20の四つの側面には、内部グランド導体2および内部グランド導体3のそれぞれの引出し部2a,3a、並びに、ダミー導体4,5が露出している。内部信号導体2の引出し部2aおよびダミー導体4相互の間隔、並びに、内部グランド導体3の引出し部3aおよびダミー導体5相互の間隔は、それぞれ後述の外部電極21〜24のめっき膜の厚さの2倍以下に設定されている。   After the dielectric ceramic green sheets 12 and 13 having the above-mentioned configuration are laminated, they are pressed and integrally fired to obtain a laminated body 20 having a rectangular parallelepiped shape as shown in FIG. On the four side surfaces of the laminate 20, the lead portions 2a and 3a of the internal ground conductor 2 and the internal ground conductor 3, and the dummy conductors 4 and 5 are exposed. The distance between the lead part 2a of the internal signal conductor 2 and the dummy conductor 4 and the distance between the lead part 3a of the internal ground conductor 3 and the dummy conductor 5 are the thicknesses of the plating films of the external electrodes 21 to 24, which will be described later, respectively. It is set to 2 times or less.

次に、前記第1実施例と同様のディップ法で、積層体20の側面に導電性ペーストを付与した後、乾燥、焼結し固着させる。こうして、積層体20の上面、側面および下面に延在し、かつ、積層体20の側面に導出した内部信号導体2や内部グランド導体3の引出し部2a,3aのそれぞれに電気的に接続する帯状の厚膜導体を形成する。ここで、内部信号導体2の引出し部2aやダミー導体4に接続する厚膜導体、並びに、内部グランド導体3の引出し部3aやダミー導体5に接続する厚膜導体は、引出し部2a,3aやダミー導体4,5の中央部に配置され、引出し部2a,3aやダミー導体4,5の一部しか覆っていない。   Next, a conductive paste is applied to the side surface of the laminate 20 by the same dipping method as in the first embodiment, and then dried, sintered, and fixed. Thus, strips extending to the upper surface, the side surface, and the lower surface of the multilayer body 20 and electrically connected to the lead portions 2a and 3a of the internal signal conductor 2 and the internal ground conductor 3 led to the side surface of the multilayer body 20, respectively. The thick film conductor is formed. Here, the thick film conductor connected to the lead portion 2a and the dummy conductor 4 of the internal signal conductor 2 and the thick film conductor connected to the lead portion 3a and the dummy conductor 5 of the internal ground conductor 3 are the lead portions 2a, 3a and The dummy conductors 4 and 5 are arranged at the center and cover only the lead portions 2a and 3a and the dummy conductors 4 and 5.

次に、前記第1実施例と同様に、積層体20をめっき浴槽に入れて湿式めっき(電解めっき)を行い、それぞれの膜厚が2〜15μm程度のNiおよびSnのめっき膜を形成する。積層体20の側面に導出した内部グランド導体2,3の引出し部2a,3aやダミー導体4,5に厚膜導体が電気的に接続しているので、厚膜導体に覆われていない引出し部2a,3aやダミー導体4,5の露出部分にも、めっき膜が析出する。めっき膜は、四方にめっき膜の厚み程度成長するため、引出し部2a,3aやダミー導体4,5の両サイドから成長しためっき膜が、引出し部2a,3aやダミー導体4,5相互間の隙間を覆う。   Next, as in the first embodiment, the laminate 20 is placed in a plating bath and wet plating (electrolytic plating) is performed to form Ni and Sn plating films having a thickness of about 2 to 15 μm. Since the thick film conductor is electrically connected to the lead portions 2a and 3a of the internal ground conductors 2 and 3 and the dummy conductors 4 and 5 led out to the side surface of the multilayer body 20, the lead portion not covered with the thick film conductor A plating film also deposits on the exposed portions of 2a, 3a and dummy conductors 4, 5. Since the plating film grows in all directions to the thickness of the plating film, the plating film grown from both sides of the lead portions 2a and 3a and the dummy conductors 4 and 5 is between the lead portions 2a and 3a and the dummy conductors 4 and 5. Cover the gap.

こうして、図9に示すように、積層体20の四つの側面に、厚膜導体とめっき膜とからなる外部信号電極21,22および外部グランド電極23,24が形成される。   In this way, as shown in FIG. 9, the external signal electrodes 21 and 22 and the external ground electrodes 23 and 24 made of the thick film conductor and the plating film are formed on the four side surfaces of the multilayer body 20.

以上の構成からなる三端子型積層コンデンサ1Aは、内部信号導体2と内部グランド導体3との対向面積が第1実施例より一層大きくとれるため、大きいコンデンサ容量を確保することができる。しかも、外部信号電極21,22が広面積に形成されているので、直流抵抗が低くなり、定格電流が高い三端子型積層コンデンサ1Aを得ることができる。   The three-terminal multilayer capacitor 1A having the above configuration can secure a large capacitor capacity because the opposing area of the internal signal conductor 2 and the internal ground conductor 3 can be made larger than that of the first embodiment. Moreover, since the external signal electrodes 21 and 22 are formed in a wide area, a three-terminal multilayer capacitor 1A having a low DC resistance and a high rated current can be obtained.

[他の実施例]
なお、本発明は前記実施例に限定されるものではなく、その要旨の範囲内で種々に変更することができる。積層セラミック電子部品は、三端子型積層コンデンサの他に、例えば積層LCフィルタ、積層インピーダンス素子、積層コイルなどがある。
[Other Examples]
In addition, this invention is not limited to the said Example, It can change variously within the range of the summary. In addition to the three-terminal multilayer capacitor, the multilayer ceramic electronic component includes, for example, a multilayer LC filter, a multilayer impedance element, and a multilayer coil.

本発明に係る積層セラミック電子部品の一実施例を示す分解斜視図。1 is an exploded perspective view showing an embodiment of a multilayer ceramic electronic component according to the present invention. 図1に示した積層セラミック電子部品の製造方法を示す斜視図。The perspective view which shows the manufacturing method of the multilayer ceramic electronic component shown in FIG. 図2に続く製造工程を示す断面図。Sectional drawing which shows the manufacturing process following FIG. 図3に続く製造工程を示す斜視図。The perspective view which shows the manufacturing process following FIG. 図4に続く製造工程を示す拡大断面図。The expanded sectional view which shows the manufacturing process following FIG. 図1に示した積層セラミック電子部品の外観斜視図。FIG. 2 is an external perspective view of the multilayer ceramic electronic component shown in FIG. 1. 本発明に係る積層セラミック電子部品の別の実施例を示す分解斜視図。The disassembled perspective view which shows another Example of the multilayer ceramic electronic component which concerns on this invention. 図7に続く製造工程を示す斜視図。The perspective view which shows the manufacturing process following FIG. 図7に示した積層セラミック電子部品の外観斜視図。FIG. 8 is an external perspective view of the multilayer ceramic electronic component shown in FIG. 7. 従来の積層セラミック電子部品を示す分解斜視図。The disassembled perspective view which shows the conventional multilayer ceramic electronic component. 図10に示した積層セラミック電子部品の外観斜視図。FIG. 11 is an external perspective view of the multilayer ceramic electronic component illustrated in FIG. 10.

符号の説明Explanation of symbols

1,1A…三端子型積層コンデンサ
2…内部信号導体
3…内部グランド導体
4,5…ダミー導体
12,13…誘電体セラミックグリーンシート
20…積層体
21,22…外部信号電極
23,24…外部グランド電極
45…厚膜導体
46…めっき膜
DESCRIPTION OF SYMBOLS 1,1A ... Three terminal type | mold multilayer capacitor 2 ... Internal signal conductor 3 ... Internal ground conductor 4,5 ... Dummy conductor 12, 13 ... Dielectric ceramic green sheet 20 ... Multilayer body 21,22 ... External signal electrode 23, 24 ... External Ground electrode 45 ... Thick film conductor 46 ... Plating film

Claims (2)

複数の内部導体と複数のセラミック層を積層して構成した矩形体状のセラミック積層体と、
前記セラミック積層体の表面に設けられ、かつ、セラミック積層体の側面に導出した前記内部導体の引出し部に電気的に接続している外部電極とを備え、
前記外部電極が、
前記セラミック積層体の上面、側面および下面に延在し、かつ、セラミック積層体の側面に導出した前記内部導体の引出し部のそれぞれの一部分に、該引出し部の中央部を帯状に覆いかつ該中央部以外を覆わないように、接続している帯状の厚膜導体と、
前記厚膜導体を覆い、かつ、セラミック積層体の側面に導出した前記内部導体の引出し部であって前記厚膜導体で覆われた部分以外の部分および前記内部導体の引出し部相互間の隙間を直接覆った状態で、前記セラミック積層体の側面に設けられているめっき膜とからなること、
を特徴とする積層セラミック電子部品。
A rectangular ceramic laminate formed by laminating a plurality of internal conductors and a plurality of ceramic layers;
An external electrode provided on the surface of the ceramic laminate and electrically connected to a lead portion of the internal conductor led to the side of the ceramic laminate,
The external electrode is
Extending to the upper surface, the side surface and the lower surface of the ceramic laminate, and covering each central portion of the lead portion of the inner conductor led out to the side surface of the ceramic laminate in a strip shape and covering the center So as not to cover other than the part, the connected strip-shaped thick film conductor,
Covering the thick film conductor and leading to the side of the ceramic laminate, the inner conductor lead-out portion other than the portion covered with the thick film conductor and the gap between the inner conductor lead-out portions Consisting of a plating film provided on the side surface of the ceramic laminate in a directly covered state,
Multilayer ceramic electronic parts characterized by
複数の内部導体と複数のセラミック層を積層して矩形体状のセラミック積層体を形成する工程と、
前記セラミック積層体の上面、側面および下面に延在し、かつ、セラミック積層体の側面に導出した前記内部導体の引出し部のそれぞれの一部分に、該引出し部の中央部を帯状に覆いかつ該中央部以外を覆わないように、接続する帯状の厚膜導体を形成する工程と、
電解めっき法にて、前記厚膜導体およびセラミック積層体の側面に導出した前記内部導体の引出し部であって前記厚膜導体で覆われた部分以外の部分を直接めっき膜で覆うとともに、前記内部導体の引出し部に析出しためっき膜の成長によって、前記内部導体の引出し部相互間の隙間をめっき膜で直接覆って、前記セラミック積層体の側面にめっき膜を形成し、前記厚膜導体と前記めっき膜からなる外部電極を形成する工程と、
を備えたことを特徴とする積層セラミック電子部品の製造方法。
A step of laminating a plurality of inner conductors and a plurality of ceramic layers to form a rectangular ceramic laminate;
Extending to the upper surface, the side surface and the lower surface of the ceramic laminate, and covering each central portion of the lead portion of the inner conductor led out to the side surface of the ceramic laminate in a strip shape and covering the center Forming a strip-shaped thick film conductor to be connected so as not to cover other than the portion ;
In the electrolytic plating method, the lead portion of the inner conductor led out to the side surface of the thick film conductor and the ceramic laminate and directly covering the portion other than the portion covered with the thick film conductor with the plating film, By the growth of the plating film deposited on the lead portion of the conductor, the gap between the lead portions of the inner conductor is directly covered with the plating film, and a plating film is formed on the side surface of the ceramic laminated body. Forming an external electrode made of a plating film;
A method for producing a multilayer ceramic electronic component comprising:
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JP4561754B2 (en) * 2007-01-30 2010-10-13 Tdk株式会社 Multilayer capacitor
JP4924490B2 (en) * 2008-03-10 2012-04-25 Tdk株式会社 Feed-through multilayer capacitor
JP2011192968A (en) 2010-02-19 2011-09-29 Murata Mfg Co Ltd Capacitor and method of manufacturing the same
JP2013021298A (en) * 2011-06-15 2013-01-31 Murata Mfg Co Ltd Multilayer ceramic electronic component
JP2013021300A (en) * 2011-06-16 2013-01-31 Murata Mfg Co Ltd Multilayer ceramic electronic component
KR101504015B1 (en) * 2013-07-09 2015-03-18 삼성전기주식회사 Multi-layered ceramic capacitor and mounting circuit board thereof
KR101504017B1 (en) * 2013-07-11 2015-03-18 삼성전기주식회사 Multi-layered ceramic capacitor and board for mounting the same
WO2024004304A1 (en) * 2022-06-27 2024-01-04 株式会社村田製作所 Feedthrough multilayer ceramic capacitor

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