JP4741735B2 - ディスク・コントローラ・メモリ・アーキテクチャ用システムおよび方法 - Google Patents
ディスク・コントローラ・メモリ・アーキテクチャ用システムおよび方法 Download PDFInfo
- Publication number
- JP4741735B2 JP4741735B2 JP2000615882A JP2000615882A JP4741735B2 JP 4741735 B2 JP4741735 B2 JP 4741735B2 JP 2000615882 A JP2000615882 A JP 2000615882A JP 2000615882 A JP2000615882 A JP 2000615882A JP 4741735 B2 JP4741735 B2 JP 4741735B2
- Authority
- JP
- Japan
- Prior art keywords
- fifo
- data
- memory
- transfer
- memory circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
- G06F3/0613—Improving I/O performance in relation to throughput
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0656—Data buffering arrangements
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0674—Disk device
- G06F3/0676—Magnetic disk device
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Human Computer Interaction (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
- Information Transfer Systems (AREA)
- Communication Control (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13271299P | 1999-05-05 | 1999-05-05 | |
| US09/547,567 US6330626B1 (en) | 1999-05-05 | 2000-04-12 | Systems and methods for a disk controller memory architecture |
| US09/548,330 US6401149B1 (en) | 1999-05-05 | 2000-04-12 | Methods for context switching within a disk controller |
| US60/132,712 | 2000-04-12 | ||
| US09/547,567 | 2000-04-12 | ||
| US09/548,330 | 2000-04-12 | ||
| PCT/US2000/012433 WO2000067107A1 (en) | 1999-05-05 | 2000-05-05 | Systems and methods for a disk controller memory architecture |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2002543514A JP2002543514A (ja) | 2002-12-17 |
| JP2002543514A5 JP2002543514A5 (enExample) | 2008-12-04 |
| JP4741735B2 true JP4741735B2 (ja) | 2011-08-10 |
Family
ID=27384336
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000615882A Expired - Lifetime JP4741735B2 (ja) | 1999-05-05 | 2000-05-05 | ディスク・コントローラ・メモリ・アーキテクチャ用システムおよび方法 |
Country Status (8)
| Country | Link |
|---|---|
| EP (1) | EP1188106B1 (enExample) |
| JP (1) | JP4741735B2 (enExample) |
| KR (1) | KR100638378B1 (enExample) |
| AT (1) | ATE321298T1 (enExample) |
| AU (1) | AU4825600A (enExample) |
| CA (1) | CA2370596C (enExample) |
| DE (1) | DE60026836T2 (enExample) |
| WO (1) | WO2000067107A1 (enExample) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030093751A1 (en) * | 2001-11-09 | 2003-05-15 | David Hohl | System and method for fast cyclic redundancy calculation |
| CN100403727C (zh) * | 2004-04-21 | 2008-07-16 | 华为技术有限公司 | 一种传递数据包编辑命令的装置及方法 |
| US20060015659A1 (en) * | 2004-07-19 | 2006-01-19 | Krantz Leon A | System and method for transferring data using storage controllers |
| US9201599B2 (en) * | 2004-07-19 | 2015-12-01 | Marvell International Ltd. | System and method for transmitting data in storage controllers |
| KR100621631B1 (ko) * | 2005-01-11 | 2006-09-13 | 삼성전자주식회사 | 반도체 디스크 제어 장치 |
| US8127089B1 (en) | 2007-02-14 | 2012-02-28 | Marvell International Ltd. | Hard disk controller which coordinates transmission of buffered data with a host |
| JP4922442B2 (ja) * | 2010-07-29 | 2012-04-25 | 株式会社東芝 | バッファ管理装置、同装置を備えた記憶装置、及びバッファ管理方法 |
| US10430210B2 (en) * | 2014-12-30 | 2019-10-01 | Micron Technology, Inc. | Systems and devices for accessing a state machine |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5315708A (en) * | 1990-02-28 | 1994-05-24 | Micro Technology, Inc. | Method and apparatus for transferring data through a staging memory |
| US6081849A (en) * | 1996-10-01 | 2000-06-27 | Lsi Logic Corporation | Method and structure for switching multiple contexts in storage subsystem target device |
| US5890207A (en) * | 1996-11-27 | 1999-03-30 | Emc Corporation | High performance integrated cached storage device |
-
2000
- 2000-05-05 DE DE60026836T patent/DE60026836T2/de not_active Expired - Lifetime
- 2000-05-05 WO PCT/US2000/012433 patent/WO2000067107A1/en not_active Ceased
- 2000-05-05 EP EP00930436A patent/EP1188106B1/en not_active Expired - Lifetime
- 2000-05-05 AT AT00930436T patent/ATE321298T1/de not_active IP Right Cessation
- 2000-05-05 AU AU48256/00A patent/AU4825600A/en not_active Abandoned
- 2000-05-05 KR KR1020017014078A patent/KR100638378B1/ko not_active Expired - Lifetime
- 2000-05-05 JP JP2000615882A patent/JP4741735B2/ja not_active Expired - Lifetime
- 2000-05-05 CA CA002370596A patent/CA2370596C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| KR20020019437A (ko) | 2002-03-12 |
| DE60026836T2 (de) | 2006-09-21 |
| EP1188106B1 (en) | 2006-03-22 |
| CA2370596C (en) | 2010-01-12 |
| KR100638378B1 (ko) | 2006-10-25 |
| EP1188106A1 (en) | 2002-03-20 |
| DE60026836D1 (de) | 2006-05-11 |
| CA2370596A1 (en) | 2000-11-09 |
| WO2000067107A1 (en) | 2000-11-09 |
| ATE321298T1 (de) | 2006-04-15 |
| JP2002543514A (ja) | 2002-12-17 |
| AU4825600A (en) | 2000-11-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6330626B1 (en) | Systems and methods for a disk controller memory architecture | |
| US6401149B1 (en) | Methods for context switching within a disk controller | |
| US5524268A (en) | Flexible processor-driven control of SCSI buses utilizing tags appended to data bytes to determine SCSI-protocol phases | |
| EP0489504B1 (en) | Bidirectional FIFO buffer for interfacing between two buses | |
| EP0241129B1 (en) | Addressing arrangement for a RAM buffer controller | |
| US5805927A (en) | Direct memory access channel architecture and method for reception of network information | |
| US5655151A (en) | DMA controller having a plurality of DMA channels each having multiple register sets storing different information controlling respective data transfer | |
| JP3433386B2 (ja) | 入出力記憶装置への直接メモリアクセスを行う装置及び方法 | |
| KR101035225B1 (ko) | 개량 데이터 전송을 위한 제어기 장치 및 방법 | |
| JPH077327B2 (ja) | データ転送方法 | |
| US6636927B1 (en) | Bridge device for transferring data using master-specific prefetch sizes | |
| US20190087091A1 (en) | Method and design for dynamic management of descriptors for sgl operation | |
| JPH06266649A (ja) | 複数のデータチャネルを介してデータを転送する方法及びその回路アーキテクチャ | |
| JPH02114350A (ja) | 周辺コントローラのためのバッファメモリサブシステムおよび方法 | |
| US5555390A (en) | Data storage method and subsystem including a device controller for respecifying an amended start address | |
| US7130932B1 (en) | Method and apparatus for increasing the performance of communications between a host processor and a SATA or ATA device | |
| JP4741735B2 (ja) | ディスク・コントローラ・メモリ・アーキテクチャ用システムおよび方法 | |
| EP0618537B1 (en) | System and method for interleaving status information with data transfers in a communications adapter | |
| US11010318B2 (en) | Method and apparatus for efficient and flexible direct memory access | |
| EP0478337B1 (en) | Process of storing data on, or retrieving data from a plurality of disks | |
| JPH0743687B2 (ja) | データ記憶サブシステム | |
| JP3241072B2 (ja) | コンピュータシステム | |
| JP4363431B2 (ja) | データ転送方式 | |
| WO1992015054A1 (en) | Data transfer between a data storage subsystem and host system | |
| JPH06105425B2 (ja) | データ記憶サブシステムとホスト・データ処理システム間のデータ転送方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A711 Effective date: 20060801 |
|
| RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20060823 |
|
| RD05 | Notification of revocation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7425 Effective date: 20060823 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20070308 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20080715 |
|
| A524 | Written submission of copy of amendment under article 19 pct |
Free format text: JAPANESE INTERMEDIATE CODE: A524 Effective date: 20081015 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20081216 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090316 |
|
| A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20090420 |
|
| A912 | Re-examination (zenchi) completed and case transferred to appeal board |
Free format text: JAPANESE INTERMEDIATE CODE: A912 Effective date: 20090731 |
|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20110509 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 4741735 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140513 Year of fee payment: 3 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| EXPY | Cancellation because of completion of term | ||
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
| R371 | Transfer withdrawn |
Free format text: JAPANESE INTERMEDIATE CODE: R371 |