JP4727641B2 - Tester equipment - Google Patents

Description

  The present invention relates to a tester apparatus, and more particularly to an apparatus for testing a device under test formed on a wafer.

  A wafer test system for testing a device under test formed on a wafer such as a semiconductor wafer generally includes a prober device and a tester device. A wafer, which is an object to be inspected, is placed on the prober apparatus, a test signal or power is supplied from the tester apparatus to the wafer, and a device under test formed on the wafer is tested (for example, Japanese Patent Laid-Open No. 2004-2004). -63586).

  Specifically, a signal supply circuit provided in the tester apparatus generates a test signal and supplies it to a device under test formed on the wafer. Similarly, a power supply provided in the tester apparatus A supply circuit generates a test power supply and supplies it to a device under test formed on the wafer. The prober device inspects the wafer placed on the prober device in cooperation with the tester device.

  However, in conventional wafer test systems, no protection circuit is provided in the signal supply circuit or power supply circuit of the tester device. For this reason, even if the signal or power applied to the device under test becomes overcurrent or overvoltage, it is assumed that the current limiting circuit or voltage limiting circuit provided in the current amplifier or voltage amplifier operates. Designed to keep signals and power supplied to the device under test. In other words, the current limiting circuit mounted on the current amplifier or the voltage amplifier, the limit value voltage, the current value signal, or the power source in which the voltage limiting circuit is operated are continuously supplied to the device under test.

The limiter value signal and power supply continue to be supplied to the device under test until the test in the wafer test system is completed. Therefore, although the current value and voltage are within the allowable range in the design, it is preferable. Absent. In particular, with the recent miniaturization of semiconductor devices, the risk of the device under test being heated abnormally cannot be denied. Furthermore, if the device under test is abnormally heated, the possibility of adversely affecting the device under test adjacent to it on the wafer cannot be denied.
JP 2004-63586 A

  Therefore, the present invention has been made in view of the above problems, and provides a tester device having a function of protecting a device under test from an abnormality in a signal or power supply supplied to the device under test formed on a wafer. With the goal.

In order to solve the above problems, a tester device according to the present invention provides:
A tester device for testing a device under test formed on a wafer,
A power supply abnormality detection circuit that monitors the power supplied to the device under test formed on the wafer and detects any power supply abnormality;
A signal abnormality detection circuit that monitors a signal supplied to the device under test formed on the wafer and detects when there is a signal abnormality;
When the power supply abnormality detection circuit detects a power supply abnormality and / or when the signal abnormality detection circuit detects a signal abnormality, the supply of power to the device under test and the supply of signals are stopped. A stop circuit;
It is characterized by providing.

  In this case, the power supply abnormality detection circuit monitors the power supply voltage and current supplied to the device under test, and when at least one of the power supply voltage and the power supply current value is higher than a predetermined reference value. May determine that a power supply abnormality has been detected.

  The signal abnormality detection circuit monitors the current of the driver power supply supplied to the output driver of the signal supplied to the device under test. If the current value of the driver power supply is higher than a predetermined reference value, the signal abnormality is detected. It may be determined that has been detected.

  The signal abnormality detection circuit monitors the voltage of the signal supplied to the device under test. When the logic level of the expected value of the signal is high, the voltage of the signal is higher than the reference voltage on the high level side. When it is low, it is determined that a signal abnormality is detected, and when the logic level of the expected value of the signal is low, the signal abnormality is detected when the voltage of the signal is higher than the low-level reference voltage. You may make it judge that it detected.

The tester device
A power supply circuit for supplying power to the device under test;
A signal supply circuit for supplying a signal to the device under test;
In addition,
The power abnormality detection circuit is provided in the power supply circuit,
The signal abnormality detection circuit may be provided in the signal supply circuit.

Further, the tester apparatus can simultaneously test a plurality of devices under test formed on a wafer,
The power supply abnormality detection circuit monitors the power supply for each device under test, the signal abnormality detection circuit monitors the signal for each signal of each device under test,
The supply stop circuit may stop the supply of power and signals to the device under test in which a power supply and / or signal abnormality is detected.

The control method of the tester device according to the present invention is as follows:
A tester apparatus control method for testing a device under test formed on a wafer,
Monitoring the power supplied to the device under test formed on the wafer, and detecting if there is an abnormality in the power,
Monitoring the signal supplied to the device under test formed on the wafer, and detecting if there is an abnormality in the signal;
A step of stopping the supply of power and the signal to the device under test when the abnormality of the power source is detected and / or when the abnormality of the signal is detected;
It is characterized by providing.

BEST MODE FOR CARRYING OUT THE INVENTION

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the embodiments described below do not limit the technical scope of the present invention.

  FIG. 1 is a diagram showing an overall configuration of a wafer test system 10 according to the present embodiment. The wafer test system 10 according to this embodiment constitutes a wafer level burn-in system that applies a thermal stress to a wafer and performs wafer level burn-in. However, the present invention can also be applied to a system that performs a wafer level test without applying thermal stress.

  As shown in FIG. 1, a wafer test system 10 according to this embodiment includes a prober device 20 and a tester device 30. A wafer, which is a test object, is placed on the prober device 20. When the wafer is placed on the prober device 20, electrodes of each device under test (DUT) formed on the wafer are connected to a probe provided on the prober device 20. The tester apparatus 30 supplies a test signal and a power source to each device under test in the wafer via this probe.

  In the present embodiment, the tester device 30 includes a test head unit 32, a cable 34, and a control unit 36. The test head unit 32 is connected to the probe of the prober apparatus 20 described above, supplies a test signal and a power source to each device under test on the wafer, acquires signals output from each device under test, Test the device under test at the wafer level.

  The test head unit 32 is supported by the arm support unit 21 of the prober device 20 via the arm 23 provided in the prober device 20. The arm support unit 21 is a device for facilitating the attachment / detachment of the test head unit 32 and the prober device 20 and for preventing the weight of the test head unit 32 from being directly applied to the probe of the prober device 20. The head unit 32 is movably supported. That is, the test head unit 32 is connected to the rotary shaft 22 via the arm 23, and the test head unit 32 moves between the position A and the position B by rotating the arm 23 around the rotary shaft 22. Move alternately. When the test head unit 32 is located at the position A, the test head unit 32 can perform a test by contacting the wafer. In addition, when the test head unit 32 is located at the position B, the test head unit 32 can be maintained. The control unit 36 is connected to the test head unit 32 via the cable 34 and performs various controls on the test head unit 32.

  FIG. 2 is a block diagram for explaining a connection relationship between the test head unit 32 and the wafer WF placed on the prober device 20. As shown in FIG. 4, the wafer WF is held by the wafer chuck 25 of the prober device 20. A pattern for forming a plurality of devices (chips) is formed on the wafer WF. The device on which the pattern is formed is separated by a dicer after electrical characteristics are inspected as a device under test, fixed to a lead frame or the like, and assembled as a semiconductor device.

A probe is formed on the probe card 24 in accordance with the electrode arrangement of the device formed on the wafer WF. The probe of the probe card 24 and the electrode of the device formed on the wafer WF are in contact with each other via the needle 26 and are electrically connected. On the other hand, the test head unit 32 includes a test head 50, a mother board 52, and a connector unit 54. The connector arrangement of the connector unit 54 matches the connector arrangement of the probe card 24, and the test head 50 is electrically connected to the probe card 24 via the connector unit 54. As a result, the test signals and power supplied from the test head 50 are supplied to the probe card 24 via the mother board 52 and the connector 54, and then supplied to the electrodes of each device on the wafer WF.

  FIG. 3 is a block diagram illustrating the overall configuration of the power / signal supply circuit 60 according to the present embodiment. In the present embodiment, the power / signal supply circuit 60 is provided inside the test head 50 of the test head unit 32.

  As shown in FIG. 3, the power / signal supply circuit 60 according to the present embodiment corresponds to the devices under test DUT1 to DUTn to be tested simultaneously, and includes a power supply circuit 62, a signal supply circuit 64, and a protection circuit. 66 are provided and configured. The number n of devices under test (DUT) that can be tested at a time is an arbitrary number depending on the design of the probe card 24 and the needle 26, the circuit design of the device under test in the wafer WF, and the like. The number n of devices under test to be tested at one time may be 128, 256, 768, and the like, for example.

  Each of the power supply circuits 62 is a circuit that generates power necessary for testing the device under test and supplies the power to the devices under test DUT1 to DUTn. Each of the signal supply circuits 64 generates various test signals necessary for testing the device under test and supplies the signals to the devices under test DUT1 to DUTn. The protection circuit 66 monitors the voltage and current of the corresponding power supply circuit 62 and the signal supply circuit 64, respectively, and turns off the power supply circuit 62 and the signal supply circuit 64 when an abnormality is detected. This is a circuit for stopping the supply of power and signals to the device under test.

  FIG. 4 is a diagram illustrating an example of a circuit configuration of the overcurrent overvoltage detection circuit 70 according to the present embodiment. In the present embodiment, the overcurrent overvoltage detection circuit 70 is a circuit provided inside the power supply circuit 62. 4 shows the overcurrent overvoltage detection circuit 70 of the power supply circuit 62 that supplies power to the device under test DUT1, but the overcurrent overvoltage detection circuits 70 of the other devices under test DUT2 to DUTn are the same. It is a configuration.

  As shown in FIG. 4, the overcurrent overvoltage detection circuit 70 includes an operational amplifier OP70, a resistor R70, switching elements SW70 and SW72, a measurement amplifier MA70, and comparators CO70 and CO72. .

  The power supply reference voltage VREF1 is input to the non-inverting input terminal of the operational amplifier OP70. The output terminal of the operational amplifier OP70 is connected to the resistor R70, and the resistor R70 is connected to the switching element SW72. The switching element SW72 is connected to the device under test DUT1, and power is supplied to the device under test DUT1.

  The switching element SW72 is connected to the inverting input terminal of the operational amplifier OP70 via the switching element SW70. By the negative feedback formed by the path of the switching element SW70 and the operational amplifier OP70, the voltage of the power source supplied to the device under test DUT1 is controlled to a predetermined voltage.

  The measurement amplifier MA70 acquires the voltage at the input terminal and the voltage at the output terminal of the resistor R70, and outputs the differential voltage to the inverting input terminal of the comparator CO70. Since the differential voltage output from the measurement amplifier MA70 is proportional to the current flowing through the resistor R70, the measurement amplifier MA70 measures the current flowing through the resistor R70.

  The overcurrent determination reference voltage VREF2 is input to the non-inverting input terminal of the comparator CO70. The comparator CO70 compares the differential voltage input to the inverting input terminal with the overcurrent determination reference voltage VREF2, and protects the high-level overcurrent detection signal SG1 if the overcurrent determination reference voltage VREF2 is higher. If the differential voltage is higher, the low level overcurrent detection signal SG1 is output to the protection circuit 66. As can be seen from this, the comparator CO70 monitors the current of the power source supplied to the device under test DUT1, and if it is higher than a predetermined reference value, the low-level overcurrent detection signal SG1 is sent to the protection circuit 66. Output.

  On the other hand, the voltage between the switching element SW70 and the inverting input terminal of the operational amplifier OP70 is input to the inverting input terminal of the comparator CO72. The overvoltage determination reference voltage VREF3 is input to the non-inverting input terminal of the comparator CO72. The comparator CO72 compares the voltage input to the inverting input terminal with the overvoltage determination reference voltage VREF3, and outputs a high level overvoltage detection signal SG2 to the protection circuit 66 if the overvoltage determination reference voltage VREF3 is higher. If the voltage input to the inverting input terminal is higher, the low-level overvoltage detection signal SG2 is output to the protection circuit 66. As can be seen from this, the comparator CO72 monitors the voltage of the negative feedback path, that is, the voltage of the power source supplied to the device under test DUT1, and if it is higher than a predetermined reference value, the low level overvoltage The detection signal SG2 is output to the protection circuit 66.

  As will be described in detail later, on / off of the switching elements SW70 and SW72 is controlled by a control signal CTL1 from the protection circuit 66. That is, the protection circuit 66 is in the case where the comparator CO70 has not detected an overcurrent (when the overcurrent detection signal SG1 is at a high level) and the comparator CO72 has not detected an overvoltage (overvoltage detection). When the signal SG2 is at a high level), both the switching elements SW70 and SW72 are turned on to supply power to the device under test DUT1. On the other hand, the protection circuit 66 detects when the comparator CO70 detects an overcurrent (when the overcurrent detection signal SG1 is at a low level) and / or when the comparator CO72 detects an overvoltage (overvoltage detection). When the signal SG2 is at a low level), the switching elements SW70 and SW72 are both turned off to cut off the power supply to the device under test DUT1. That is, the protection circuit 66 cuts off the supply of power when the power supply becomes overvoltage and / or overcurrent.

  FIG. 5 is a diagram illustrating an example of a circuit configuration of the abnormal signal detection circuit 80 according to the present embodiment. In the present embodiment, the abnormal signal detection circuit 80 is a circuit provided inside the signal supply circuit 64. 5 shows the abnormal signal detection circuit 80 of the signal supply circuit 64 that supplies a signal to the device under test DUT1, but the abnormal signal detection circuits 80 of the other devices under test DUT2 to DUTn have the same configuration. Further, FIG. 5 illustrates a circuit configuration for supplying m signals 1 to m to the device under test DUT1.

  As shown in FIG. 5, the abnormal signal detection circuit 80 includes high-level operational amplifiers OP82-1 to OP82-m, low-level operational amplifiers OP84-1 to OP84-m, and high-level side overcurrent detection. Circuits 82-1 to 82-m, low-level side overcurrent detection circuits 84-1 to 84-m, high-level side resistors R82-1 to R82-m, and low-level side resistors R84-1 to R84-1 R84-m, output drivers DR80-1 to DR80-m, switching elements SW80-1 to SW80-m, driver level check circuits DLC80-1 to DLC80-m, and OR circuits OR80 and OR82, It is configured.

  Since the circuit configurations for supplying the signals 1 to m are the same, here, the circuit configuration of the abnormal signal detection circuit 80 will be described based on the circuit for supplying the signal 1. The high level signal reference voltage VIH1 is input to the non-inverting input terminal of the high level side operational amplifier OP82-1. The output terminal of the operational amplifier OP82-1 is connected to the power supply terminal on the high level side of the output driver DR80-1 via the resistor R82-1.

  The output side terminal of the resistor R82-1 is connected to the inverting input terminal of the operational amplifier OP82-1, and forms a negative feedback path. As a result, power of a predetermined voltage is supplied from the operational amplifier OP82-1 to the high-level power supply terminal of the output driver DR80-1.

  Further, the voltage at the input side terminal and the voltage at the output side terminal of the resistor R82-1 are connected to the high-level side overcurrent detection circuit 82-1. The high-level overcurrent detection circuit 82-1 uses these differential voltages to monitor the current flowing through the resistor R82-1, and if the current value of the current flowing through the resistor R82-1 is higher than a predetermined reference value. The high level overcurrent detection signal is output to the OR circuit OR82. That is, the overcurrent detection circuit 82-1 is a circuit that detects an overcurrent of the power supplied to the high level side of the output driver DR80-1.

  Similarly, the low-level signal reference voltage VIL1 is input to the non-inverting input terminal of the low-level operational amplifier OP84-1. The output terminal of the operational amplifier OP84-1 is connected to the power supply terminal on the low level side of the output driver DR80-1 via the resistor R84-1.

  The output side terminal of the resistor R84-1 is connected to the inverting input terminal of the operational amplifier OP84-1, and forms a negative feedback path. As a result, power of a predetermined voltage is supplied from the operational amplifier OP84-1 to the low-level power supply terminal of the output driver DR80-1.

  Further, the voltage at the input side terminal and the voltage at the output side terminal of the resistor R84-1 are connected to the low-level side overcurrent detection circuit 84-1. The low-level side overcurrent detection circuit 84-1 uses these differential voltages to monitor the current flowing through the resistor R84-1, and if the current value of the current flowing through the resistor R84-1 is higher than a predetermined reference value. The high level overcurrent detection signal is output to the OR circuit OR82. That is, the overcurrent detection circuit 84-1 is a circuit that detects an overcurrent of the power source supplied to the low level side of the output driver DR80-1.

  FIG. 6 is a signal chart for explaining the waveforms of the input signal and the output signal of the output driver DR80-1. FIG. 6A is a diagram illustrating an example of a waveform of the input signal 1 input to the input terminal of the output driver DR80-1. FIG. 6B is a diagram illustrating an example of a waveform of the signal 1 to be output from the output driver DR80-1 when the input signal 1 of FIG. 6A is input. FIG. 6C is a diagram showing an example of a case where there is a short in the device under test and the waveform of the signal 1 is distorted. FIG. 6D is a diagram illustrating a logic level of an expected value based on the input signal 1 input to the exp terminal.

  As shown in FIGS. 5 and 6A, the input signal 1 is input to the input terminal of the output driver DR80-1. The input signal 1 is a high level or low level logic signal. As shown in FIG. 6B, the output driver DR 80-1 outputs a high level or low level output signal as a signal 1 based on the input signal 1. This signal 1 output from the output driver DR80-1 is supplied to the DUT 1 via the switching element SW80-1.

  The output terminal of the output driver DR80-1 is also connected to the din terminal of the driver level check circuit DLC80-1. The input terminal of the output driver DR80-1 is also connected to the exp terminal of the driver level check circuit DLC80-1. As shown in FIG. 6D, since the signal input to the exp terminal is the input signal 1, the signal waveform of the exp terminal is the same as the signal waveform of the input signal 1. That is, the signal waveform at the exp terminal represents the logic level of the expected value of the signal 1 output from the output driver DR80-1.

  Furthermore, the high level side reference voltage VOH1 is input to the vdh terminal of the driver level check circuit DLC80-1, and the low level side reference voltage VOL1 is input to the vdl terminal. The high-level side reference voltage VOH1 represents the reference value of the voltage of the signal 1 input to the terminal din when the logic level of the expected value input to the exp terminal is high. That is, when the logic level of the expected value is a high level and the signal 1 is lower than the high-level side reference voltage VOH1, the driver level check circuit DLC80-1 receives a high level logic level error signal from the fail terminal. Is output.

  On the other hand, the low-level side reference voltage VOL1 represents the reference value of the voltage of the signal 1 input to the terminal din when the logic level of the expected value input to the exp terminal is the low level. That is, when the logic level of the expected value is a low level and the signal 1 is higher than the low-level side reference voltage VOL1, the driver level check circuit DLC80-1 outputs a high-level logic level error signal from the fail terminal. Is output. That is, the driver level check circuit DLC80-1 outputs a low level logic level abnormal signal to the OR circuit OR80 when the voltage of the logic level of the signal 1 is within the normal range, and is not within the normal range. Is a circuit that outputs a high level logic level abnormality signal to the OR circuit OR80.

  For example, as shown in FIG. 6C, since the logic level of the expected value input to the exp terminal is high at the strobe point of the cycle T5, the signal 1 output from the output driver DR80-1 is Therefore, it is necessary to be higher than the high level side reference voltage VOH1. However, the voltage of the signal 1 input to the din terminal is lower than the high level side reference voltage VOH1. Therefore, the driver level check circuit DLC80-1 determines that the voltage of the signal 1 is not within the normal range, and outputs a high level logic level abnormality signal to the OR circuit OR80.

  As can be seen from this, the driver level check circuit DLC80-1 provides different reference voltages when the logic level of the expected value of the signal 1 is high and when it is low, and the logic level of the expected value is high. In this case, it is determined that an abnormality has been detected when the voltage of the signal 1 is lower than the high-level reference voltage VOH1, and when the logic level of the expected value is low, it is higher than the low-level reference voltage VOL1. This circuit determines that an abnormality has been detected.

  These circuit configurations are the same from signal 1 to signal m. Therefore, the OR circuit OR80 outputs a high level abnormality detection signal SG3 when any one of the signal 1 to the signal m becomes a high level. That is, when any one of the signals 1 to m is not within the normal range, the OR circuit OR80 outputs the high level level abnormality detection signal SG3, and all of the signals 1 to m are within the normal range. If it is within the range, a low level abnormality detection signal SG3 is output.

  The overcurrent detection signals output from the high level overcurrent detection circuits 82-1 to 82-m and the low level overcurrent detection circuits 84-1 to 84-m are input to the OR circuit OR82. ing. Therefore, the OR circuit OR82 outputs a high-level overcurrent detection signal SG4 when an abnormality occurs in the power supply supplied to the power supply terminals of the output drivers DR80-1 to DR80-m of the signal 1 to the signal m. When all of the power supplied to the power supply terminals of the output drivers DR80-1 to DR80-m are normal, the low-level overcurrent detection signal SG4 is output.

  As shown in FIG. 3, the level abnormality detection signal SG3 and the overcurrent detection signal SG4 are input to the protection circuit 66. That is, the level abnormality detection signal SG3 and the overcurrent detection signal SG4 are input to the protection circuit 66 provided for each device under test from the signal supply circuit 64 of each device under test.

  Further, as described above, the overcurrent detection signal SG1 and the overvoltage detection signal SG2 are also input to the protection circuit 66 provided in each of the devices under test DUT1 to DUTn from the power supply circuit 62 of each device under test. The If any one of the overcurrent detection signal SG1, the overvoltage detection signal SG2, the level abnormality detection signal SG3, and the overcurrent detection signal SG4 indicates an abnormality, the protection circuit 66 corresponds to the corresponding power supply circuit. A control signal CTL1 for turning off the switching element is output to 62 and the signal supply circuit 64.

  For example, when at least one of the overcurrent detection signal SG1 and the overvoltage detection signal SG2 output from the power supply circuit 62 of the device under test DUT1 is at a low level and / or the level output from the signal supply circuit 64 When at least one of the abnormality detection signal SG3 and the overcurrent detection signal SG4 is at a high level, the protection circuit 66 of the device under test DUT1 is connected to the power supply circuit 62 and the signal supply circuit 64 of the device under test DUT1 by switching elements. A control signal CTL1 for turning off is output. In the power supply circuit 62, the switching elements SW70 and SW72 are turned off, and in the signal supply circuit 64, the switching element SW80-1 is turned off by the control signal CTL1 for turning off the switching elements.

  As a result, the supply of power to the device under test DUT1 is stopped, and the supply of signals is also stopped. For this reason, it is possible to avoid applying an overvoltage or overcurrent to the device under test DUT1 until the test is completed, and the influence of the overvoltage or overcurrent on the device under test DUT1 is affected by the device under test DUT1. It is possible to avoid adversely affecting other adjacent devices under test.

  In particular, when performing a burn-in test in a wafer level test, the voltage applied to the device under test during the test tends to increase and the test time tends to increase, and the voltage and current applied to the device under test are limited. Although it is within the range, it is not a preferable state in consideration of the influence on other adjacent devices under test. According to the wafer test system 10 according to the present embodiment, a device under test whose power supply or signal supply is cut off is excluded from the test target, but adverse effects on the adjacent device under test can be eliminated. .

  In addition, this invention is not limited to the said embodiment, A various deformation | transformation is possible. For example, in the above-described embodiment, both the voltage and current value of the power source supplied to the device under test are monitored to detect the power source abnormality. However, the method for detecting the power source abnormality is limited to this. Is not something For example, only the voltage of the power source supplied to the device under test may be monitored, or only the current value of the power source supplied to the device under test may be monitored.

  In the above-described embodiment, both the power supply supplied to the output drivers DR80-1 to DR80-m that supply signals to the device under test and the voltage of the signal output from the output drivers DR80-1 to DR80-m. However, the method for detecting the signal abnormality is not limited to this. For example, only the power supplied to the output drivers DR80-1 to DR80-m that supply signals to the device under test may be monitored, or the signals output from the output drivers DR80-1 to DR80-m may be monitored. Only the voltage may be monitored.

  Furthermore, in the above-described embodiment, the overcurrent overvoltage detection circuit 70 for detecting a power supply abnormality is provided in the power supply circuit 62, but the position where the overcurrent overvoltage detection circuit 70 is provided can be arbitrarily changed. Similarly, in the above-described embodiment, the abnormal signal detection circuit 80 for detecting a signal abnormality is provided in the signal supply circuit 64, but the position where the abnormal signal detection circuit 80 is provided can be arbitrarily changed.

  In the above-described embodiment, the case where the tester device 30 can test a plurality of devices under test has been described as an example. However, when the tester device 30 tests the devices under test one by one, The present invention can be applied.

It is a front view for demonstrating the whole structure of the wafer test system which concerns on this embodiment. It is a block diagram for demonstrating an example of the connection relation between the test head unit which concerns on this embodiment, and a prober apparatus. It is a block diagram for demonstrating an example of the circuit structure of the power supply and signal supply circuit which concerns on this embodiment. It is a circuit diagram for demonstrating an example of the circuit structure of the overcurrent overvoltage detection circuit which concerns on this embodiment. It is a circuit diagram for demonstrating an example of the circuit structure of the abnormal signal detection circuit which concerns on this embodiment. It is a figure which shows an example of the waveform of the input signal input into the output driver of the abnormal signal detection circuit of FIG. 5, and the output signal output from this output driver.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Wafer test system 20 Prober apparatus 21 Arm support unit 30 Tester apparatus 32 Test head unit 34 Cable 36 Control unit 60 Power supply / signal supply circuit 62 Power supply circuit 64 Signal supply circuit 66 Protection circuit SG1 Overcurrent detection signal SG2 Overvoltage detection signal SG3 Level abnormality detection signal SG4 Overcurrent detection signal

Claims (5)

A tester apparatus for testing a device under test formed on a wafer while applying thermal stress to the wafer and performing wafer-level burn-in ,
A power supply abnormality detection circuit that monitors power supplied to the device under test formed on the wafer and detects whether or not the power supply is abnormal;
A signal abnormality detection circuit that monitors a signal supplied to the device under test formed on the wafer and detects whether or not the signal is abnormal;
When the power supply abnormality detection circuit does not detect a power supply abnormality, and when the signal abnormality detection circuit does not detect a signal abnormality, supply power to the device under test and supply a signal. A protection circuit;
With
The power supply abnormality detection circuit monitors the voltage and current of a power supply to be supplied to the device under test, and when at least one of the voltage of the power supply and the current value of the power supply is higher than a predetermined reference value, the power supply It is determined that an abnormality has been detected,
The signal abnormality detection circuit monitors the current of the driver power supply supplied to the output driver of the signal supplied to the device under test, and detects a signal abnormality when the current value of the driver power supply is higher than a predetermined reference value. As well as
The signal abnormality detection circuit further monitors the voltage of the signal supplied to the device under test. When the logic level of the expected value of the signal is high, the voltage of the signal is higher than the reference voltage on the high level side. When it is low, it is determined that a signal abnormality is detected, and when the logic level of the expected value of the signal is low, the signal abnormality is detected when the voltage of the signal is higher than the low-level reference voltage. Judge that it was detected,
A tester device characterized by that. A power supply circuit for supplying power to the device under test;
A signal supply circuit for supplying a signal to the device under test;
In addition,
The power abnormality detection circuit is provided in the power supply circuit,
The signal abnormality detection circuit is provided in the signal supply circuit,
The tester device according to claim 1. The tester apparatus can simultaneously test a plurality of devices under test formed on a wafer,
The power supply abnormality detection circuit monitors the power supply for each device under test, the signal abnormality detection circuit monitors the signal for each signal of each device under test,
The protection circuit supplies power and signals to a device under test in which the power supply abnormality detection circuit does not detect power supply abnormality and does not detect signal abnormality.
The tester device according to claim 1 or 2, wherein   In the signal abnormality detection circuit, the current of the driver power supply supplied to the output driver is monitored by a first overcurrent detection circuit for detecting an overcurrent of the power supply supplied to the high level side of the output driver, 4. The tester device according to claim 1, wherein the tester device is operated by a second overcurrent detection circuit that detects an overcurrent of a power source supplied to the low level side of the power supply. A tester apparatus control method for testing a device under test formed on a wafer while applying thermal stress to the wafer and performing wafer level burn-in ,
A power supply abnormality detection step for monitoring the power supplied to the device under test formed on the wafer and detecting whether there is a power supply abnormality;
A signal abnormality detection step of monitoring a signal supplied to the device under test formed on the wafer and detecting whether or not there is a signal abnormality;
A power supply signal supplying step of supplying power and signals to the device under test when the power supply abnormality is not detected and the signal abnormality is not detected;
With
In the power supply abnormality detection step, the power supply voltage and current supplied to the device under test are monitored, and when at least one of the power supply voltage and the power supply current value is higher than a predetermined reference value, It is determined that an abnormality has been detected,
In the signal abnormality detection step, the current of the driver power supply supplied to the output driver of the signal supplied to the device under test is monitored, and if the current value of the driver power supply is higher than a predetermined reference value, the signal abnormality is detected. As well as
In the signal abnormality detection step, the voltage of the signal supplied to the device under test is further monitored, and when the logic level of the expected value of the signal is high, the voltage of the signal is higher than the high level side reference voltage. When it is low, it is determined that a signal abnormality is detected, and when the logic level of the expected value of the signal is low, the signal abnormality is detected when the voltage of the signal is higher than the low-level reference voltage. Judge that it was detected,
A tester apparatus control method characterized by the above.

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