JP2007333387A - Semiconductor inspection system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor inspection system which can detect all abnormalities occurring at various parts across the inspection system, including an inspection board and inspection circuit elements at the periphery of interface. <P>SOLUTION: An abnormality detection circuit 106 is placed on the same substrate 107 as a probe card substrate 101 of a probe card 102, which is installed during a normal inspection of a semiconductor chip to constitute a circuit abnormality detection system 108. The circuit abnormality detection system 108, as a substitute for the probe card 102 installed during the normal inspection, is installed by the same substrate 107 on a probe card mounting section of the pogo ring 104, thereby expanding an abnormality detection program and a circuit abnormality detection function, which have mainly been for a semiconductor tester, to a leading-edge part of the inspection system and detecting malfunctions in the inspection board 103 and the inspection circuit on the periphery of the pogo ring 104. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor inspection apparatus for testing and inspecting electrical characteristics of semiconductor chips on a semiconductor wafer, for example.

  2. Description of the Related Art Conventionally, in a manufacturing process of a semiconductor device such as an LSI, for example, a semiconductor inspection apparatus widely used for inspecting a semiconductor device which is a semiconductor device completed as a semiconductor chip or a product on a semiconductor wafer is included in the apparatus. It has an enormous number of circuits and is configured to be able to perform an inspection test on the electrical characteristics of a semiconductor chip or semiconductor device to be inspected.

  Therefore, for example, when an inspection test of a semiconductor chip or a semiconductor device is performed, a system diagnosis program is executed to check whether or not the function of the semiconductor inspection apparatus itself is normal.

  In such system diagnosis, when system diagnosis related to the test head is performed, the semiconductor inspection apparatus is configured to be performed by mounting a diagnostic board dedicated to system diagnosis on the test head.

The conventional semiconductor inspection apparatus as described above (see, for example, Patent Document 1) will be described below with reference to the drawings.
FIG. 9 is a cross-sectional view showing a structure around a test head when system diagnosis is executed in a conventional semiconductor inspection apparatus. In FIG. 9, 910 is a probe card type diagnostic card, 940 is a test head, 960 is a wafer mother board, 962 is an inspection board, 963 is a circuit abnormality detection diagnostic circuit section, 964 is a coaxial cable, and 966 is a probing Assembly 969 is a pogo pin.

The operation of the semiconductor inspection apparatus as described above will be described below.
As shown in FIG. 9, the probe card type diagnostic card 910 having the same fitting shape as the probe card at the open end on the probe card side with the intermediary circuit structure mounted, and the probe card type diagnostic card 910 A circuit means for detecting a circuit abnormality detection circuit 963 of the semiconductor inspection apparatus is used. As a result, the semiconductor test has an intermediary circuit structure that provides a one-to-one electrical intermediary connection between the test head 940 and the probe card, and is connected to the wafer prober to electrically test semiconductor chips on the wafer. In the apparatus, automatic system diagnosis can be performed with the wafer mother board mounted.

  The intermediary circuit structure described above is all of the circuit structures that have a one-to-one electrical intermediary connection between the test head 940 and the probe card. An example is a wafer mother board 960. Further, there is a configuration means for adding a unique board identification ID code to the probe card type diagnostic card 910 and adding a circuit that can read the code to the probe card type diagnostic card 910. As a result, the system can read the board identification ID code, confirm the mounting of the probe card type diagnostic card 910, and execute the system diagnostic program corresponding to the probe card type diagnostic card 910.

As described above, in the system diagnosis of the wafer mother board 960 connected to the wafer prober, the automatic system diagnosis including the wafer mother board with the wafer mother board 960 mounted is realized. Yes.
Japanese Patent Laid-Open No. 10-150082

  However, in the conventional semiconductor inspection apparatus as described above, the main subject of abnormality detection is a semiconductor tester (semiconductor tester), including abnormality diagnosis and wafer mother board 960 connected to the wafer prober. The abnormality detection means for executing the overall abnormality diagnosis has a configuration, but each of the inspection circuit and the inspection circuit elements in the interface peripheral portion existing between the semiconductor tester and the wafer mother board 960 is provided. There is a problem in that it is impossible to individually detect all malfunctions occurring in each part of the entire inspection apparatus including elements.

  The present invention solves the above-mentioned conventional problems, and detects all abnormal defects occurring in each part of the entire inspection apparatus including the inspection circuit elements in the peripheral part of the inspection board and the interface as defects of the inspection apparatus. Provided is a semiconductor inspection apparatus capable of performing the above.

  In order to solve the above-described problem, in the semiconductor inspection apparatus according to claim 1 of the present invention, a plurality of probe needles that are in electrical contact with the external connection terminals of the semiconductor chip are inspected on the probe card substrate in order to inspect the semiconductor chip. An attached probe card; a semiconductor tester for testing electrical characteristics of the semiconductor chip to inspect the semiconductor chip; and the plurality of probe needles are electrically connected through the probe card board; An inspection circuit for processing and transmitting a test signal of the semiconductor chip to and from a semiconductor tester, and through the inspection circuit in a state where the plurality of probe needles are in electrical contact with external connection terminals of the semiconductor chip. The semiconductor chip is detected based on a test result obtained by the semiconductor tester obtained by processing transmission of the test signal. In the semiconductor inspection apparatus, a circuit abnormality in which an abnormality detection circuit for detecting an operation abnormality in the inspection circuit is formed on the same substrate as the probe card substrate, instead of the probe card, in the probe card mounting portion A detection device is attached and the inspection circuit is tested.

  A semiconductor inspection apparatus according to claim 2 of the present invention is the semiconductor inspection apparatus according to claim 1, wherein the time determination circuit transmits and processes the time signal as a test signal for the semiconductor chip. A plurality of operation abnormality detection circuits including a time determination operation abnormality detection circuit that detects an operation abnormality of the time determination circuit as an operation abnormality in the inspection circuit. And an abnormal operation of the time determination circuit in the inspection circuit is detected.

  A semiconductor inspection apparatus according to claim 3 of the present invention is the semiconductor inspection apparatus according to claim 1, wherein the inspection circuit uses the relay circuit to process and transmit a relay control signal as a test signal for the semiconductor chip. A plurality of signal processing transmission circuits including a response circuit, and the abnormality detection circuit includes a plurality of relay transient response operation abnormality detection circuits that detect an operation abnormality of the relay transient response circuit as an operation abnormality in the inspection circuit. It comprises an operation abnormality detection circuit, and detects an operation abnormality of the relay transient response circuit in the inspection circuit.

  A semiconductor inspection apparatus according to a fourth aspect of the present invention is the semiconductor inspection apparatus according to the first aspect, wherein the inspection power is supplied to the inspection circuit as a test signal for the semiconductor chip. A plurality of operation abnormality detection circuits including a power supply operation abnormality detection circuit that detects an operation abnormality of the power supply circuit as an operation abnormality in the inspection circuit. And an abnormal operation of the power supply circuit in the inspection circuit is detected.

  The semiconductor inspection apparatus according to claim 5 of the present invention is the semiconductor inspection apparatus according to claim 1, wherein the supply circuit processes and transmits the supply signal as a test signal for the semiconductor chip. A plurality of operation abnormality detection circuits including a signal supply operation abnormality detection circuit that detects an operation abnormality of the supply signal circuit as an operation abnormality in the inspection circuit. And an abnormal operation of the supply signal circuit in the inspection circuit is detected.

  According to a sixth aspect of the present invention, there is provided the semiconductor inspection apparatus, wherein a plurality of probe needles that are in electrical contact with the respective external connection terminals of the plurality of semiconductor chips in order to simultaneously inspect the plurality of semiconductor chips, A probe card attached to the semiconductor chip, a semiconductor tester for simultaneously testing electrical characteristics of the plurality of semiconductor chips to simultaneously inspect the plurality of semiconductor chips, and the plurality of probe needles electrically connected through the probe card substrate. A plurality of inspection circuits that are connected and process and transmit test signals to each of the plurality of semiconductor chips between the probe card substrate and the semiconductor tester; The test chip is electrically connected to each external connection terminal of the semiconductor chip through the plurality of inspection circuits. In a semiconductor inspection apparatus that simultaneously inspects the plurality of semiconductor chips based on a test result obtained by the semiconductor tester obtained by processing signal transmission, in the probe card mounting portion, instead of the probe card, A configuration in which a plurality of abnormality detection circuits for detecting respective operation abnormalities in a plurality of inspection circuits are formed on the same substrate as the probe card substrate is attached, and the plurality of inspection circuits are tested. It is characterized by that.

  As described above, according to the present invention, a circuit abnormality detection device in which an abnormality detection circuit is arranged on the same substrate of a probe card, instead of a probe card to be mounted at the time of a normal inspection of a semiconductor chip, on a probe card mounting portion By installing the card on the same board, the abnormality detection program and circuit abnormality detection function, which were mainly semiconductor testers, are expanded to the most advanced part of the inspection equipment. It is also possible to detect an abnormal operation of the inspection board and the inspection circuit in the periphery of the interface existing between the two.

  As described above, it is possible to detect all abnormalities occurring in each part of the entire inspection apparatus including the inspection circuit elements in the inspection board and the interface peripheral part, and wasteful operation of the inspection apparatus during the occurrence of abnormality is possible. It can be greatly reduced, and a unified abnormality detection method can be unified, so that abnormality detection occurring in the inspection apparatus can be efficiently detected over the entire inspection apparatus.

  As a result, the reliability of the semiconductor inspection apparatus as a product can be greatly improved, and the cost of the semiconductor inspection apparatus can be reduced.

Hereinafter, a semiconductor inspection apparatus showing an embodiment of the present invention will be specifically described with reference to the drawings.
FIG. 1 is a sectional view showing the structure of the semiconductor inspection apparatus according to the present embodiment. FIG. 2 is a block diagram showing the configuration of the semiconductor inspection apparatus of the present embodiment. In the semiconductor inspection apparatus according to the present embodiment, as shown in FIGS. 1 and 2, for example, in a normal inspection for inspecting the quality of a semiconductor chip (not shown) on a wafer, the external connection terminals of the semiconductor chip are electrically connected. A probe card 102 in which a plurality of probe needles 100 that can be contacted are attached to a probe card substrate 101, and a semiconductor tester (semiconductor) that tests the electrical characteristics of the semiconductor chip according to a built-in software program for normal inspection of the semiconductor chip The tester 200 and a plurality of probe needles 100 are electrically connected through the probe card substrate 101, and are provided in the periphery of the inspection board 103 and the interface (pogo ring) 104 between the probe card substrate 101 and the semiconductor tester 200. An inspection circuit 201 for processing and transmitting the test signal of In the normal inspection of the semiconductor chip, the test results obtained by the semiconductor tester 200 obtained by transmitting the test signal through the inspection circuit 201 in a state where the plurality of probe needles 100 are in electrical contact with the external connection terminals of the semiconductor chip. Based on the above, the electrical quality of the semiconductor chip is inspected.

  Further, when testing for the presence or absence of abnormal operation of the inspection circuit 201 configured in the periphery of the inspection board 103 and the interface (pogo ring) 104, the probe card mounting portion of the interface (pogo ring) 104 is connected to the probe card when inspecting the semiconductor chip. Instead of the probe card 102 mounted via the folder unit 105, a circuit abnormality detection device 108 in which an abnormality detection circuit 106 for detecting an operation abnormality in the inspection circuit 201 is formed on the same substrate 107 as the probe card substrate is attached. It is configured as follows.

  In addition, the inspection circuit 201 provided in the periphery of the inspection board 103 and the interface (pogo ring) 104 includes a plurality of signal processing transmission circuits. As these signal processing transmission circuits, for example, test signals for semiconductor chips are used here. A supply current circuit 202 that processes and transmits a current signal supplied to a specific external connection terminal of the semiconductor chip, and a time determination circuit 203 that processes and transmits a time signal supplied to the specific external connection terminal of the semiconductor chip as a test signal for the semiconductor chip. A relay transient response circuit 204 for processing and transmitting a relay control signal to be supplied to a specific external connection terminal of the semiconductor chip as a test signal for the semiconductor chip, and to a specific external connection terminal of the semiconductor chip as a test signal for the semiconductor chip A power supply circuit 205 for processing and transmitting the power supply, and a semiconductor chip test A supply signal circuit 206 which processes transmit supply signal supplied to the particular external connection terminals of the semiconductor chip is provided as a use signal through the connector 1 to n.

  The abnormality detection circuit 106 of the circuit abnormality detection device 108 includes a plurality of operation abnormality detection circuits. As these operation abnormality detection circuits, here, for example, the operation of the supply current circuit 202 as an operation abnormality in the inspection circuit 201 is performed. A resistor 207 as a current supply operation abnormality detection circuit for detecting an abnormality, and an oscillation circuit 208 as a time determination operation abnormality detection circuit for detecting an operation abnormality of the time determination circuit 203 as an operation abnormality in the inspection circuit 201; , A signal generator 209 as a relay transient response operation abnormality detection circuit for detecting an operation abnormality of the relay transient response circuit 204 as an operation abnormality in the inspection circuit 201, and an operation abnormality of the power supply circuit 205 as an operation abnormality in the inspection circuit 201. Connector 210 as a power supply operation abnormality detection circuit for detecting A judging circuit 211 as a signal supply operation abnormality detection circuit for detecting an abnormal operation due to incomplete contact or the like in the connector 1~n supply signal circuit 206 is provided as the abnormal operation in 査回 path 201.

A configuration example of each circuit included in the abnormality detection circuit 106 will be described below.
3 to 7 are circuit diagrams showing the detailed configuration of each circuit of the abnormality detection circuit in the semiconductor inspection apparatus of the present embodiment, and FIG. 3 is a circuit diagram showing the configuration of the resistor in the abnormality detection circuit. 4 is a circuit diagram showing a configuration of an oscillation circuit in the abnormality detection circuit, FIG. 5 is a circuit diagram showing a configuration of a signal generator in the abnormality detection circuit, and FIG. 6 is a connector in the abnormality detection circuit. FIG. 7 is a circuit diagram showing the configuration of the determination circuit and the display in the abnormality detection circuit.

  In the resistor 207 shown in FIG. 3, 300 and 310 are resistance elements 1 kΩ (here, 13 are provided), and 301 and 311 are resistance elements 2 kΩ (here, 4 are provided). 2 shows a configuration example in which two sets (n = 2) of inspection circuits 201 are provided on the inspection board 103 so that two semiconductor chips can be inspected simultaneously. In this configuration example, each of the resistance elements One end is commonly connected to the ground potential, the other end is connected to the 1 kΩ side connection terminals 302 and 312 for the resistance elements 1 kΩ 300 and 310, and the 2 kΩ side connection terminals 303 and 313 for the resistance elements 2 kΩ 301 and 311, respectively. Has been.

  It should be noted that two resistance values such as the resistance element 1 kΩ 300 and the resistance element 2 kΩ 301 are provided in one resistor (for example, n = 1) 207, and different currents flow with respect to the same applied voltage. By using this, one contact (for example, a contact) is connected to, for example, the resistance element 1 kΩ 300 and the other contact (for example, b contact) is connected to, for example, the resistance element 2 kΩ 301 by a relay or the like. This is to specify the contact point.

  The oscillation circuit 208 shown in FIG. 4 is a general rectangular wave oscillation circuit using a timer IC. 400 is a timer IC, 401 is a 12v power supply, and supplies a predetermined constant voltage (here, 5v) to the timer IC 400. Regulator, 402 is a power supply terminal for applying 12v power to the input side of the regulator 401, 403 and 413 are switching transistors that are switched by a rectangular wave from the timer IC 400, and 404 and 414 are grounded with one end connected to the ground potential Resistors, 405 and 415 are output terminals, and 406 and 416 are switching switches that are switched to one of the switching transistors 403 and 413 and the ground resistors 404 and 414 and connected to the output terminals 405 and 415, respectively.

  The 12v power source is supplied from the semiconductor tester 200 side, and the regulator 401 stabilizes the supply voltage from the semiconductor tester 200 side with a voltage lower than that voltage.

  In the signal generator 209 shown in FIG. 5, 501 is a logic IC (FPGA, CPLD, etc.), 502 is a reference clock, 503 is a relay control signal, 504 is a relay operation time (1), and 505 is a signal generation waiting time (1). , 506 is a pattern signal (1), 507 is a capture signal (1), 508 is a relay operation time (2), 509 is a capture signal (2), 510 is a relay operation time (3), and 511 is a signal generation waiting time ( 2), 512 is a pattern signal (2), 513 is a capture signal (3), 514 is a relay operation time (4), 515 is a pattern signal (3), and 516 is a capture signal (4).

  In the connector 210 shown in FIG. 6, 600 is a receiving side terminal that receives supply power of each potential of, for example, + 5v, −5v, + 12v, −12v, and ground potential (GND) from the semiconductor tester 200, and 601 is, for example, + 5v, − 5V, + 12v, −12v, a return side terminal that returns the voltage of each potential of the ground potential (GND) to the semiconductor tester 200, 602 is, for example, + 5v, −5v, + 12v, − from the semiconductor tester 200 received by the reception side terminal 600 12v is a return wiring that returns the voltage of each potential of the ground potential (GND) to the return terminal 601 as it is at 1: 1.

  In the determination circuit 211 shown in FIG. 7, 700 is a determination signal, 701 is a display, 702 is an LED, 703 is an AND circuit, 704 is a signal (1), 705 is a signal (2), and 706 is a signal (n). .

The operation of the semiconductor inspection apparatus configured as described above will be described below.
For example, when testing whether there is an abnormal operation of the inspection circuit 201 formed in the periphery of the inspection board 103 and the interface (pogo ring) 104 before the normal inspection of the semiconductor chip, first, as shown in FIG. (Pogoring) Anomaly detection circuit 106 for detecting an operation abnormality in the inspection circuit 201 instead of the probe card 102 attached to the probe card mounting portion 104 of the semiconductor card via the probe card folder portion 105 during the normal inspection of the semiconductor chip. Is mounted on the same substrate 107 as the probe card substrate.

  Then, as shown in FIG. 2, the resistor 207 causes an operation caused by a disconnection of a resistor in the supply current circuit 202, a contact failure of a relay, a disconnection of a relay winding, a short circuit between relay windings, a short circuit between wirings, or the like. Detect anomalies. For example, in the resistor 207 shown in FIG. 3, a predetermined voltage set in advance from the semiconductor tester 200 side is applied to the corresponding 1 kΩ side connection terminal 302 and 2 kΩ side connection terminal 303 through each circuit of the supply current circuit 202, In addition, each current flowing out from the semiconductor tester 200 side to each circuit of the supply current circuit 202 is measured on the semiconductor tester 200 side itself, and each current thus measured is compared with a specified current value. Thus, the above-described abnormal operation of the supply current circuit 202 can be detected in the semiconductor tester 200.

  Further, the oscillation circuit 208 detects an abnormal operation due to a time setting failure or a circuit failure of the time determination circuit 203. For example, in the oscillation circuit 208 shown in FIG. 4, for any output terminal 405, the output terminal 405 is first connected to the ground resistor 404 side for a preset period by switching the changeover switch 406, and then the changeover switch 406. When the output terminal 405 is switched to the state connected to the switching transistor 403 side, and after the preset period from that time, the first output terminal 405 is further returned to the state connected to the grounding resistor 404 side after a preset period. In addition, the number of rectangular wave pulses from the timer IC 400 during the period in which the output terminal 405 is connected to the switching transistor 403 side is counted by the time determination circuit 203 connected to the output terminal 405. Judgment time and the result On the semiconductor tester 200 side, the determination time by the time determination circuit 203 is compared with the time of a preset period based on the switching timing of the changeover switch 406 preset in the oscillation circuit 208, and this operation is performed. By executing for each time determination circuit connected to each output terminal, the above-described operation abnormality of the time determination circuit 203 can be detected in the semiconductor tester 200.

  In addition, the signal generator 209 causes malfunctions due to relay failure in the relay transient response circuit 204, relay winding disconnection, relay winding line short, relay control signal line disconnection, line short, etc. To detect.

Hereinafter, an operation example shown in FIG. 5B will be described with respect to the operation detecting operation abnormality in the relay excessive response circuit 204 using the signal generator 209 shown in FIG.
As shown in FIG. 5A, a logic IC 501 that can freely generate a signal such as an FPGA or CPLD receives a relay control signal and generates a reference clock 502 from a clock generator 502. A pattern signal is generated based on the above.

Next, an operation example of the signal generator 209 will be described with reference to FIG. First, the abnormality detection operation at the time of relay ON operation will be described.
When the signal generator 209 receives the relay control signal 503 from the semiconductor tester 200, the signal generator 209 outputs the pattern signal (1) 506 after the waiting time of the specified operation (ON) time of the relay (signal generation waiting time (1) 505). Output. The semiconductor tester 200 takes in the pattern signal (1) 506 after the waiting time (1) of the signal generation waiting time (1) 505.

  When the relay operation is normal, the relay operation time (1) 504 is within the signal generation waiting time (1) 505, and therefore the same capture signal (1) 507 as the pattern signal (1) 506 output by the signal generator 209 is obtained. Is taken in by the semiconductor tester 200.

  In the semiconductor tester 200, the signal pattern of the pattern signal (1) 506 generated by the signal generator 209 is held in advance, and the captured signal (1) 507 is compared with the previously held pattern signal (1) 506 to obtain a signal. Can be confirmed to be the same, and in that case, it is possible to confirm that the relay is operating normally.

  When the relay operation is abnormal, the relay operation time (2) 508 becomes longer than the signal generation waiting time (1) 505, and the pattern signal (1) 506 generated by the signal generator 209 is the capture signal (2) 509. The different test signals (2) 509 are acquired by the semiconductor tester 200. The semiconductor tester 200 can confirm that the signals are not the same by comparing the pattern signal (1) 506 and the capture signal (2) 509, and confirm that the relay is operating abnormally in that case. It is possible.

Next, an abnormality detection operation at the time of relay OFF operation will be described.
When the signal generator 209 receives the relay control signal 503 from the semiconductor tester 200, the signal generator 209 outputs the pattern signal (2) 512 after the waiting time of the specified operation OFF time of the relay (signal generation waiting time (2) 511). To do. The semiconductor tester 200 takes in the pattern signal (2) 512 after the signal generation waiting time (2) 511 waiting time.

  When the relay operation is normal, since the relay operation time (3) 510 is within the signal generation waiting time (2) 511, the capture signal (3) 513 does not include any signal. The semiconductor tester 200 can confirm that the relay is operating normally by confirming that there is no signal in the capture signal (3) 513.

  When the relay operation is abnormal, the relay operation time (4) 514 is longer than the signal generation waiting time (2) 511, and the capture signal (4) 516 includes some signal. The semiconductor tester 200 can confirm that the relay is operating abnormally by confirming that there is any signal in the capture signal (4) 516.

As described above, the operation abnormality of the relay transient response circuit 204 can be detected in the semiconductor tester 200.
Further, the connector 210 detects an abnormal operation due to disconnection of the power supply circuit 205, line-to-line short, or the like. For example, in the connector 210 shown in FIG. 6, for example, + 5v, −5v, + 12v, −12v, and ground potential (GND) voltages supplied to the semiconductor chip during normal inspection from the semiconductor tester 200 side are supplied to the supply power circuit 205. Are applied to the corresponding receiving-side terminal 600 through the respective circuits, and at that time, each voltage returned from the return-side terminal 601 to the semiconductor tester 200 side through the other circuits of the power supply circuit 205 is returned to the semiconductor tester 200 by the return wiring 602. 200, the operation abnormality of the power supply circuit 205 is detected in the semiconductor tester 200 by comparing each voltage measured in this way with each voltage value output to each circuit of the power supply circuit 205. Can be detected.

  Further, the determination circuit 211 detects an abnormal operation due to incomplete contact or short between lines in the connectors 1 to n of the supply signal circuit 206 and displays the detection result on the display 212 constituted by LEDs or the like.

  For example, in the determination circuit 211 shown in FIG. 7, the signal (1) 704, the signal (2) 705, and the signal (n) 706 are all output on the AND circuit 703 only when the determination signal 700 is ON, and the LED 702 is turned on. Thus, by functioning as the display 701 (212) indicating that there is no problem in mounting, the semiconductor tester 200 can detect the abnormal operation of the supply signal circuit 206.

Next, another configuration of the semiconductor inspection apparatus according to the present embodiment will be described. The semiconductor inspection apparatus shown in FIGS. 1 and 2 can also be configured as follows.
FIG. 8 is a block diagram showing another configuration of the semiconductor inspection apparatus of the present embodiment. In this semiconductor inspection apparatus, as shown in FIG. 1 and FIG. 8, for example, a plurality of semiconductor chips in a normal inspection for simultaneously inspecting the quality of a plurality (n> 2) of semiconductor chips (not shown) on a wafer. A probe card 102 having a plurality of probe needles 100 that are in electrical contact with the respective external connection terminals are attached to the probe card substrate 101, and electrical characteristics of the plurality of semiconductor chips for simultaneous inspection of the plurality of semiconductor chips. A semiconductor tester (semiconductor tester) 200 that tests simultaneously according to a built-in software program and a plurality of probe needles 100 are electrically connected through a probe card substrate 101, and an inspection board 800 between the probe card substrate 101 and the semiconductor tester 200. And interface (pogo ring) 104 A plurality of (n> 2) inspection circuits 801 that process and transmit test signals to each of the plurality of semiconductor chips, and the plurality of probe needles 100 are respectively connected to the plurality of semiconductor chips during normal inspection of the semiconductor chips. A configuration in which a plurality of semiconductor chips are simultaneously inspected based on a test result obtained by the semiconductor tester 200 obtained by transmitting a test signal through a plurality of inspection circuits 801 while being in electrical contact with the external connection terminals. Has been.

  Further, when testing whether or not there is an abnormal operation of the plurality of inspection circuits 801 formed in the periphery of the inspection board 800 and the interface (pogo ring) 104, an inspection of the semiconductor chip is performed on the probe card mounting portion of the interface (pogo ring) 104. Sometimes, instead of the probe card 102 mounted via the probe card folder unit 105, a plurality (n> 2) of abnormality detection circuits 802 for detecting respective operation abnormalities in the plurality of inspection circuits 801 are connected to the probe card substrate. A circuit abnormality detection device 804 formed on the same substrate 803 is attached.

  In FIG. 8, each of the plurality of (first to nth) inspection circuits 801 corresponds to the inspection circuit 201 shown in FIG. 2, and each of the plurality of (first to nth) abnormality detection circuits 802 This corresponds to the abnormality detection circuit 106 shown in FIG.

  By configuring as described above, for example, a plurality of semiconductor chips on a wafer are configured on the periphery of an inspection board and interface (pogo ring) of a semiconductor inspection apparatus configured to inspect their quality at the same time. With respect to the entire semiconductor inspection apparatus including the inspection circuit, it is possible to test whether or not there is an abnormal operation of each part.

  According to the configuration of the present embodiment as described above, a circuit in which an anomaly detection circuit is arranged on the same substrate as the probe card, instead of the probe card that is attached to the probe card mounting portion of the pogo ring during the normal inspection of the semiconductor chip. By installing the anomaly detection device on the same substrate as the probe card, the anomaly detection program and the circuit anomaly detection function, which were mainly semiconductor testers, are expanded to the most advanced part of the inspection device, and are used for semiconductor testers and wafers. It is also possible to detect an abnormal operation of the inspection board existing between the mother board and the inspection circuit around the pogo ring.

  Therefore, it is possible to detect all abnormalities that occur in each part of the inspection device including the inspection circuit elements in the inspection board and the periphery of the pogo ring. In addition, it is possible to unify the overall abnormality detection method, and to efficiently detect abnormality defects occurring in the inspection apparatus throughout the inspection apparatus.

As a result, the reliability of the semiconductor device as a product can be significantly improved, and the cost of the semiconductor device can be reduced.
In addition, the circuit abnormality detection device has an abnormality detection circuit arranged on the same substrate as the probe card substrate, and is attached to the probe card mounting portion of the pogo ring instead of the probe card to be mounted during normal inspection of the semiconductor chip. Therefore, the abnormality detection circuit of the circuit abnormality detection device can be mounted on an existing probe card substrate that has been used for a probe card that is conventionally mounted during normal inspection of a semiconductor chip. it can.

  In addition, according to the above, when testing for the presence or absence of an abnormal state of the semiconductor inspection apparatus, the abnormality detection circuit is placed on the same substrate as the probe card substrate from the probe card that is mounted for the normal inspection of the semiconductor chip. It is possible to replace the arranged circuit abnormality detection device quickly and easily.

  In addition, according to the above, when replacing the probe card that has been mounted for the normal inspection of the semiconductor chip with the circuit abnormality detection device in order to test the presence or absence of the abnormal state of the semiconductor inspection device, when the circuit abnormality detection device is mounted In addition, it is possible to eliminate the need to prepare a special dedicated jig such as an adapter for mounting the circuit abnormality detection device.

  The semiconductor inspection apparatus of the present invention is capable of detecting all of the abnormal defects occurring in the respective parts over the entire inspection apparatus including the inspection circuit elements of the inspection board and the interface peripheral portion as defects of the inspection apparatus. For example, the present invention can be applied to a semiconductor inspection apparatus for inspecting semiconductor chips on a semiconductor wafer.

Sectional drawing which shows the structure of the semiconductor inspection apparatus of embodiment of this invention The block diagram which shows the structure of the semiconductor inspection apparatus of the embodiment The circuit diagram which shows the detailed structure of the resistor of the circuit for abnormality detection in the semiconductor inspection apparatus of the embodiment The circuit diagram which shows the detailed structure of the oscillation circuit of the circuit for abnormality detection in the semiconductor inspection apparatus of the embodiment The circuit diagram which shows the detailed structure of the signal generator of the circuit for abnormality detection in the semiconductor inspection apparatus of the embodiment The circuit diagram which shows the detailed structure of the connector of the circuit for abnormality detection in the semiconductor inspection apparatus of the embodiment The circuit diagram which shows the detailed structure of the determination circuit of the circuit for abnormality detection in the semiconductor inspection apparatus of the embodiment, and a display The block diagram which shows the other structure of the semiconductor inspection apparatus of the embodiment Sectional drawing which shows the structure around a test head at the time of system diagnosis execution in the conventional semiconductor inspection equipment

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Probe needle 101 Probe card board 102 Probe card 103 Inspection board 104 Pogo ring 105 Probe card folder part 106 Abnormality detection circuit 107 Probe card same board 108 Circuit abnormality detection apparatus 200 Semiconductor tester (semiconductor tester)
201 Inspection Circuit 202 Supply Current Circuit 203 Time Determination Circuit 204 Relay Transient Response Circuit 205 Supply Power Circuit 206 Supply Signal Circuit 207 Resistor 208 Oscillation Circuit 209 Signal Generator 210 Connector 211 Determination Circuit 212 Display 300, 310 Resistive Element 1 kΩ
301, 311 Resistance element 2kΩ
302, 312 1 kΩ side connection terminal 303, 313 2 kΩ side connection terminal 400 Timer IC
401 Regulator 402 Power supply terminal 403, 413 Switching transistor 404, 414 Ground resistance 405, 415 Output terminal 406, 416 Changeover switch 501 Logic IC (FPGA, CPLD, etc.)
502 Reference clock 503 Relay control signal 504 Relay operation time (1)
505 Waiting time for signal generation (1)
506 Pattern signal (1)
507 Capture signal (1)
508 Relay operation time (2)
509 Capture signal (2)
510 Relay operation time (3)
511 Waiting time for signal generation (2)
512 Pattern signal (2)
513 Capture signal (3)
514 Relay operation time (4)
515 Pattern signal (3)
516 Capture signal (4)
600 Reception side terminal 601 Reply side terminal 602 Return wiring 700 Determination signal 701 Display 702 LED
703 AND circuit 704 Signal (1)
705 signal (2)
706 Signal (n)
800 Inspection Board 801 1st to nth Inspection Circuit 802 1st to nth Abnormality Detection Circuit 803 Probe Card Same Board 804 Circuit Abnormality Detection Device 910 Probe Card Type Diagnosis Card 940 Test Head 960 Wafer Mother Board 962 Inspection Board 963 Diagnostic circuit part for circuit abnormality detection 964 Coaxial cable 966 Probing assembly 969 Pogo pin

Claims (6)

A probe card in which a plurality of probe needles that are in electrical contact with external connection terminals of the semiconductor chip to inspect the semiconductor chip are attached to the probe card substrate;
A semiconductor tester for testing electrical characteristics of the semiconductor chip to inspect the semiconductor chip;
The plurality of probe needles are electrically connected through the probe card substrate, and have an inspection circuit that processes and transmits a test signal for the semiconductor chip between the probe card substrate and the semiconductor tester,
Based on a test result by the semiconductor tester obtained by processing transmission of the test signal through the inspection circuit in a state where the plurality of probe needles are in electrical contact with external connection terminals of the semiconductor chip, the semiconductor chip In semiconductor inspection equipment that inspects
In the probe card mounting part,
Instead of the probe card,
A circuit abnormality detection device in which an abnormality detection circuit for detecting an operation abnormality in the inspection circuit is formed on the same substrate as the probe card substrate is attached,
A semiconductor inspection apparatus configured to test the inspection circuit. The semiconductor inspection apparatus according to claim 1,
The inspection circuit includes a plurality of signal processing transmission circuits including a time determination circuit that processes and transmits a time signal as a test signal for the semiconductor chip,
The abnormality detection circuit is configured with a plurality of operation abnormality detection circuits including a time determination operation abnormality detection circuit that detects an operation abnormality of the time determination circuit as an operation abnormality in the inspection circuit,
A semiconductor inspection apparatus for detecting an operation abnormality of the time determination circuit in the inspection circuit. The semiconductor inspection apparatus according to claim 1,
The inspection circuit is constituted by a plurality of signal processing transmission circuits including a relay transient response circuit that processes and transmits a relay control signal as a test signal for the semiconductor chip,
The abnormality detection circuit is configured with a plurality of operation abnormality detection circuits including a relay transient response operation abnormality detection circuit that detects an operation abnormality of the relay transient response circuit as an operation abnormality in the inspection circuit,
A semiconductor inspection apparatus for detecting an operation abnormality of the relay transient response circuit in the inspection circuit. The semiconductor inspection apparatus according to claim 1,
The inspection circuit is constituted by a plurality of signal processing transmission circuits including a power supply circuit that processes and transmits a power supply as a test signal for the semiconductor chip,
The abnormality detection circuit comprises a plurality of operation abnormality detection circuits including a power supply operation abnormality detection circuit that detects an operation abnormality of the power supply circuit as an operation abnormality in the inspection circuit,
A semiconductor inspection apparatus for detecting an operation abnormality of the power supply circuit in the inspection circuit. The semiconductor inspection apparatus according to claim 1,
The inspection circuit is composed of a plurality of signal processing transmission circuits including a supply signal circuit that processes and transmits a supply signal as a test signal for the semiconductor chip,
The abnormality detection circuit comprises a plurality of operation abnormality detection circuits including a signal supply operation abnormality detection circuit that detects an operation abnormality of the supply signal circuit as an operation abnormality in the inspection circuit,
A semiconductor inspection apparatus for detecting an operation abnormality of the supply signal circuit in the inspection circuit. A probe card in which a plurality of probe needles that are in electrical contact with respective external connection terminals of the plurality of semiconductor chips in order to simultaneously inspect a plurality of semiconductor chips are attached to a probe card substrate;
A semiconductor tester for simultaneously testing the electrical characteristics of each of the plurality of semiconductor chips to simultaneously test the plurality of semiconductor chips;
A plurality of test circuits in which the plurality of probe needles are electrically connected through the probe card substrate and process and transmit test signals to each of the plurality of semiconductor chips between the probe card substrate and the semiconductor tester; Have
In the state where the plurality of probe needles are in electrical contact with the respective external connection terminals of the plurality of semiconductor chips, the test results obtained by the semiconductor tester obtained by processing transmission of the test signals through the plurality of inspection circuits. On the basis of the semiconductor inspection apparatus for simultaneously inspecting the plurality of semiconductor chips,
In the probe card mounting part,
Instead of the probe card,
Attach a circuit abnormality detection device in which a plurality of abnormality detection circuits for detecting respective operation abnormalities in the plurality of inspection circuits are formed on the same substrate as the probe card substrate,
A semiconductor inspection apparatus configured to test the plurality of inspection circuits.

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