JP4708723B2 - 半導体記憶装置 - Google Patents

半導体記憶装置 Download PDF

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Publication number
JP4708723B2
JP4708723B2 JP2004098463A JP2004098463A JP4708723B2 JP 4708723 B2 JP4708723 B2 JP 4708723B2 JP 2004098463 A JP2004098463 A JP 2004098463A JP 2004098463 A JP2004098463 A JP 2004098463A JP 4708723 B2 JP4708723 B2 JP 4708723B2
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JP
Japan
Prior art keywords
signal
address
latch
data
sense
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2004098463A
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English (en)
Japanese (ja)
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JP2005285230A (ja
JP2005285230A5 (enExample
Inventor
貴志 久保
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2004098463A priority Critical patent/JP4708723B2/ja
Priority to US11/072,274 priority patent/US7180824B2/en
Publication of JP2005285230A publication Critical patent/JP2005285230A/ja
Publication of JP2005285230A5 publication Critical patent/JP2005285230A5/ja
Application granted granted Critical
Publication of JP4708723B2 publication Critical patent/JP4708723B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Read Only Memory (AREA)
JP2004098463A 2004-03-30 2004-03-30 半導体記憶装置 Expired - Fee Related JP4708723B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2004098463A JP4708723B2 (ja) 2004-03-30 2004-03-30 半導体記憶装置
US11/072,274 US7180824B2 (en) 2004-03-30 2005-03-07 Semiconductor memory device with a page mode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004098463A JP4708723B2 (ja) 2004-03-30 2004-03-30 半導体記憶装置

Publications (3)

Publication Number Publication Date
JP2005285230A JP2005285230A (ja) 2005-10-13
JP2005285230A5 JP2005285230A5 (enExample) 2007-03-15
JP4708723B2 true JP4708723B2 (ja) 2011-06-22

Family

ID=35096125

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004098463A Expired - Fee Related JP4708723B2 (ja) 2004-03-30 2004-03-30 半導体記憶装置

Country Status (2)

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US (1) US7180824B2 (enExample)
JP (1) JP4708723B2 (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4823530B2 (ja) * 2005-01-24 2011-11-24 ルネサスエレクトロニクス株式会社 半導体記憶装置及び半導体記憶システム
US20090327535A1 (en) * 2008-06-30 2009-12-31 Liu Tz-Yi Adjustable read latency for memory device in page-mode access
US8023334B2 (en) * 2008-10-31 2011-09-20 Micron Technology, Inc. Program window adjust for memory cell signal line delay
KR101151177B1 (ko) * 2009-12-31 2012-06-01 에스케이하이닉스 주식회사 반도체 메모리 장치의 블럭 디코더
KR101701433B1 (ko) * 2010-06-25 2017-02-03 삼성전자주식회사 무선주파수인식 태그 및 그것의 신호 수신 방법
JP6097222B2 (ja) 2010-12-24 2017-03-15 マイクロン テクノロジー， インク． メモリ用連続的ページ読み出し
TWI570734B (zh) * 2012-06-07 2017-02-11 美光科技公司 記憶體連續頁面讀取
KR102346629B1 (ko) * 2014-12-05 2022-01-03 삼성전자주식회사 메모리 접근 제어 방법 및 장치
JP6359491B2 (ja) * 2015-06-12 2018-07-18 東芝メモリ株式会社 半導体記憶装置
CN108710814B (zh) * 2018-05-15 2021-06-08 华南理工大学 一种无芯片rfid标签的结构模式信号的自动搜索方法
CN111489773B (zh) * 2019-01-29 2023-04-07 合肥格易集成电路有限公司 一种读取数据的电路、非易失存储器以及读取数据的方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2696026B2 (ja) * 1991-11-21 1998-01-14 株式会社東芝 半導体記憶装置
KR950004854B1 (ko) 1992-10-08 1995-05-15 삼성전자 주식회사 반도체 메모리 장치
JPH1139863A (ja) 1997-07-18 1999-02-12 Sony Corp 半導体記憶装置
KR100274591B1 (ko) * 1997-07-29 2001-01-15 윤종용 동기형 버스트 매스크 롬 및 그것의 데이터 독출 방법
JP2001118395A (ja) * 1999-10-18 2001-04-27 Nec Corp 半導体記憶装置及びデータの読み出し方法
US6621761B2 (en) * 2000-05-31 2003-09-16 Advanced Micro Devices, Inc. Burst architecture for a flash memory
JP4190836B2 (ja) * 2002-08-30 2008-12-03 Ｎｅｃエレクトロニクス株式会社 半導体記憶装置

Also Published As

Publication number Publication date
US20050232068A1 (en) 2005-10-20
JP2005285230A (ja) 2005-10-13
US7180824B2 (en) 2007-02-20

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