JP4696616B2 - Display panel and manufacturing method thereof - Google Patents

Description

The invention, together with concerns the production process of de I spray panel, to display panel manufactured by the manufacturing method.

An active matrix drive type display panel, a semiconductor circuit, and other circuits are manufactured by patterning wiring on a substrate. As a wiring patterning method, a method of directly patterning a wiring by discharging metal fine particles dispersed in a solvent by an ink jet apparatus onto a substrate has been developed (see, for example, Patent Document 1 and Patent Document 2). Japanese Patent Application Laid-Open No. 2004-228561 describes that after a liquid repellent self-assembled film is formed on the entire surface of the substrate, ink is ejected toward the self-assembled film in order to suppress the spread of ink droplets that have landed on the substrate. Yes. Patent Document 2 describes that a fine groove is formed in a substrate by pressing a mold against the substrate, and conductive ink is injected into the groove. In any case, the solidified ink becomes the wiring.
JP 2003-80694 A JP 2004-356255 A

However, in the method described in Patent Document 1, since the metal fine particles dispersed in the solvent are in a liquid state, the shape becomes unstable as the thickness of the wiring becomes thick, and the width of the wire becomes larger as the cross section of the wiring approaches the lower bottom surface. It tends to be trapezoidal.
In the method described in Patent Document 2, if the substrate is soft, a groove can be formed on the surface of the substrate by transferring the processed mold. However, if the substrate is not flexible, the groove is not formed on the substrate. Can not form.

  Therefore, the present invention has been made in order to solve the above-described problems, and an object thereof is to make it possible to accurately form a wiring that is difficult to peel off.

In order to solve the above problems, in the method for manufacturing a display panel of the present invention,
The display panel is
A plurality of transistors;
A scanning line, a signal line, and a supply line connected to at least one of the plurality of transistors;
A protective insulating film and a planarizing film covering the transistor;
An insulating film formed on the planarizing film;
An adhesion layer formed on the insulating film;
A barrier rib formed on the adhesion layer that is thicker than each electrode of the transistor, the scanning line, the signal line, and the supply line;
An organic EL element having a subpixel electrode formed on the planarizing film, a counter electrode, and an organic EL layer provided between the subpixel electrode and the counter electrode;
With
Between the signal line and the partition, the protective insulating film, the planarization film , the insulating film and the adhesion layer are interposed,
Forming a resist having an opening through which the adhesion layer is exposed;
The metal nano-ink or metal particles coated on the adhesive layer thus exposed in the openings of the resist,
The resist is removed after drying after applying the metal nano ink,
After removing the resist, the partition walls are patterned by baking the metal nano ink ,
A liquid repellent conductive layer having liquid repellency and electrically conducting in the thickness direction is formed on the surface of the partition wall,
Applying an organic compound-containing liquid toward the subpixel electrode formed between the partition walls to form the organic EL layer,
The counter electrode is formed continuously on the liquid repellent conductive layer and the organic EL layer, and the partition and the counter electrode are electrically connected through the liquid repellent conductive layer. .
It is preferable to use silver nano ink as the metal nano ink .

It is preferable that the linear expansion coefficient of the adhesion layer is between the linear expansion coefficient of the wiring and the linear expansion coefficient of a member immediately below the adhesion layer.

  The display panel of the present invention is manufactured using the above manufacturing method.

  According to the present invention, since the metal nano ink or metal fine particles are applied to the openings of the resist, the applied metal nano ink or metal fine particles are blocked by the resist, and the spread of the applied metal nano ink or metal fine particles is prevented. can do. Therefore, the wiring can be patterned with high accuracy.

  The best mode for carrying out the present invention will be described below with reference to the drawings. However, although various technically preferable limitations for implementing the present invention are given to the embodiments described below, the scope of the invention is not limited to the following embodiments and illustrated examples.

[First Embodiment]
FIG. 1 is a diagram showing a process sequence of a wiring patterning method.

  As shown in FIG. 1A, a substrate 550 is first prepared. As the substrate 550, an insulating substrate such as a plastic substrate, a glass substrate, or a transparent substrate can be used. As the substrate 550, a transistor array panel in which one or a plurality of thin film transistors is formed for each pixel can be used.

  A thin film of chromium or the like is formed on the surface of the substrate 550 by a vapor deposition method (for example, PVD method such as sputtering), and the thin film is subjected to shape processing by a photolithography method and an etching method, so that FIG. As shown, an adhesion layer 551 is formed on the surface of the substrate 550. The adhesion layer 551 is formed when a wiring 554 described later has poor adhesion with the substrate 550 and may be peeled off. The adhesion layer 551 is formed on both the wiring 554 and the substrate 550. It is a film with excellent adhesion. The linear expansion coefficient of the adhesion layer 551 is preferably between the linear expansion coefficient of the substrate 550 and the linear expansion coefficient of the wiring 554.

  Next, as illustrated in FIG. 1C, a resist 552 is applied to the entire surface of the substrate 550, and the adhesion layer 551 is covered with the resist 552.

  Next, as shown in FIG. 1D, by exposing and developing the resist 552, a part of the resist 552 is removed, and the adhesion layer 551 is exposed. In addition, in order to expose the adhesion layer 551, when the resist 552 is a positive type, light is irradiated to a portion overlapping the adhesion layer 551. When the resist 552 is a negative type, other than the portion overlapping the adhesion layer 551. Irradiate light.

  Next, as illustrated in FIG. 1E, the metal nano ink 553 is ejected from the inkjet head 560 toward the adhesion layer 551. The metal nano-ink used here is a dispersion medium in which a plurality of metal fine particles having a diameter of about 5 to 9 nm including at least one of silver, gold, copper, aluminum, and an alloy mainly composed of these are coated with a coating agent. In particular, silver nano-ink is preferably used because it is dispersed and can be processed at a relatively low temperature in the baking step described later and has a relatively low specific resistance. The metal nano ink 553 may be mixed with a metal having a low melting point so that the metal nano ink 553 is easily melted when aggregated by firing. When the metal nano ink 553 is ejected from the ink jet head 560 while moving at least one of the ink jet head 560 and the substrate 550 along the surface of the substrate 550, the metal nano ink 553 is deposited on the line on the adhesion layer 551. While the metal nano ink 553 is applied on the adhesion layer 551, the substrate 550 is heated to several tens of degrees Celsius, so that the solvent in the metal nano ink 553 is evaporated and a dried wiring 554 is formed. Instead of ejecting the metal nano ink 553 as droplets using the inkjet head 560, the wiring 554 may be patterned by using a dispenser or applying the metal nano ink. Further, the wiring 554 may be patterned by applying a powder made of metal fine particles instead of applying the metal nano ink. In addition, dip film formation may be performed in which the adhesion layer 551 of the substrate 550 is attached to a tank filled with the metal nano ink 553 in the state of FIG.

  Even when the metal nano ink is difficult to adhere to the substrate 550, the wiring layer 551 made of the metal nano ink can be formed on the substrate 550 because the adhesion layer 551 having high adhesion to the metal nano ink is patterned. .

  Further, since the resist 552 is patterned and the metal nano ink is applied to the openings between the resists 552, the applied metal nano ink is blocked by the resist 552, and bleeding of the applied metal nano ink can be prevented. it can. Therefore, the wiring 554 can be patterned with high accuracy.

  Next, as shown in FIG. 1F, after the metal nano ink is applied, the resist 552 is removed by a removing liquid. However, since the wiring 554 is hardened, the wiring 554 is not removed.

  Next, the wiring 554 is baked at 180 ° C. to 220 ° C. for 30 minutes to 60 minutes, and a plurality of metal fine particles in the wiring 554 are fixed and aggregated to be completely solidified. As described above, since the metal nano ink is supported by the resist 552 and fits in the opening of the resist 552, even if the viscosity is low, the metal nano ink does not spread from the adhesion layer 551 and flow out onto the substrate 550. That is, since the width of the wiring 554 can be regulated by the opening width of the resist 552, it can be set to a predetermined length, and adjacent wirings 554 are not short-circuited.

[Second Embodiment]
The electroluminescent display panel in 2nd Embodiment is demonstrated. In the following description, the term electroluminescence is abbreviated as EL.

  FIG. 2 is a plan view of four pixels in the display area of the EL display panel. As shown in FIG. 2, in this EL display panel, red, blue and green sub-pixels P constitute one dot pixel, and such pixels are arranged in a matrix. When attention is paid to the arrangement in the horizontal direction, red subpixels P, blue subpixels P, and green subpixels P are repeatedly arranged in this order. When attention is paid to the arrangement in the vertical direction, the same colors are arranged in a line.

  In this EL display panel, a plurality of scanning lines X, signal lines Y, and supply lines Z are provided in order to output various signals to the subpixels P. The scanning lines X and the supply lines Z extend in the horizontal direction, and the signal lines Y extend in the vertical direction. Here, when the m-dot subpixels P are arranged in the horizontal direction (where m is a multiple of 3), the m signal lines Y are provided in parallel to each other, and the n-dot subpixels P are When arranged in the vertical direction (where n is an integer greater than or equal to 2), the n scanning lines X and the n supply lines Z are provided in parallel to each other. The scanning lines X and the supply lines Z are alternately arranged.

  FIG. 3 is an equivalent circuit diagram of the sub-pixel P. The subpixel P includes three n-channel transistors 21 to 23, a capacitor 24, and the organic EL element 20, and the color of the subpixel P is determined by the emission color of the organic EL element 20. Hereinafter, the transistor 21 is referred to as a switch transistor 21, the transistor 22 is referred to as a holding transistor 22, and the transistor 23 is referred to as a drive transistor 23.

  In the switch transistor 21, the source 21 s is conducted to the signal line Y, the drain 21 d is conducted to the anode of the organic EL element 20, the source 23 s of the driving transistor 23 and the electrode 24 b of the capacitor 24, and the gate 21 g is the gate of the holding transistor 22. 22g and the scanning line X are conducted.

  In the holding transistor 22, the source 22 s is connected to the gate 23 g of the drive transistor 23 and the electrode 24 a of the capacitor 24, the drain 22 d is connected to the drain 23 d of the drive transistor 23 and the supply line Z, and the gate 22 g is the gate of the switch transistor 21. 21g and the scanning line X are conducted.

  In the driving transistor 23, the source 23 s is electrically connected to the anode of the organic EL element 20, the drain 21 d of the switch transistor 21 and the electrode 24 b of the capacitor 24, and the drain 23 d is electrically connected to the drain 22 d and the supply line Z of the holding transistor 22. 23 g is electrically connected to the source 22 s of the holding transistor 22 and the electrode 24 a of the capacitor 24.

  The sources 21s of the switch transistors 21 of any subpixel P arranged in a line along the vertical direction are electrically connected to the common signal line Y. On the other hand, the gate 21g of the switch transistor 21 of any subpixel P arranged in a line along the horizontal direction is electrically connected to the common scanning line X.

  In FIG. 3, the switch transistor 21, the holding transistor 22, and the drive transistor 23 are n-channel type, but may be p-channel type. In this case, the relationship between the source and the drain is reversed.

  4 is a cross-sectional view of the EL display panel cut in the thickness direction along the cutting line IV-IV in FIG. As shown in FIG. 4, the switch transistor 21, the holding transistor 22, and the driving transistor 23 are provided on the insulating substrate 2. The switch transistor 21, the holding transistor 22 and the driving transistor 23 are covered with a common protective insulating film 32.

  Each of the switch transistor 21, the holding transistor 22, and the driving transistor 23 is a thin film transistor having an inverted staggered structure. That is, the switch transistor 21 includes a gate 21g formed on the insulating substrate 2, a semiconductor film 21c opposed to the gate 21g with the gate insulating film 31 interposed therebetween, and a channel protective film formed on the central portion of the semiconductor film 21c. Impurity semiconductor films 21a and 21b formed to be spaced apart from each other on both ends of the semiconductor film 21c and partially overlap the channel protective film 21p, a drain 21d formed on the impurity semiconductor film 21a, and an impurity semiconductor And a source 21s formed on the film 21b. Similarly to the switch transistor 21, the drive transistor 23 also includes a gate 23g, a semiconductor film 23c, a channel protection film 23p, impurity semiconductor films 23a and 23b, a drain 23d, and a source 23s formed on the impurity semiconductor film 23b. And is composed of. The holding transistor 22 is configured similarly to the switch transistor 22 and the drive transistor 23.

  The gate 21g of the switch transistor 21, the gate 22g of the holding transistor 22, the gate 23g of the driving transistor 23, and the electrode 24a of the capacitor 24 are insulated by a vapor phase growth method (for example, PVD method such as sputtering, ion plating, vacuum deposition). The conductive gate layer (for example, a film made of Al and Ti) formed on the substrate 2 is formed by patterning using a photolithography method and an etching method. The scanning line X and the supply line Z are formed simultaneously with the gates 21g to 23g by patterning the gate layer. The gates 21g to 23g, the electrode 24a, the scanning line X, and the supply line Z are covered with a common gate insulating film 31.

  The drain 21d and source 21s of the switch transistor 21, the drain 22d and source 22s of the holding transistor 22, the drain 23d and source 23s of the driving transistor 23, and the electrode 24b of the capacitor 24 are formed on the gate insulating film 31 by vapor deposition. The conductive drain layer thus formed (for example, a film formed by laminating a film made of Al and Ti on a Cr film) is formed by patterning using a photolithography method and an etching method. The signal line Y is formed simultaneously with the sources 21s to 23s and the drains 21d to 23d by patterning the drain layer. The sources 21s to 23s, the electrodes 24b, the drains 21d to 23d, and the signal line Y are covered with a common protective insulating film 32 including silicon nitride or silicon oxide. Although not shown, a low-resistance wiring containing copper, silver, gold, aluminum, or an alloy containing them as a main component is formed on the supply line Z in order to eliminate signal delay due to the resistance of the wiring of the supply line Z. May be. This wiring is buried in a groove provided in at least one of the planarizing film 33 and the protective insulating film 32. The low resistance wiring is insulated from the signal line Y and the metal partition wall W by an insulating film 34 described later.

  On the protective insulating film 32, a planarizing film 33 obtained by curing a resin is laminated. The surface of the planarization film 33 is flattened, and unevenness due to the switch transistor 21, the holding transistor 22, the drive transistor 23, the scanning line X, the signal line Y, and the supply line Z is eliminated by the planarization film 33.

  The stacked structure from the insulating substrate 2 to the planarizing film 33 is the transistor array panel 50.

On the planarizing film 33, subpixel electrodes 20a that are anodes of the organic EL elements 20 are arranged in a matrix. In FIG. 2, the position of the rectangular subpixel P represents the position of the subpixel electrode 20a (shown in FIG. 3 and the like). That is, the subpixel electrodes 20a are arranged in a line in the vertical direction between the adjacent signal lines Y, and the subpixel electrodes 20a are arranged in a line in the horizontal direction between the scanning line X and the adjacent supply line Z below the scanning line X. Yes. Note that these subpixel electrodes 20a are conductive films (for example, tin-doped indium oxide (ITO), zinc-doped indium oxide, indium oxide (In ₂ O ₃ )) formed on the planarizing film 33 by vapor phase growth. ), Tin oxide (SnO ₂ ), zinc oxide (ZnO), or cadmium-tin oxide (CTO)) is formed by patterning using a photolithography method and an etching method. In each subpixel P, a contact hole 91 is formed so as to penetrate the planarization film 33 and the protective insulating film 32, and the subpixel electrode 20 a and the source 23 s of the driving transistor 23 are formed by the conductive pad 92 buried in the contact hole 91. It is connected.

On the planarizing film 33, an insulating film 34 is formed in addition to the subpixel electrode 20a. The insulating film 34 is formed in a mesh shape so as to sew between the subpixel electrodes 20 a and overlaps with a part of the outer edge of the subpixel electrode 20 a, and the subpixel electrode 20 a is surrounded by the insulating film 34. The insulating film 34 is made of silicon nitride (SiN) or silicon oxide (SiO ₂ ).

  An adhesion layer 35 made of, for example, chromium is formed on the insulating film 34 by a PVD method such as sputtering, ion plating, vacuum deposition, and the like, and copper, silver, gold, aluminum, and their main components are formed on the adhesion layer 35. A metal partition wall W containing at least one of the alloys is laminated. The adhesion layer 35 is formed when the metal partition wall W does not have good adhesion with the insulating film 34 and may be peeled off. However, it is a film having excellent adhesion. The linear expansion coefficient of the adhesion layer 35 is preferably between the linear expansion coefficient of the insulating film 34 and the linear expansion coefficient of the metal partition wall W. As shown in FIG. 2, the adhesion layer 35 and the metal partition wall W extend in the vertical direction between the column of the subpixel electrodes 20a in the vertical direction and the column of the adjacent subpixel electrodes 20a, and adhere to the signal line Y. The layer 35 and the metal partition wall W overlap each other in plan view. The metal partition wall W is obtained by curing the metal nano ink, and is sufficiently thicker than each electrode of the transistors 21 to 23, the scanning line X, the signal line Y, and the supply line Z, and further functions as an auxiliary wiring. These metal barriers W are connected to each other outside the region where the subpixels P are arranged, and are electrically connected to a counter electrode 20c described later. The metal partition wall W is electrically connected to the counter electrode 20c to supply a common voltage, and has an effect of reducing the sheet resistance of the electrode as a whole even if the counter electrode 20c does not have a sufficiently low resistance. For this reason, even if each counter electrode 20c is thin or has a high resistance, it functions as an electrode sufficiently. Therefore, if the counter electrode 20c is a transparent electrode, the light transmittance of the counter electrode 20c can be improved.

  In FIG. 2, the width of the metal partition wall W is narrower than that of the signal line Y in order to make it easy to distinguish the signal line Y from the metal partition wall W. However, as shown in FIG. The metal partition wall W may have substantially the same width as the signal line Y, or the metal partition wall W may be wider than the signal line Y. In FIG. 2, a plurality of metal partition walls W are formed in a line shape and overlap a part of the insulating film 34, but the metal partition walls W are formed in a mesh shape, and the mesh-shaped metal partition walls W are formed in the insulating film 34. It may be overlapped with the whole.

  A liquid repellent conductive film 36 having liquid repellency is formed on the surface of the metal partition wall W. In the liquid repellent conductive film 36, the hydrogen atom (H) of the mercapto group (—SH) of triazyltrithiol represented by the following chemical formula (1) is reduced and released, and the sulfur atom (S) is selectively metal. It is one that is oxidized and adsorbed on the surface of the partition wall W. A state where the contact angle with respect to a certain liquid is 50 ° or more is called liquid repellency, and a state where the contact angle with respect to a certain liquid is 40 ° or less is called lyophilic.

  The liquid repellent conductive layer 36 has a very thin molecular layer structure. That is, since the liquid repellent conductive layer 36 is a very thin film of triazyltrithiol molecules on the surface of the metal partition wall W, the liquid repellent conductive layer 36 has a very low resistance and can be electrically conducted in the thickness direction. The triazyltrithiol molecule selectively binds to the metal, but does not coat the metal oxide such as ITO or the organic substance so as to exhibit liquid repellency. In order to make liquid repellency remarkable, instead of triazyltrithiol, a liquid repellent functional group in which the mercapto group (-SH) of triazyltrithiol contains alkyl fluoride as shown in the following chemical formula (2) A derivative substituted with a group may be used. The liquid repellent functional group may be other than that represented by the chemical formula (2). In the compound of the chemical formula (2), the hydrogen atom (H) of the mercapto group is reduced and released, and the sulfur atom (S) is oxidized and adsorbed on the surface of the metal partition wall W, whereby the liquid repellent conductive layer 36 is formed. .

ただし、ｍは１以上の整数であり好ましくは２であり、ｎは１以上の整数であり好ましくは３である。

However, m is an integer greater than or equal to 1, Preferably it is 2, n is an integer greater than or equal to 1, Preferably it is 3.

  An organic EL layer 20b is stacked on the subpixel electrode 20a. The organic EL layer 20b is formed by stacking two or more organic compound-containing layers. Here, the organic EL layer 20b has a two-layer structure in which a hole transport layer 20d and a light emitting layer 20e are sequentially stacked from the subpixel electrode 20a. The hole transport layer is made of PEDOT (polythiophene) which is a conductive polymer and PSS (polystyrene sulfonic acid) which is a dopant, and the light emitting layer is made of a polyfluorene-based light emitting material. The organic EL layer 20b may have a three-layer structure including a hole transport layer, a light emitting layer, and an electron transport layer in order from the subpixel electrode 20a, or a light emitting layer, an electron transport layer, and the like in order from the subpixel electrode 20a. The subpixel electrode 20a may be a cathode, the light emitting layer and the hole transport layer may be sequentially formed from the subpixel electrode 20a, or the electron transport layer and the light emitting layer may be sequentially formed from the subpixel electrode 20a. Alternatively, the combination of the charge transport layer and the light emitting layer can be arbitrarily set. In these layer structures, a laminated structure in which an interlayer that restricts charge transport is interposed between appropriate layers may be used, or another laminated structure may be used.

  The organic EL layer 20b is formed by a wet coating method (for example, an ink jet method) after the liquid repellent conductive film 36 is formed. In this case, an organic compound-containing liquid containing PEDOT and PSS that becomes the hole transport layer 20d is applied to the subpixel electrode 20a to form a dry film, and then an organic material containing a polyfluorene-based light emitting material that becomes the light emitting layer 20e. Although the compound-containing liquid is applied, since the thick metal partition wall W is provided, the liquid-repellent conductive film 36 is further formed on the surface of the metal partition wall W, so that it is applied to the adjacent subpixel electrode 20a. It is possible to prevent the mixed organic compound-containing liquid from mixing over the metal partition wall W.

  When the subpixel P is red, the organic EL layer 20b (particularly, the light emitting layer 20e) emits red light. When the subpixel P is green, the organic EL layer 20b emits green light, and the subpixel P When blue is blue, the material of each light emitting layer 20e is set so that the organic EL layer 20b emits blue light.

  On the organic EL layer 20b, a counter electrode 20c which is a cathode of the organic EL element 20 is formed. The counter electrode 20c is a common electrode formed in common for all the subpixels P, and is formed on the entire surface. Since the counter electrode 20c is formed on the entire surface, the counter electrode 20c covers the metal partition wall W with the liquid repellent conductive film 36 interposed therebetween. Since the liquid repellent conductive layer 36 is an extremely thin film, the counter electrode 20c and the metal partition wall W are electrically connected via the liquid repellent conductive layer 36, and a common potential output from the metal partition wall W stretched with low resistance. Thus, the potential of the counter electrode 20c is equal in all subpixels.

  The counter electrode 20c is formed of a material having a work function lower than that of the subpixel electrode 20a. For example, the counter electrode 20c is formed of a simple substance or an alloy containing at least one of indium, magnesium, calcium, lithium, barium, and a rare earth metal. Further, when the EL display panel has a bottom emission structure, the counter electrode 20c may have a laminated structure in which layers of the above various materials are laminated, and a metal layer is deposited in addition to the above various material layers. It may be a laminated structure. Specifically, the counter electrode 20c has a laminated structure including a high-purity barium layer having a low work function provided on the organic EL layer 20b side and an aluminum layer provided so as to cover the barium layer. Or a laminated structure comprising a lithium layer provided on the organic EL layer 20b side and an aluminum layer provided so as to cover the barium layer, and in the case of a top emission structure, the counter electrode 20c has the work function described above. A layered structure in which a layer containing a simple substance or an alloy and a transparent electrode such as ITO described above are formed thereon, and the subpixel electrode 20a is formed of a reflective metal layer and an ITO or the like formed thereon. A stacked structure of metal oxide layers may be used. When the counter electrode 20c is used as an anode, the counter electrode 20c may be composed of the above-described transparent electrode such as ITO.

  The organic EL element 20 is formed by laminating the subpixel electrode 20a, the organic EL layer 20b, and the counter electrode 20c in this order.

  Hereinafter, the width, cross-sectional area, and resistivity of the metal partition wall W are defined. Here, when the number of sub-pixels of the display panel is WXGA (768 × 1366), a desirable width and cross-sectional area of the metal partition wall W are defined. FIG. 9 is a graph showing current-voltage characteristics of the drive transistor 23 and the organic EL element 20 of each subpixel.

  In FIG. 9, the vertical axis represents the magnitude of the write current flowing between the source 23 s and the drain 23 d of one drive transistor 23 or the magnitude of the drive current flowing between the anode and cathode of one organic EL element 20. The axis represents the level of the voltage between the source 23s and the drain 23d of one drive transistor 23 (at the same time, the voltage between the gate 23g and the drain 23d of one drive transistor 23). In the figure, solid line Ids max is a write current and drive current at the maximum luminance gradation (brightest display), and alternate long and short dash line Ids mid is an intermediate luminance between the highest luminance gradation and the lowest luminance gradation. The two-dot chain line Vpo is a threshold value, that is, a pinch-off voltage between the unsaturated region (linear region) and the saturated region of the driving transistor 23, and the three-dot chain line Vds is the driving transistor 23. The write current that flows between the source 23s and the drain 23d of FIG.

  Here, the voltage VP1 is a pinch-off voltage of the driving transistor 23 at the maximum luminance gradation, and the voltage VP2 is a source-drain voltage when a writing current of the maximum luminance gradation flows through the driving transistor 23. VELmax (voltage VP4−voltage VP3) is a voltage between the anode and the cathode when the organic EL element 20 emits light with the driving current of the maximum luminance gradation equal in magnitude to the writing current of the maximum luminance gradation. The voltage VP2 ′ is a source-drain voltage when the driving transistor 23 receives an intermediate luminance gradation write current, and the voltage (voltage VP4′−voltage VP3 ′) is an organic EL element 20 having an intermediate luminance gradation. This is the anode-cathode voltage when light is emitted with a driving current of intermediate luminance gradation having the same magnitude as the writing current.

  Since both the drive transistor 23 and the organic EL element 20 are driven in the saturation region, a value VX obtained by subtracting (the voltage Vcom during the light emission period of the metal barrier W) from (the voltage VH during the light emission period of the supply line Z) is The following formula (1) is satisfied.

      VX = Vpo + Vth + Vm + VEL (1)

  Vth (equal to VP2−VP1 at the maximum luminance) is a threshold voltage of the drive transistor 23, VEL (equal to VELmax at the maximum luminance) is an anode-cathode voltage of the organic EL element 20, and Vm is The allowable voltage is displaced according to the gradation.

  As is apparent from the figure, the higher the luminance gradation of the voltage VX, the higher the voltage (Vpo + Vth) required between the source and drain of the transistor 23 and the voltage VEL required between the anode and cathode of the organic EL element 20. Becomes higher. Therefore, the allowable voltage Vm becomes lower as the luminance gradation becomes higher, and the minimum allowable voltage Vmmin becomes VP3−VP2.

  The organic EL element 20 generally deteriorates with time regardless of the low-molecular EL material and the high-molecular EL material, and increases in resistance. It has been confirmed that the anode-cathode voltage after 10,000 hours is about 1.4 times the initial voltage. That is, the voltage VEL increases with time even at the same luminance gradation. For this reason, the higher the allowable voltage Vm at the beginning of driving, the more stable the operation over a long period of time. Therefore, the voltage VX is set so that the voltage VEL is 8V or higher, more preferably 13V or higher.

  This allowable voltage Vm includes not only the increase in resistance of the organic EL element 20 but also the voltage drop caused by the supply line Z.

  When the voltage drop is large due to the wiring resistance of the common line Z, the power consumption of the display panel is remarkably increased. Therefore, the voltage drop of the common line Z is particularly preferably set to 1 V or less.

As a result of considering the sub-pixel width Wp which is the length of one sub-pixel P in the row direction and the number of sub-pixels (1366) in the row direction, it is common when the panel size of the display panel is 32 inches or 40 inches. The total length of the line Z is 706.7 mm and 895.2 mm, respectively. Here, when the line width WL of the metal partition wall W is increased, the area of the organic EL layer 20b is structurally reduced, and further, a parasitic capacitance with other wirings is generated to cause a further voltage drop. Each of the line widths WL is preferably suppressed to one fifth or less of the subpixel width Wp. Considering this, when the panel size of the display panel is 32 inches and 40 inches, the width WL is within 34 μm and within 44 μm, respectively. In addition, the maximum film thickness Hmax of the metal partition wall W is 1.5 times the minimum processing dimension 4 μm of the transistors 21 to 23, that is, 6 μm, considering the aspect ratio. Thus the maximum cross-sectional area Smax of the metal barrier wall W 32 inch, 40 inches, respectively 204Myuemu ^2, a 264μm ^2.

  In order to reduce the maximum voltage drop of the metal partition wall W to 1 V or less when all of the 32-inch display panels are lit so that the maximum current flows, the wiring resistivity of the metal partition wall W is as shown in FIG. ρ / cross-sectional area S needs to be set to 4.7 Ω / cm or less. FIG. 11 shows the correlation between the cross-sectional area of the metal partition wall W and the current density of the 32-inch display panel. Note that the resistivity allowed at the maximum cross-sectional area Smax of the metal partition wall W is 9.6 μΩcm at 32 inches and 6.4 μΩcm at 40 inches.

  For a 40-inch display panel, in order to make each maximum voltage drop of the metal partition wall W 1V or less when fully lit so that the maximum current flows, the wiring resistance of the metal partition wall W as shown in FIG. The ratio ρ / cross-sectional area S needs to be set to 2.4 Ω / cm or less. FIG. 13 shows the correlation between the cross-sectional area of the metal partition wall W of the 40-inch display panel and the current density.

  The failure life MTF that stops operating due to the failure of the metal partition wall W satisfies the following formula (2).

MTF = A exp (Ea / K _b T) / ρJ ² (2)

Ea is the activation energy, K _b T = 8.617 × 10 ⁻⁵ eV, ρ is the resistivity of the metal partition wall W, and J is the current density.

The failure life MTF of the metal partition wall W is limited by an increase in resistivity or electromigration. When the metal partition wall W is set to Al (single Al or an alloy such as AlTi or AlNd) and the MTF is estimated for 10,000 hours at an operating temperature of 85 ° C., the current density J is 2.1 × 10 ⁴ A / cm ² or less. It is necessary to. Similarly, when the metal partition wall W is set to Cu, it is necessary to make it 2.8 × 10 ⁶ A / cm ² or less. It is assumed that materials other than Al in the Al alloy have a lower resistivity than Al.
In consideration of these points, in the 32-inch display panel, the cross-sectional area S of the Al-based metal partition wall W that does not cause the metal partition wall W to fail in 10,000 hours in the fully lit state is 57 μm ² from FIG. Similarly, the cross-sectional area S of each of the Cu metal partition walls W is 0.43 μm ² or more from FIG.

In the 40-inch display panel, the cross-sectional area S of the Al-based metal partition wall W that does not cause the metal partition wall W to fail in 10,000 hours in the fully lit state requires 92 μm ² or more from FIG. Each cross-sectional area S of the Cu metal partition wall W is required to be 0.69 μm ² or more from FIG.

In the Al-based metal partition wall W, if the Al-based resistivity is 4.00 μΩcm, the 32-inch display panel has a wiring resistivity ρ / cross-sectional area S of 4.7 Ω / cm or less as described above. Smin is 85.1 μm ² . At this time, since the wiring width WL of the metal partition wall W is within 34 μm as described above, the minimum film thickness Hmin of the metal partition wall W is 2.50 μm.

In addition, since the wiring resistivity ρ / cross-sectional area S is 2.4 Ω / cm or less in the 40-inch display panel of the Al-based metal partition wall W, the minimum cross-sectional area Smin is 167 μm ^{2 as} described above. At this time, since the wiring width WL of the metal partition wall W is within 44 μm as described above, the minimum film thickness Hmin of the metal partition wall W is 3.80 μm.

In the case of the Cu metal partition wall W, if the Cu resistivity is 2.10 μΩcm, the 32-inch display panel has a wiring resistivity ρ / cross-sectional area S of 4.7 Ω / cm or less as described above, so the minimum cross-sectional area Smin is 44.7 μm ² . At this time, since the wiring width WL of the metal partition wall W is within 34 μm as described above, the minimum film thickness Hmin of the metal partition wall W is 1.31 μm.

Further, in the 40-inch display panel of the Cu metal partition wall W, the wiring resistivity ρ / cross-sectional area S is 2.4Ω / cm or less as described above, so the minimum cross-sectional area Smin is 87.5 μm ² . At this time, since the wiring width WL of the metal partition wall W is within 44 μm as described above, the minimum film thickness Hmin of the metal partition wall W is 1.99 μm.

  From the above, in order to operate the display panel normally and with low power consumption, it is preferable to set the voltage drop at the metal partition wall W to 1 V or less. In the 32-inch panel, the film thickness H is 2.50 μm to 6 μm, the width WL is 14.1 μm to 34.0 μm, the resistivity is 4.0 μΩcm to 9.6 μΩcm, and the metal partition wall W is an Al-based 40 inch. In the panel, when the metal partition wall W is Al, the film thickness H is 3.80 μm to 6 μm, the width WL is 27.8 μm to 44.0 μm, and the resistivity is 4.0 μΩcm to 9.6 μΩcm.

In general, in the case of an Al-based metal partition wall W, the thickness H is 2.50 μm to 6 μm, the width WL is 14.1 μm to 44 μm, and the resistivity is 4.0 μΩcm to 9.6 μΩcm.
Similarly, in a 32-inch panel in which the metal partition wall W is Cu, the film thickness H is 1.31 μm to 6 μm, the width WL is 7.45 μm to 34 μm, the resistivity is 2.1 μΩcm to 9.6 μΩcm, and the metal partition wall W is In a 40-inch panel of Cu, when the metal partition wall W is Cu-based, the film thickness H is 1.99 μm to 6 μm, the width WL is 14.6 μm to 44.0 μm, and the resistivity is 2.1 μΩcm to 9.6 μΩcm. .

In general, in the case of the Cu metal partition wall W, the film thickness H is 1.31 μm to 6 μm, the width WL is 7.45 μm to 44 μm, and the resistivity is 2.1 μΩcm to 9.6 μΩcm.
Therefore, when an Al-based material or Cu is applied as the metal barrier W, the metal barrier W of the display panel has a film thickness H of 1.31 μm to 6 μm, a width WL of 7.45 μm to 44 μm, and a resistivity of 2.1 μΩcm to 9.6 μΩcm.

  Next, a method for manufacturing an EL display panel having a bottom emission structure will be described.

  As shown in FIG. 5, a transistor array panel 50 is manufactured by appropriately performing vapor deposition, photolithography, and etching several times, and contact holes 91 are formed in the respective subpixels P so as to be conductive. The pad 92 is embedded, and the transparent subpixel electrode 20a made of a metal oxide such as ITO is patterned in the order of the vapor phase growth method, the photolithography method, and the etching method. Next, after the insulating film 34 is formed by vapor deposition, the sub-pixel electrode 20a is exposed by patterning in a mesh pattern over the transistor array panel 50.

  Next, as shown in FIG. 6, an adhesion layer 35 made of chromium is formed on the insulating film 34 between the subpixel electrodes 20a, and a transistor is formed on the insulating film 34 by vapor deposition, photolithography, and etching. A network is formed on the array panel 50. Note that the insulating film 34 may be patterned before the metal layer that forms the adhesion layer 35 is formed, and the insulating film 34 may be patterned after the adhesion layer 35 is patterned. .

  Next, as shown in FIG. 7, a resist 52 is applied to the entire surface, and the resist 52 is exposed and developed, so that the resist 52 is exposed between the adjacent subpixel electrodes 20 a in the horizontal direction and above the adhesion layer 35. Opening is performed, and the adhesion layer 35 is exposed in the opening.

  Next, as shown in FIG. 8, the metal nano ink is applied to the opening of the resist 52 using an inkjet head or a dispenser, and the metal partition wall W is laminated on the adhesion layer 35. When the inkjet head is used, at least one of the inkjet head or dispenser and the transistor array panel 50 so that the discharge nozzle or dispenser nozzle of the metal nano ink of the inkjet head moves relatively along the surface of the transistor array panel 50. The metal nano ink is ejected from the ink jet head or the dispenser while moving. The metal nano-ink used here is a dispersion medium in which a plurality of metal fine particles having a diameter of about 5 to 9 nm including at least one of silver, gold, copper, aluminum, and an alloy mainly composed of these are coated with a coating agent. Silver nano-ink is particularly preferable because it is dispersed, can be processed at a relatively low temperature in the baking step, and has a relatively low specific resistance. The metal nano ink may be mixed with a metal having a low melting point so as to be easily melted when aggregated by firing. While the metal nano ink is applied on the adhesion layer 35, the transistor array panel 50 is heated to several tens of degrees Celsius, so that the solvent in the metal nano ink is evaporated and a dried metal partition wall W is formed. Further, the metal partition wall W may be formed by applying a powder made of metal fine particles instead of applying the metal nano ink. In this case, it is desirable to quickly heat the metal particles to a temperature at which the metal particles are melted so that the metal particles do not scatter. Further, in the state of FIG. 7, dip film deposition may be performed in which the adhesion layer 35 of the transistor array panel 50 is deposited in a tank filled with metal nano ink.

  As described above, even when the metal nano ink is difficult to adhere to the insulating film 34, the adhesion layer 35 having high adhesion to the metal nanopace is patterned. It can form without having. In addition, since the resist 52 is patterned and the metal nano ink is applied to the openings between the resists 52, the applied metal nano ink is blocked by the resist 52, and bleeding of the applied metal nano ink can be prevented. it can. Therefore, the metal partition wall W can be patterned with high accuracy. Further, since the metal nano ink is supported by the resist 52 and fits in the opening of the resist 52, the metal nano ink does not spread from the adhesion layer 35 and flow out to the subpixel electrode 20a even if the viscosity is low. That is, the width of the metal partition wall W can be regulated by the opening width of the resist 52, so that the metal partition wall W can be set to a predetermined length, and the metal partition wall W is short-circuited with the subpixel electrode 20a or the adjacent metal partition wall W. There is no.

  Next, after removing the resist 52, the metal partition wall W is baked at 180 ° C. to 220 ° C. for 30 to 60 minutes to fix, aggregate, and completely solidify a plurality of metal fine particles in the metal partition wall W.

  Next, the transistor array panel 50 is cleaned by an ultraviolet / ozone cleaning method. Next, an aqueous solution of a triazine thiol compound or a triazine thiol derivative (for example, chemical formula (1) or chemical formula (2)) is applied to the entire surface of the transistor array panel 50, or the transistor array panel 50 is immersed in the aqueous triazine thiol solution. By doing so, the surface treatment of the metal partition wall W is performed. Due to the nature of triazine thiol, an aqueous triazine thiol solution is applied to the surface of the metal partition wall W, and the liquid repellent conductive film 36 is formed on the surface of the metal partition wall W, but the surface of the insulating film 34 is liquid repellent. A conductive film is not formed.

Here, the fluorine-based triazine dithiol derivative of the chemical formula (2) is hardly soluble or insoluble in water, but can be dissolved in an aqueous solution of the same molar amount of NaOH or KOH to prepare a fluorine-based triazine dithiol derivative aqueous solution. . The concentration of the aqueous solution is in the range of 1 × 10 ⁻⁴ to 1 × 10 ⁻² mol / L. When using a fluorine-based triazinedithiol derivative aqueous solution, it is preferable that the temperature of the aqueous solution is 20 to 30 ° C. and the immersion time is 1 to 10 minutes. The more fluorine in the fluorine-based triazine dithiol derivative, the more water-repellent it is, but it is difficult for it to dissolve in the solvent. The trithiol and dithiol described above are not limited to monothiol, and in the case of monothiol, one or two liquid repellent functional groups containing alkyl fluoride may be provided.

  After immersing the transistor array panel 50 in the aqueous triazine thiol solution, the transistor array panel 50 is taken out and the transistor array panel 50 is rinsed with alcohol. This flushes away excess triazine thiol.

Next, after the transistor array panel 50 is secondarily washed with water, an inert gas (for example, nitrogen gas (N ₂ )) is blown onto the transistor array panel 50 to dry the transistor array panel 50.

  Next, an organic compound-containing liquid in which a hole injection material (PEDOT as a conductive polymer and PSS as a dopant) is dispersed in water is applied to the subpixel electrode 20a. As an application method, an inkjet method (droplet discharge method) or other printing methods may be used, or a coating method such as a dip coating method or a spin coating method may be used. In order to form the hole transport layer 20d independently for each subpixel electrode 20a, a printing method such as an inkjet method is preferable.

  When the hole transport layer 20d is formed by the wet coating method as described above, the thick metal partition wall W is provided, and further, the liquid repellent conductive film 36 is coated on the surface of the metal partition wall W. The organic compound-containing liquid applied to the adjacent subpixel electrodes 20a does not mix beyond the metal partition wall W. Therefore, the hole transport layer 20d can be formed independently for each subpixel electrode 20a.

  Furthermore, the liquid repellent property of the liquid repellent conductive film 36 prevents the organic compound-containing liquid applied to the subpixel electrode 20a from becoming thick at the outer edge of the subpixel electrode 20a, so that the hole transport layer 20d has a uniform thickness. A film can be formed.

  After forming the hole transport layer 20d, the transistor array panel 50 is heat-treated at a temperature of 160 to 180 ° C. using a hot plate.

  Next, polyfluorene-based luminescent materials whose emission colors are red, green, and blue are respectively dissolved in organic solvents (for example, tetralin, tetramethylbenzene, and mesitylene) to prepare organic compound-containing liquids for red, green, and blue, respectively. Then, a red organic compound-containing liquid is applied on the hole transport layer 20d of the red subpixel P, and a green organic compound-containing liquid is applied on the hole transport layer 20d of the green subpixel P, On the hole transport layer 20d of the blue subpixel P, a blue organic compound-containing liquid is applied. Thereby, the light emitting layer 20e is formed on the hole transport layer 20d. As an application method, an ink-jet method (droplet discharge method) or other printing method is used, and coating is performed for each color.

  When the light emitting layer 20e is formed by the wet coating method as described above, the thick metal partition wall W is provided, and further, the surface of the metal partition wall W is coated with the liquid repellent conductive film 36. The organic compound-containing liquid applied to the matching subpixel P does not mix beyond the metal partition wall W. Therefore, the light emitting layer 20e can be formed independently for each subpixel P.

  In addition, before forming the light emitting layer 20e, an interlayer layer for limiting the hole transport property from the hole transport layer 20d is laminated on the hole transport layer 20d by a wet coating method such as an ink jet method, and then the interlayer layer The light emitting layer 20e may be laminated on the substrate.

  Next, the transistor array panel 50 is dried by a hot plate under an inert gas atmosphere (for example, a nitrogen gas atmosphere), and the residual solvent is removed. In addition, you may dry with a sheathed heater in a vacuum.

  Next, the counter electrode 20c is formed on the entire surface by vapor deposition. Specifically, a thin film of Ca or Ba is formed on the entire surface by vacuum deposition, and Al or ITO is formed on the entire surface. In the metal partition wall W, the liquid repellent conductive layer 36 is an extremely thin film, so that the counter electrode 20c and the metal partition wall W are electrically connected through the liquid repellent conductive layer 36, and the metal partition wall W stretched with low resistance is provided. Is equal to the potential of the counter electrode 20c in every sub-pixel.

  Next, an ultraviolet curable or thermosetting adhesive is applied to a sealing substrate (for example, a metal cap or a glass substrate), and the sealing substrate is bonded to the counter electrode 20c with the adhesive. Thereby, an EL display panel is completed.

  As described above, according to the present embodiment, the metal partition wall W protruding between the sub-pixels P is grown on the electrodes of the transistors 21 to 23 by the plating method. A film can be formed, and the resistance of the metal partition wall W can be reduced. Since the metal partition wall W is electrically connected to the counter electrode 20c, the voltage of the counter electrode 20c can be made uniform in the plane even when the counter electrode 20c itself is thinned to have a higher resistance. Therefore, variation in the light emission intensity for each subpixel P can be prevented, and the light emission intensity in the surface can be made uniform. For example, even when the same potential is applied to all the subpixel electrodes 20a, the light emission intensity of the organic EL layer 20b is almost equal in any subpixel P.

[Third Embodiment]
Next, an EL display panel according to the third embodiment will be described with reference to FIG. In addition, the same code | symbol is attached | subjected to the part which mutually respond | corresponds between the EL display panel in 3rd Embodiment, and the EL display panel in 2nd Embodiment. Below, when the mutually corresponding parts differ between the EL display panel in 3rd Embodiment and the EL display panel in 2nd Embodiment, the different part is demonstrated.

  In the EL display panel according to the third embodiment, the metal partition wall W is embedded in the contact hole 37 provided in the upper layer 133a of the insulating film 34 and the planarizing film 33. Here, the planarizing film 33 is composed of an upper layer 133a and a lower layer 133b, and the metal partition wall W is not embedded up to the lower layer 133b but is embedded in the upper layer 133a. Each of the upper layer 133a and the lower layer 133b is obtained by curing a photosensitive resin like a resist, and a portion of the upper layer 133a where the metal partition wall W is embedded is opened by exposure / development to form a contact hole 37. Specifically, the metal nano ink etches the upper layer 133a and the insulating film 34 from the state of FIG. 5 to form a contact hole 37, and the metal nano ink is applied to the contact hole 37 to form the metal partition wall W. While the metal nano ink is being applied, the transistor array panel 50 is heated to several tens of degrees Celsius, so that the solvent quickly evaporates and the dried metal fine particles are stacked in the contact hole 37. At this time, if the metal fine particles are stacked more than the height of the insulating film 34, a metal mask is deposited on the insulating film 34 after providing a resist mask having a contact hole at the position of the contact hole 37. Is preferred. The other manufacturing steps are the same as those in the second embodiment.

  The upper layer 133a and the insulating film 34 are used as a recess for embedding the metal partition wall W. However, since the upper layer 133a and the insulating film 34 are not removed and remain in the display panel as they are, the metal partition wall W has a bottom surface and sidewalls of the upper layer 133a and an insulating layer. Since the film 34 is in close contact with the side wall of the film 34, the metal partition wall W is more difficult to peel off as compared with the case of the second embodiment.

  As shown in FIG. 15, after the lower layer 133b is formed and before the upper layer 133a is formed, the adhesion layer 35 may be patterned on the lower layer 133b by a vapor deposition method, a photolithography method, and an etching method. good. In this case, after patterning the adhesive layer 35, the upper layer 133a is laminated and then the contact hole 37 is formed, or after the upper layer 133a is laminated and the contact hole 37 is provided in the upper layer 133a, the adhesive layer 35 is laminated. Thereafter, metal partition walls W are formed by applying metal nano ink toward the contact holes 37.

  The present invention is not limited to the above-described embodiments, and various improvements and design changes may be made without departing from the spirit of the present invention.

  For example, the liquid repellent conductive film 36 may be coated after the surface of the metal partition wall W is plated with gold.

Hereinafter, the present invention will be described more specifically with reference to examples.
As the substrate for patterning the wiring, a substrate having a silicon nitride (SiN) film formed on the surface thereof was used. In addition, Ag nanometal ink (model Agl TeH) manufactured by Vacuum Metallurgical Co., Ltd. was used as the metal nanoink. Further, as the resist, a novolak positive resist (model NPR3510PG) manufactured by Nagase ChemteX Corporation was used.

First, a chromium film having a thickness of 20 to 30 nm was formed on the surface of the substrate as an adhesion layer by sputtering, and the chromium film was patterned by a photolithography method and an etching method. The chromium film is formed so that the wiring is sufficiently adhered to the silicon nitride.
Thereafter, the positive resist was patterned by photolithography so as to expose the chromium film. Here, the film thickness of the positive resist was 1.5 μm, the opening width was 30 μm, and the opening pitch was 169 μm.
Next, metal nano ink was discharged to the opening of the resist by an ink jet method. At this time, the substrate stage of the ink jet apparatus was heated, and the metal nano ink was discharged in a state where the surface temperature of the substrate was heated to 50 ° C. In addition, the amount of droplets of the metal nano ink was 30 pl, the landing pitch was 85 μm, and the overcoating was performed twice.
Next, the substrate was left on the substrate stage until the applied metal nano ink was dry. When the ink was dry, the substrate was taken out, and the substrate was immersed in a potassium hydroxide aqueous solution as a removal solution, and the resist was removed. The concentration of potassium hydroxide is preferably 5 to 10 wt%. At this time, since the applied metal nano ink was temporarily dried on the substrate, the metal nano ink was not peeled even when the substrate was immersed in an aqueous potassium hydroxide solution.
After removing the resist, the metal nano ink was baked in the air. The firing condition temperature was 180 to 220 ° C., and the firing time was 30 to 60 minutes.
The completed wiring had a width of 30 μm and a film thickness of 1.5 μm.

It is process drawing of the patterning method of wiring. It is a schematic plan view of a display panel. It is an equivalent circuit diagram of a subpixel. FIG. 4 is a cross-sectional view taken along the line IV-IV in FIG. It is the figure which showed 1 process of the manufacturing method of a display panel. It is the figure which showed the next process of FIG. It is the figure which showed the next process of FIG. It is the figure which showed the next process of FIG. 4 is a graph showing current-voltage characteristics of a drive transistor 23 and an organic EL element 20. It is a graph which shows the correlation of the maximum voltage drop of the metal partition W and wiring resistivity (rho) / cross-sectional area S in a 32-inch display panel. It is a graph which shows the correlation of the cross-sectional area of the metal partition W and current density in a 32-inch display panel. It is a graph which shows the correlation of the maximum voltage drop of the metal partition W of a 40-inch display panel, and wiring resistivity (rho) / sectional area S. FIG. It is a graph which shows the correlation of the cross-sectional area of the metal partition wall W of a 40-inch display panel, and current density. It is sectional drawing of the display panel in 3rd Embodiment. It is sectional drawing of the display panel in a modification.

Explanation of symbols

35 Thin film 50 Transistor array panel 52 Resist 133a Upper layer (resist)
W Metal partition (wiring)
550 Transistor array panel 551 Thin film 552 Resist 553 Metal nano ink 554 Wiring

Claims (4)

In the display panel manufacturing method,
The display panel is
A plurality of transistors;
A scanning line, a signal line, and a supply line connected to at least one of the plurality of transistors;
A protective insulating film and a planarizing film covering the transistor;
An insulating film formed on the planarizing film;
An adhesion layer formed on the insulating film;
A barrier rib formed on the adhesion layer that is thicker than each electrode of the transistor, the scanning line, the signal line, and the supply line;
An organic EL element having a subpixel electrode formed on the planarizing film, a counter electrode, and an organic EL layer provided between the subpixel electrode and the counter electrode;
With
Between the signal line and the partition, the protective insulating film, the planarization film , the insulating film and the adhesion layer are interposed,
Forming a resist having an opening through which the adhesion layer is exposed;
The metal nano-ink or metal particles coated on the adhesive layer thus exposed in the openings of the resist,
The resist is removed after drying after applying the metal nano ink,
After removing the resist, the partition walls are patterned by baking the metal nano ink ,
A liquid repellent conductive layer having liquid repellency and electrically conducting in the thickness direction is formed on the surface of the partition wall,
Applying an organic compound-containing liquid toward the subpixel electrode formed between the partition walls to form the organic EL layer,
The counter electrode is formed continuously on the liquid repellent conductive layer and the organic EL layer, and the partition and the counter electrode are electrically connected through the liquid repellent conductive layer. Display panel manufacturing method.   The method for manufacturing a display panel according to claim 1, wherein silver nanoink is used as the metal nanoink. Linear expansion coefficient of the adhesive layer, the manufacturing method of a display panel according to claim 1 or 2, characterized in that between the linear expansion coefficient of the material directly beneath the contact layer and the linear expansion coefficient of the partition wall . Display panel, characterized in that it is manufactured by the manufacturing method according to any one of claims 1 to 3.

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