JP4691294B2 - 乗算−加算演算用高精度プロセッサ - Google Patents

乗算−加算演算用高精度プロセッサ Download PDF

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JP4691294B2
JP4691294B2 JP2001514658A JP2001514658A JP4691294B2 JP 4691294 B2 JP4691294 B2 JP 4691294B2 JP 2001514658 A JP2001514658 A JP 2001514658A JP 2001514658 A JP2001514658 A JP 2001514658A JP 4691294 B2 JP4691294 B2 JP 4691294B2
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multiplier
unit
fpu
fractional part
floating point
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JP2003529124A5 (enExample
JP2003529124A (ja
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ホ イン−ウァイ，
ジョン ケリー，
ジェイムス ジィアン，
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ミップス テクノロジーズ インコーポレイテッド
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49942—Significance control
    • G06F7/49947—Rounding
    • G06F7/49957—Implementation of IEEE-754 Standard
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
JP2001514658A 1999-07-30 2000-07-24 乗算−加算演算用高精度プロセッサ Expired - Fee Related JP4691294B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/364,512 1999-07-30
US09/364,512 US7346643B1 (en) 1999-07-30 1999-07-30 Processor with improved accuracy for multiply-add operations
PCT/US2000/020160 WO2001009712A1 (en) 1999-07-30 2000-07-24 Processor with improved accuracy for multiply-add operations

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JP2003529124A JP2003529124A (ja) 2003-09-30
JP2003529124A5 JP2003529124A5 (enExample) 2007-09-06
JP4691294B2 true JP4691294B2 (ja) 2011-06-01

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US (2) US7346643B1 (enExample)
EP (1) EP1234228A4 (enExample)
JP (1) JP4691294B2 (enExample)
WO (1) WO2001009712A1 (enExample)

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CN114647399B (zh) * 2022-05-19 2022-08-16 南京航空航天大学 一种低能耗高精度近似并行定宽乘法累加装置
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