JP4678156B2 - Cathode panel conditioning method, cold cathode field emission display device conditioning method, and cold cathode field emission display device manufacturing method - Google Patents

Description

  The present invention relates to a conditioning method for a cathode panel constituting a cold cathode field emission display device, a conditioning method for a cold cathode field emission display device in which a cathode panel and an anode panel are assembled, and a cold cathode field emission display device. It relates to the manufacturing method.

  As an image display device that can replace the mainstream cathode ray tube (CRT), various types of flat display devices have been studied. Examples of such a flat display device include a liquid crystal display device (LCD), an electroluminescence display device (ELD), and a plasma display device (PDP). In addition, a cold cathode field emission display device, so-called field emission display (FED), which can emit electrons from a solid into a vacuum without using thermal excitation has been proposed. It has attracted attention from the viewpoint of color display and low power consumption.

  A cold cathode field emission display device (hereinafter sometimes abbreviated as a display device) generally has a cathode panel having an electron emission region corresponding to each pixel arranged in a two-dimensional matrix, and emits from the electron emission region. The anode panel having a phosphor region that emits light when excited by collision with the emitted electrons has a configuration in which the anode panel is disposed to face each other through a vacuum layer. The electron emission region is usually provided with one or a plurality of cold cathode field emission devices (hereinafter sometimes abbreviated as field emission devices). Examples of field emission devices include Spindt type, flat type, edge type, and planar type.

  As an example, a conceptual partial end view of a display device having a Spindt-type field emission device is shown in FIG. 8, and a schematic view of a part of the cathode panel CP and the anode panel AP when the cathode panel CP and the anode panel AP are disassembled. A simple exploded perspective view is shown in FIG. The Spindt-type field emission device constituting this display device was formed on the cathode 10 formed on the support 10, the insulating layer 12 formed on the support 10 and the cathode 11, and the insulating layer 12. A gate electrode 13, an opening 14 provided in the gate electrode 13 and the insulating layer 12 (a first opening 14A provided in the gate electrode 13 and a second opening 14B provided in the insulating layer 12), and an opening It is composed of a conical electron emission portion 15 formed on the cathode electrode 11 located at the bottom of the portion 14.

  Alternatively, FIG. 9 shows a conceptual partial end view of a display device having a so-called flat field emission device having a substantially planar electron emission portion 115. The field emission device includes a cathode electrode 11 formed on a support 10, an insulating layer 12 formed on the support 10 and the cathode electrode 11, a gate electrode 13 formed on the insulating layer 12, a gate An opening 14 provided in the electrode 13 and the insulating layer 12 (a first opening 14A provided in the gate electrode 13 and a second opening 14B provided in the insulating layer 12) and a bottom of the opening 14 The electron emission portion 115 is formed on the cathode electrode 11 positioned. The electron emission part 115 is comprised from many carbon nanotubes with which one part was embedded in the matrix, for example.

  In these display devices, the cathode electrode 11 has a strip shape extending in the first direction, and the gate electrode 13 has a strip shape extending in a second direction different from the first direction (see FIG. 10). In general, the cathode electrode 11 and the gate electrode 13 are each formed in a strip shape in a direction in which the projected images of both the electrodes 11 and 13 are orthogonal to each other. An overlapping region where the strip-shaped cathode electrode 11 and the strip-shaped gate electrode 13 overlap is an electron emission region EA, which corresponds to one subpixel. Such electron emission areas EA are usually arranged in a two-dimensional matrix within the effective area of the cathode panel CP (area that functions as an actual display portion). Here, when the number of gate electrodes formed on the cathode panel CP is M and the number of cathode electrodes is N, the number of electron emission regions EA is M × N.

  On the other hand, the anode panel AP has phosphor regions 22 having a predetermined pattern on the substrate 20 (specifically, a red light-emitting phosphor region 22R, a green light-emitting phosphor region 22G, and a blue light-emitting phosphor region 22B). The phosphor region 22 is formed and covered with the anode electrode 24. In addition, a space between these phosphor regions 22 is embedded with a light absorbing layer (black matrix) 23 made of a light absorbing material such as carbon to prevent the occurrence of color turbidity and optical crosstalk in the display image. ing. In FIG. 8, reference numeral 21 represents a partition, reference numeral 25 represents a spacer, and reference numeral 26 represents a spacer holding portion. In FIG. 9, illustration of partition walls, spacers, and spacer holding portions is omitted.

  By disposing the anode panel AP and the cathode panel CP so that the electron emission region EA and the phosphor region 22 face each other and joining the peripheral portion via the frame body 27, exhausting and sealing, A display device can be manufactured. A space surrounded by the anode panel AP, the cathode panel CP, and the frame 27 is in a vacuum.

  A relatively negative voltage is applied to the cathode electrode 11 from the cathode electrode control circuit 31, a relatively positive voltage is applied to the gate electrode 13 from the gate electrode control circuit 32, and the anode electrode 24 is applied to the anode electrode 24 more than the gate electrode 13. Further, a higher positive voltage is applied from the anode electrode control circuit 33. When performing display in such a cold cathode field emission display, for example, a scanning signal is input from the cathode electrode control circuit 31 to the cathode electrode 11 and a video signal is input from the gate electrode control circuit 32 to the gate electrode 13. Alternatively, a video signal is input from the cathode electrode control circuit 31 to the cathode electrode 11, and a scanning signal is input from the gate electrode control circuit 32 to the gate electrode 13. Electrons are emitted from the electron emission portions 15 and 115 based on the quantum tunnel effect by an electric field generated when a voltage is applied between the cathode electrode 11 and the gate electrode 13, and the electrons are attracted to the anode electrode 24. It passes through 24 and collides with the phosphor region 22. As a result, the phosphor region 22 is excited to emit light, and a desired image can be obtained. That is, the operation of the cold cathode field emission display is basically controlled by the voltage applied to the gate electrode 13 and the voltage applied to the cathode electrode 11.

In the design of the display device, when the target brightness and contrast for achieving the brightest display are set, the target brightness for achieving the darkest display is derived. The voltage difference between the voltage v _G0 applied to the gate electrode and the voltage v _C0 applied to the cathode electrode to obtain the emission electron current at the target brightness for achieving the darkest display. Δv (= v _G0 −v _C0 ) is obtained. This voltage difference Δv (= v _G0 −v _C0 ) is called a cut-off voltage v _CUT .

  By the way, it is generally difficult to uniformly manufacture the electron emission portion 15 in the Spindt-type field emission device, particularly the tip portion thereof. When the electron emission characteristics of the electron emission portion 15 vary, the electron emission state from the electron emission portion 15 varies. In addition, since the electron emission portion 115 in the flat type field emission device is composed of a large number of carbon nanotubes, variation in the characteristics of individual carbon nanotubes and the arrangement state of the carbon nanotubes in one electron emission portion 115 Due to variations and the like, the electron emission state from the electron emission portion 115 varies.

When the operating voltage of the display device is at or near the cut-off voltage v _CUT , the display device displays the darkest display. However, when there is a field emission device that emits electrons even at or near the cutoff voltage v _CUT (hereinafter referred to as a low voltage electron emission field emission device for convenience), the display device as a whole has the darkest display. However, as a result of the electron emission region including the low voltage electron emission field emission device being recognized as a bright spot, there arises a problem that image quality deteriorates.

  In manufacturing a flat field emission device, carbon nanotubes may be left as a residue on the gate electrode 13 or the insulating layer 12 in the step of forming the electron emission portion 115. In such a case, based on the electric field formed by the anode electrode 24, electrons are emitted from the carbon nanotubes left as residues on the gate electrode 13 and the insulating layer 12, and the luminescent spots in the display device are uneven. Thus, the image quality may be deteriorated.

JP2002-343254 JP 2003-168355 A

  As a technique for preventing the occurrence of the problem described above, a conditioning technique disclosed in Japanese Patent Application Laid-Open No. 2002-343254 can be applied.

That is, the cathode panel CP is placed in a conditioning chamber provided with an inspection electrode facing the electron emission region, and a DC voltage _VA is applied to the inspection electrode. Alternatively, after assembling the cathode panel CP and the anode panel AP, the DC voltage V _A is applied to the anode electrode 24 before sealing. Here, the DC voltage V _A applied to the inspection electrode or the anode electrode 24 is higher than the DC voltage v _A applied to the anode electrode 24 during the actual operation of the display device. The first gate electrode, the second gate electrode, the third gate electrode,..., While simultaneously applying a voltage V _C (for example, 0 volts) to all of the N cathode electrodes 11. , A pulsed voltage V _G (> 0 volts) is sequentially applied to the (M−1) -th gate electrode and the M-th gate electrode, and then again the first gate electrode, the second gate electrode, numbered gate electrode of the third gate electrode, ..., the (M-1) th gate electrode, in the M-th gate electrode, sequentially applying a pulse voltage V _G (> 0 V) Repeat the operation.

As a result, in the low voltage electron emission field emission device, as a result of an excessive current flowing through the electron emission portions 15 and 115, the function of the electron emission field emission device is destroyed and the electron emission is stopped. be able to. In addition, in the case of carbon nanotubes left as a residue on the gate electrode 13 or the insulating layer 12 in the manufacture of the flat type field emission device, the direct current voltage V _A applied to the inspection electrode or the anode electrode 24 is used. Electrons are emitted based on the formed electric field, and an excess current flows through the carbon nanotubes left as residues on the gate electrode 13 and the insulating layer 12, resulting in removal by combustion.

However, in the case where a low voltage electron emission field emission device exists, even if no voltage is applied to the gate electrode 13, the electric field formed by the DC voltage V _A applied to the inspection electrode or the anode electrode 24. In some cases, electrons are emitted from the electron emission portions 15 and 115. In such a case, a direct current continues to flow between the field emission element and the inspection electrode or the anode electrode 24 during the conditioning process. As a result, the cathode panel CP or the like caused by the temperature rise in the field emission element or the anode electrode 24 There is a risk that the anode panel AP may be damaged, or the discharge inside the display device or the cathode panel CP may be broken.

Therefore, the first object of the present invention is to prevent the occurrence of damage to the cathode panel or the anode panel, the discharge breakdown in the cold cathode field emission display device or the cathode panel, and the like in the cutoff voltage v _CUT or the vicinity thereof. Cathode panel conditioning method, cold cathode field emission display device conditioning method, and cold cathode field emission display device capable of removing the cold cathode field emission device that emits electrons in operation It is to provide a method. The second object of the present invention is to provide a residue on the gate electrode or the insulating layer without causing problems such as damage to the cathode panel or anode panel and discharge breakdown in the cold cathode field emission display device or cathode panel. The present invention provides a conditioning method for a cathode panel, a conditioning method for a cold cathode field emission display device, and a manufacturing method for a cold cathode field emission display device capable of removing a substance that emits remaining electrons. .

The cathode panel conditioning method according to the first aspect of the present invention for achieving the first object is as follows.
(A) A plurality of strip-like cathode electrodes formed on the support and extending in the first direction;
(B) an insulating layer formed on the cathode electrode and the support;
(C) a plurality of strip-shaped gate electrodes formed on the insulating layer and extending in a second direction different from the first direction;
(D) one or a plurality of openings provided in a portion of the gate electrode and the insulating layer located in an overlapping region where the cathode electrode and the gate electrode overlap, and the cathode electrode exposed at the bottom; and
(E) an electron emission region having an electron emission portion located on the overlapping region where the cathode electrode and the gate electrode overlap each other and provided on the cathode electrode exposed at the bottom of the opening;
A cathode panel comprising: a conditioning panel provided with an inspection electrode facing the electron emission region;
While evacuating the conditioning chamber, applying a constant voltage V _C to each cathode electrode and applying a voltage V _IE to the inspection electrode, each gate electrode has a minimum voltage value V _G-MIN and a maximum voltage. A pulse voltage having a value V _G-MAX (where V _G-MIN <V _C <V _G-MAX << V _IE ) is applied.

The cathode panel conditioning method according to the second aspect of the present invention for achieving the second object described above,
(A) A plurality of strip-like cathode electrodes formed on the support and extending in the first direction;
(B) an insulating layer formed on the cathode electrode and the support;
(C) a plurality of strip-shaped gate electrodes formed on the insulating layer and extending in a second direction different from the first direction;
(D) one or a plurality of openings provided in a portion of the gate electrode and the insulating layer located in an overlapping region where the cathode electrode and the gate electrode overlap, and the cathode electrode exposed at the bottom; and
(E) an electron emission region having an electron emission portion located on the overlapping region where the cathode electrode and the gate electrode overlap each other and provided on the cathode electrode exposed at the bottom of the opening;
A cathode panel comprising: a conditioning panel provided with an inspection electrode facing the electron emission region;
While evacuating the conditioning chamber, a constant voltage V _C is applied to each cathode electrode, and a constant voltage V _G (where V _G <V _C ) is applied to each gate electrode. A voltage V _IE (where V _C << V _IE ) is applied.

A conditioning method of a cold cathode field emission display according to the first aspect of the present invention for achieving the first object is as follows:
(A) A plurality of strip-like cathode electrodes formed on the support and extending in the first direction;
(B) an insulating layer formed on the cathode electrode and the support;
(C) a plurality of strip-shaped gate electrodes formed on the insulating layer and extending in a second direction different from the first direction;
(D) one or a plurality of openings provided in a portion of the gate electrode and the insulating layer located in an overlapping region where the cathode electrode and the gate electrode overlap, and the cathode electrode exposed at the bottom; and
(E) an electron emission region having an electron emission portion located on the overlapping region where the cathode electrode and the gate electrode overlap each other and provided on the cathode electrode exposed at the bottom of the opening;
And a cathode cathode electron emission display device comprising: a cathode panel comprising: a cathode panel; and an anode panel comprising a phosphor region and an anode electrode joined together at the periphery thereof,
With a constant voltage V _C applied to each cathode electrode and a voltage V _A applied to the anode electrode, each gate electrode has a pulse-like shape having a minimum voltage value V _G-MIN and a maximum voltage value V _G-MAX. A voltage (however, V _G-MIN <V _C <V _G-MAX << V _A ) is applied.

A conditioning method of a cold cathode field emission display according to the second aspect of the present invention for achieving the second object described above,
(A) A plurality of strip-like cathode electrodes formed on the support and extending in the first direction;
(B) an insulating layer formed on the cathode electrode and the support;
(C) a plurality of strip-shaped gate electrodes formed on the insulating layer and extending in a second direction different from the first direction;
(D) one or a plurality of openings provided in a portion of the gate electrode and the insulating layer located in an overlapping region where the cathode electrode and the gate electrode overlap, and the cathode electrode exposed at the bottom; and
(E) an electron emission region having an electron emission portion located on the overlapping region where the cathode electrode and the gate electrode overlap each other and provided on the cathode electrode exposed at the bottom of the opening;
And a cathode cathode electron emission display device comprising: a cathode panel comprising: a cathode panel; and an anode panel comprising a phosphor region and an anode electrode joined together at the periphery thereof,
In a state where a constant voltage V _C is applied to each cathode electrode and a constant voltage V _G (where V _G <V _C ) is applied to each gate electrode, a voltage V _A (where V _C << V _A ) is applied.

A manufacturing method of a cold cathode field emission display according to the first aspect of the present invention for achieving the first object is as follows.
(A) A plurality of strip-like cathode electrodes formed on the support and extending in the first direction;
(B) an insulating layer formed on the cathode electrode and the support;
(C) a plurality of strip-shaped gate electrodes formed on the insulating layer and extending in a second direction different from the first direction;
(D) one or a plurality of openings provided in a portion of the gate electrode and the insulating layer located in an overlapping region where the cathode electrode and the gate electrode overlap, and the cathode electrode exposed at the bottom; and
(E) an electron emission region having an electron emission portion located on the overlapping region where the cathode electrode and the gate electrode overlap each other and provided on the cathode electrode exposed at the bottom of the opening;
After disposing the cathode panel equipped with in a conditioning chamber equipped with an inspection electrode facing the electron emission region,
While evacuating the conditioning chamber, applying a constant voltage V _C to each cathode electrode and applying a voltage V _IE to the inspection electrode, each gate electrode has a minimum voltage value V _G-MIN and a maximum voltage. A conditioning process is applied to apply a pulsed voltage having a value V _G-MAX (where V _G-MIN <V _C <V _G-MAX << V _IE ).
The cathode panel obtained in this way and the anode panel provided with the phosphor region and the anode electrode formed on the substrate are joined at the periphery thereof.

A manufacturing method of a cold cathode field emission display according to the second aspect of the present invention for achieving the second object described above,
(A) A plurality of strip-like cathode electrodes formed on the support and extending in the first direction;
(B) an insulating layer formed on the cathode electrode and the support;
(C) a plurality of strip-shaped gate electrodes formed on the insulating layer and extending in a second direction different from the first direction;
(D) one or a plurality of openings provided in a portion of the gate electrode and the insulating layer located in an overlapping region where the cathode electrode and the gate electrode overlap, and the cathode electrode exposed at the bottom; and
(E) an electron emission region having an electron emission portion located on the overlapping region where the cathode electrode and the gate electrode overlap each other and provided on the cathode electrode exposed at the bottom of the opening;
After disposing the cathode panel equipped with in a conditioning chamber equipped with an inspection electrode facing the electron emission region,
While evacuating the conditioning chamber, a constant voltage V _C is applied to each cathode electrode, and a constant voltage V _G (where V _G <V _C ) is applied to each gate electrode. A conditioning process for applying a voltage V _IE (V _C << V _IE ) is performed.
The cathode panel obtained in this way and the anode panel provided with the phosphor region and the anode electrode formed on the substrate are joined at the periphery thereof.

A conditioning method for a cathode panel according to the first aspect of the present invention, a conditioning method for a cold cathode field emission display according to the first aspect of the present invention, or a cold cathode field electron according to the first aspect of the present invention. In the conditioning process in the manufacturing method of the emission display device (hereinafter, these may be collectively referred to as the method according to the first aspect of the present invention), the cathode panel has a field frequency T (Hz) during actual operation. The frequency T _G (Hz) of the pulse voltage applied to each gate electrode is driven by the line-sequential driving method, and T _G = T / α (where 2 ≦ α ≦ 10) is satisfied. be able to.

In the method according to the first aspect of the present invention including the above-described preferable configuration, it is preferable that V _C −V _G−MIN ≧ 10 (volts) or V _G−MAX −V _C Is a value such that an electric field is generated in the vicinity of the electron emission portion so that electrons are emitted from the electron emission portion based on the quantum tunnel effect. Specifically, the voltage V _IE applied to the inspection electrode or It is desirable that the value be such that an electric field of at least 8 volts / μm is formed in the vicinity of the electron emission portion due to a synergistic effect with the voltage V _A applied to the anode electrode.

A cathode panel conditioning method according to the second aspect of the invention, a cold cathode field emission display conditioning method according to the second aspect of the invention, or a cold cathode field electron according to the second aspect of the invention. In the conditioning process in the manufacturing method of the emission display device (hereinafter, these may be collectively referred to as the method according to the second aspect of the present invention), V _C −V _G ≧ 10 (volts) is satisfied. It is preferable.

In the method according to the first aspect or the second aspect of the present invention including the various preferable configurations described above, a configuration in which constant voltages V _IE and V _A are applied to the inspection electrode or the anode electrode may be adopted. Alternatively, a pulse voltage having minimum voltage values V _IE-MIN and V _A-MIN and maximum voltage values V _IE and V _A may be applied to the inspection electrode or the anode electrode. Then, in the latter case, the actual operation, the cathode panel is driven by a line sequential driving method of field frequency T (Hz), the frequency T _IE of the pulsed voltage applied to the inspection electrode or anode, T _A (Hz) may be configured to satisfy T _IE or T _A = T / β (where 10 ≦ β ≦ 100). Further, a constant voltage V _IE to the inspection electrode or anode electrode, instead of applying the V _A, the voltage V _IE applied to the inspection electrode or anode electrode, may over time increases the V _A. In this case, the time-dependent increase in the voltages V _IE and V _A applied to the inspection electrode or the anode electrode may be linear or stepped.

In the conditioning method of the cold cathode field emission display device according to the first aspect or the second aspect of the present invention including the various preferable configurations described above, the space between the cathode panel and the anode panel is formed. It is preferable to execute the conditioning method while evacuating. However, in the case where the cold cathode field emission display device is provided with a getter or the like that can reliably adsorb gas generated inside the cold cathode field emission display device, the present invention includes various preferable configurations described above. The cold cathode field emission display device conditioning method according to the first aspect or the second aspect of the present invention is applied to a cold cathode field emission display device finished product (internally exhausted to a high vacuum and sealed You may perform with respect to an electron emission display apparatus. The degree of vacuum P ₁ (Pa) of the space between the cathode panel and the anode panel when the conditioning method is executed while exhausting the space between the cathode panel and the anode panel, or alternatively, for the conditioning being exhausted The degree of vacuum P ₁ (Pa) in the chamber is, for example, 0.01 ≦ P ₁ / P ₀ ≦ when the degree of vacuum in the completed cold cathode field emission display is P ₀ (Pa). It is desirable to satisfy 100. Note that P ₀ is on the order of 10 ⁻³ Pa to 10 ⁻⁶ Pa. When the value of P ₁ is too high (that is, when the degree of vacuum is poor), an excessive current flows also in an electron emission portion (cold cathode field emission device) that emits electrons at a voltage higher than the cutoff voltage v _CUT. There is a fear. On the other hand, if the value of P ₁ is too low (that is, high vacuum), an excessive current flows through the electron emission portion (cold cathode field emission device) that emits electrons at or near the cutoff voltage v _CUT. There is no fear.

The chamber provided with the inspection electrode is, for example,
A housing with an open top,
An inspection table placed in the housing for mounting the cathode panel;
Vacuum means for evacuating the housing,
An inspection voltage application unit having a structure capable of contacting the ends of the cathode electrode and the gate electrode;
An inspection substrate attached to the upper open portion of the housing and having an inspection electrode; and
Voltage control means for applying a voltage to the inspection electrode, the cathode electrode and the gate electrode;
It can consist of

In the cathode panel conditioning method or the cold cathode field emission display manufacturing method according to the first or second aspect of the present invention, the cathode panel is placed in a chamber whose pressure is set to P _1. The electron emission region is arranged so as to face the inspection electrode. Specifically,
(1) A method in which a cathode panel is carried into a chamber whose pressure is set to a pressure P _{1 in} advance and the cathode panel is disposed so that an electron emission region faces an inspection electrode. (2) A cathode panel is placed in the chamber. After carrying in and arranging the cathode panel so that the electron emission region faces the inspection electrode, the method of exhausting the inside of the chamber so that the inside becomes the pressure P ₁ (3) Loading the cathode panel into the chamber Any method may be employed in which the cathode panel is arranged so that the electron emission region faces the inspection electrode after the inside of the chamber is evacuated so that the inside becomes the pressure P ₁ .

In the method according to the first aspect or the second aspect of the present invention, a rectangular wave voltage can be exemplified as the form of the pulsed voltage. When the pulsed voltage is a rectangular wave voltage, t (V _G−MAX ) / T _G ^{−1 in} the method according to the first aspect of the present invention, the cathode panel according to the second aspect of the present invention T (V _IE ) / T _IE ^{−1 in} the conditioning method or cold cathode field emission display manufacturing method, t (V _A ) in the cold cathode field emission display conditioning method according to the second aspect of the present invention / a T _a ^-1 is called a duty ratio. Here, t (V _G-MAX ) is the length of time (unit: second) that the maximum voltage value V _G-MAX is applied to the gate electrode, and t (V _IE ) is the maximum voltage value V to the inspection electrode. _The time length (unit: second) in which _IE is applied, and t (V _A ) represents the time length (unit: second) in which the maximum voltage value V _A is applied to the anode electrode.

As the value of V _G-MIN in the method according to the first aspect of the present invention, 0 it is most preferable to employ a bolt, is not limited to this, even if a positive value at a negative value There may be. The value of V _G-MAX may be a voltage approximately equal to the maximum value of the pulse voltage v _G applied to the gate electrode during the actual operation of the cold cathode field emission display. The constant voltages V _IE and V _A applied to the inspection electrode or the anode electrode are higher than the DC voltage v _A applied to the anode electrode during actual operation of the cold cathode field emission display device. For example, it is preferable that 1.2 v _A ≦ V _IE and V _A ≦ 2.0 v _A are satisfied.

As the value of V _G in the method according to the second aspect of the present invention, 0 it is most preferable to employ a bolt, it is not limited thereto, a negative value is also a positive value Also good. The constant voltage or maximum voltage values V _IE and V _A applied to the inspection electrode or the anode electrode are higher than the DC voltage v _A applied to the anode electrode during the actual operation of the cold cathode field emission display. For example, it is preferable that 1.2 v _A ≦ V _IE and V _A ≦ 2.0 v _A are satisfied. The minimum voltage values V _IE-MIN and V _A-MIN preferably satisfy, for example, 0 ≦ V _IE-MIN and V _A-MIN ≦ 0.1 v _A.

  In the method according to the first aspect of the present invention or the method according to the second aspect of the present invention, the field frequency T (Hz) may be 60 Hz, for example.

Cold cathode field emission devices (hereinafter abbreviated as field emission devices)
(A) a strip-shaped cathode electrode formed on the support and extending in the first direction;
(B) an insulating layer formed on the cathode electrode and the support;
(C) a strip-shaped gate electrode formed on the insulating layer and extending in a second direction different from the first direction;
(D) an opening provided in a portion of the gate electrode and the insulating layer located in an overlapping region where the cathode electrode and the gate electrode overlap, and an exposed portion of the cathode electrode at the bottom; and
(E) an electron emission portion provided on the cathode electrode exposed at the bottom of the opening,
Consists of.

  In the method according to the first aspect of the present invention, the type of the field emission device is not particularly limited, and the Spindt-type field emission device (the conical electron emission portion is provided on the cathode electrode positioned at the bottom of the opening). Field emission devices) and flat type field emission devices (field emission devices in which a substantially planar electron emission portion is provided on the cathode electrode located at the bottom of the opening). Moreover, a flat type field emission device can be mentioned as a type of the field emission device in the method according to the second aspect of the present invention.

  From the viewpoint of simplifying the structure of the cold cathode field emission display, the projected image of the cathode electrode and the projected image of the gate electrode are orthogonal, that is, the first direction and the second direction are orthogonal. To preferred. In the cathode panel, the electron emission regions are arranged in a two-dimensional matrix, and each electron emission region is provided with one or a plurality of field emission elements. When the number of gate electrodes formed on the cathode panel is M and the number of cathode electrodes is N, the number of electron emission regions is M × N.

Then, in the method according to the first aspect of the present invention, at the same time to all of the N cathode electrodes, and always in a state of applying a constant voltage V _C, the first gate electrode, the second , The third gate electrode,..., The (M−1) th gate electrode, and the Mth gate electrode are sequentially applied with a pulsed voltage, and then the first gate electrode is again applied to the first gate electrode. A pulsed voltage is sequentially applied to the first gate electrode, the second gate electrode, the third gate electrode,..., The (M−1) th gate electrode, and the Mth gate electrode. You just have to repeat the operation. Alternatively, alternatively, a process in which a pulsed voltage is simultaneously applied to the collected m gate electrodes may be employed. On the other hand, in the method according to the second aspect of the present invention, the inspection electrodes are applied with the constant voltages V _G and V _C applied to the M gate electrodes and the N cathode electrodes at the same time. Alternatively, V _IE and V _A are applied to the anode electrode.

A field emission device is generally manufactured by the following method.
(1) forming a cathode electrode on a support;
(2) forming an insulating layer on the entire surface (on the support and the cathode electrode);
(3) forming a gate electrode on the insulating layer;
(4) forming an opening in a portion of the gate electrode and the insulating layer in a region where the cathode electrode and the gate electrode overlap, and exposing the cathode electrode at the bottom of the opening;
(5) A step of forming an electron emission portion on the cathode electrode located at the bottom of the opening.

Alternatively, the field emission device can be manufactured by the following method.
(1) forming a cathode electrode on a support;
(2) forming an electron emission portion on the cathode electrode;
(3) forming an insulating layer on the entire surface (on the support and the electron emission portion or on the support, the cathode electrode and the electron emission portion);
(4) forming a gate electrode on the insulating layer;
(5) A step of forming an opening in a portion of the gate electrode and the insulating layer in the overlapping region of the cathode electrode and the gate electrode, and exposing the electron emission portion at the bottom of the opening.

  The field emission device may be provided with a focusing electrode. That is, a field emission element in which an interlayer insulating layer is further provided on the gate electrode and the insulating layer, and a focusing electrode is provided on the interlayer insulating layer, or an electric field in which the focusing electrode is provided above the gate electrode. It can also be an emitting element. Here, the focusing electrode is an electrode for converging the trajectory of emitted electrons that are emitted from the opening and directed toward the anode electrode, thereby improving the luminance and preventing optical crosstalk between adjacent pixels. It is. In a so-called high-voltage type cold cathode field emission display device in which the potential difference between the anode electrode and the cathode electrode is on the order of several kilovolts and the distance between the anode electrode and the cathode electrode is relatively long, the focusing electrode Is particularly effective. A relative negative voltage is applied to the focusing electrode from the focusing electrode control circuit. The focusing electrode is not necessarily provided for each field emission element. For example, by extending the field emission elements along a predetermined arrangement direction of the field emission elements, a convergence effect common to a plurality of field emission elements is exerted. You can also

  In the Spindt-type field emission device, the material constituting the electron emission portion is molybdenum, molybdenum alloy, tungsten, tungsten alloy, titanium, titanium alloy, niobium, niobium alloy, tantalum, tantalum alloy, chromium, chromium alloy, and And at least one material selected from the group consisting of silicon (polysilicon and amorphous silicon) containing impurities. The electron emission portion of the Spindt-type field emission device can be formed by, for example, a sputtering method or a CVD method in addition to the vacuum evaporation method.

In the flat field emission device, it is preferable that the material constituting the electron emission portion is composed of a material having a work function Φ smaller than that of the material constituting the cathode electrode. What is necessary is just to determine based on the work function of the material which comprises a cathode electrode, the electric potential difference between a gate electrode and a cathode electrode, the magnitude | size of the emission electron current density requested | required, etc. As typical materials constituting the cathode electrode in the field emission device, tungsten (Φ = 4.55 eV), niobium (Φ = 4.02 to 4.87 eV), molybdenum (Φ = 4.53 to 4.95 eV), Examples include aluminum (Φ = 4.28 eV), copper (Φ = 4.6 eV), tantalum (Φ = 4.3 eV), and chromium (Φ = 4.5 eV). The electron emission portion preferably has a work function Φ smaller than these materials, and the value is preferably approximately 3 eV or less. Such materials include carbon (Φ <1 eV), cesium (Φ = 2.14 eV), LaB ₆ (Φ = 2.66-2.76 eV), BaO (Φ = 1.6-2.7 eV), SrO (Φ = 1.25 to 1.6 eV), Y ₂ O ₃ (Φ = 2.0 eV), CaO (Φ = 1.6 to 1.86 eV), BaS (Φ = 2.05 eV), TiN (Φ = 2. 92 eV) and ZrN (Φ = 2.92 eV). More preferably, the electron emission portion is made of a material having a work function Φ of 2 eV or less. In addition, the material which comprises an electron emission part does not necessarily need to be provided with electroconductivity.

Alternatively, in the flat type field emission device, as a material constituting the electron emission portion, a material in which the secondary electron gain δ of the material is larger than the secondary electron gain δ of the conductive material constituting the cathode electrode is used. You may select suitably. That is, silver (Ag), aluminum (Al), gold (Au), cobalt (Co), copper (Cu), molybdenum (Mo), niobium (Nb), nickel (Ni), platinum (Pt), tantalum (Ta) ), Metals such as tungsten (W), zirconium (Zr); semiconductors such as germanium (Ge); inorganic simple substances such as carbon and diamond; and aluminum oxide (Al ₂ O ₃ ), barium oxide (BaO), beryllium oxide ( BeO), calcium oxide (CaO), magnesium oxide (MgO), tin oxide (SnO ₂ ), barium fluoride (BaF ₂ ), calcium fluoride (CaF ₂ ) and other compounds can be selected as appropriate. . In addition, the material which comprises an electron emission part does not necessarily need to be provided with electroconductivity.

Alternatively, in the flat type field emission device, carbon, more specifically, amorphous diamond, graphite, carbon nanotube structure, ZnO whisker, MgO whisker, SnO ₂ whisker is particularly preferable as a constituent material of the electron emission part. , MnO whiskers, Y ₂ O ₃ whiskers, NiO whiskers, ITO whiskers, In ₂ O ₃ whiskers, and Al ₂ O ₃ whiskers. When the electron emission portion is composed of these, the emission electron current density required for the cold cathode field emission display device can be obtained with an electric field intensity of 5 × 10 ⁶ V / m or less. Further, if the material constituting the electron emission portion is an electric resistor, the emission electron current obtained from each electron emission portion can be made uniform, and accordingly, when incorporated in a cold cathode field emission display device. Luminance variation can be suppressed. Furthermore, since these materials have extremely high resistance to the sputtering effect by ions of residual gas in the cold cathode field emission display, the lifetime of the field emission device can be extended.

  Specific examples of the carbon nanotube structure include carbon nanotubes and / or graphite nanofibers. More specifically, the electron emission part may be composed of carbon nanotubes, the electron emission part may be composed of graphite nanofibers, or the electron emission is performed from a mixture of carbon nanotubes and graphite nanofibers. You may comprise a part. Macroscopically, carbon nanotubes and graphite nanofibers may be in the form of powder or thin film. In some cases, the carbon nanotube structure has a conical shape. It may be. Carbon nanotubes and graphite nanofibers are produced by various CVD methods such as the well-known arc discharge method and laser ablation method, such as PVD method, plasma CVD method, laser CVD method, thermal CVD method, vapor phase synthesis method, and vapor phase growth method. Can be manufactured and formed.

  A desired region of the cathode electrode (for example, the bottom of the opening) is obtained by dispersing the carbon nanotube structure or the above-mentioned various whiskers (hereinafter collectively referred to as carbon nanotube structure) in a binder material. For example, a method of baking or curing a binder material after being applied to a cathode electrode portion (specifically, an organic binder material such as an epoxy resin or an acrylic resin, a silver paste, a nickel paste) For example, a conductive paste such as water glass or an inorganic binder material dispersed in a carbon / nanotube structure is applied to a desired area of the cathode electrode, and then the solvent is removed, and the binder material or conductive paste is baked. A flat type field emission device can also be manufactured by a method of curing. Such a method is referred to as a first method for forming a carbon nanotube structure or the like. An example of the application method is a screen printing method.

Alternatively, a flat type field emission device can be manufactured by applying a metal compound solution in which a carbon nanotube structure or the like is dispersed to a desired region of the cathode electrode and then firing the metal compound. The carbon nanotube structure or the like is fixed on a desired region of the cathode electrode with a matrix derived from metal atoms constituting the metal compound. Such a method is referred to as a second method for forming a carbon nanotube structure or the like. The matrix is preferably composed of a conductive metal oxide, and more specifically composed of tin oxide, indium oxide, indium oxide-tin, zinc oxide, antimony oxide, or antimony-tin oxide. preferable. After firing, a state in which a part of each carbon / nanotube structure or the like is embedded in the matrix can be obtained, or a state in which each carbon / nanotube structure or the like is entirely embedded in the matrix can be obtained. The volume resistivity of the matrix is preferably 1 × 10 ⁻⁹ (Ω · m) to 5 × 10 ⁻⁶ (Ω · m).

  As a metal compound which comprises a metal compound solution, an organic metal compound, an organic acid metal compound, or a metal salt (for example, chloride, nitrate, acetate) can be mentioned, for example. Specifically, as a metal compound solution composed of an organic acid metal compound, an organic tin compound, an organic indium compound, an organic zinc compound, or an organic antimony compound is dissolved in an acid (for example, hydrochloric acid, nitric acid, or sulfuric acid). Can be mentioned which are diluted with an organic solvent (for example, toluene, butyl acetate, isopropyl alcohol). In addition, as a metal compound solution composed of an organometallic compound, specifically, an organic tin compound, an organic indium compound, an organic zinc compound, and an organic antimony compound are dissolved in an organic solvent (for example, toluene, butyl acetate, isopropyl alcohol). Can be illustrated. When the metal compound solution is 100 parts by weight, it is preferable to have a composition containing 0.001 to 20 parts by weight of the carbon / nanotube structure and 0.1 to 10 parts by weight of the metal compound. The metal compound solution may contain a dispersant or a surfactant. Further, from the viewpoint of increasing the thickness of the matrix, an additive such as carbon black may be added to the metal compound solution. Moreover, depending on the case, water can also be used as a solvent instead of an organic solvent.

  Examples of a method for applying a metal compound solution in which a carbon nanotube structure or the like is dispersed on a desired region of a cathode electrode include a spray method, a spin coating method, a dipping method, a diquarter method, and a screen printing method. However, it is preferable to use the spray method from the viewpoint of easy application.

  After a metal compound solution in which a carbon nanotube structure or the like is dispersed is applied on a desired region of the cathode electrode, the metal compound solution is dried to form a metal compound layer, and then the metal compound layer on the cathode electrode After removing the unnecessary portion of the metal compound, the metal compound may be fired, or after firing the metal compound, the unnecessary portion on the cathode electrode may be removed, or only on a desired region of the cathode electrode. A solution may be applied.

  The firing temperature of the metal compound is, for example, a temperature at which the metal salt is oxidized to form a conductive metal oxide, or an organic metal compound or an organic acid metal compound is decomposed to form an organic metal compound or an organic acid. Any temperature can be used as long as it can form a matrix derived from metal atoms constituting the metal compound (for example, a conductive metal oxide). For example, the temperature is preferably 300 ° C. or higher. The upper limit of the firing temperature may be a temperature at which thermal damage or the like does not occur in the constituent elements of the field emission device or the cathode panel.

  In the first formation method or the second formation method of the carbon nanotube structure or the like, after the formation of the electron emission portion, a kind of activation treatment (cleaning treatment) of the surface of the electron emission portion is performed. This is preferable from the viewpoint of further improving the efficiency of electron emission from the electron emission portion. Examples of such treatment include plasma treatment in a gas atmosphere such as hydrogen gas, ammonia gas, helium gas, argon gas, neon gas, methane gas, ethylene gas, acetylene gas, and nitrogen gas.

  In the first formation method or the second formation method of the carbon nanotube structure or the like, the electron emission portion may be formed at the cathode electrode portion located at the bottom of the opening portion. You may form so that it may extend from the part of the cathode electrode located in the bottom part to parts of the cathode electrode other than the bottom part of an opening part. In addition, the electron emission portion may be formed on the entire surface of the portion of the cathode electrode located at the bottom of the opening or may be formed partially.

  It is preferable to orient the tip of the carbon nanotube structure or the like in the direction approaching the normal direction of the support as much as possible. By achieving such a state, it is possible to improve the electron emission characteristics of the electron emission portion and make the electron emission characteristics uniform. As a method for achieving such a state, a method disclosed in Japanese Patent Laid-Open No. 2003-168355 can be exemplified. That is, a composite layer in which a carbon nanotube structure or the like is embedded in a matrix (also called a base material or a base material) on a desired region of the cathode electrode is formed, and then a release layer is attached to the surface of the composite layer Then, the peeling layer is mechanically peeled off to obtain an electron emission portion in which the carbon nanotube structure or the like is embedded in the matrix with the tip portion protruding.

The constituent materials of the cathode electrode, gate electrode, and focusing electrode are aluminum (Al), tungsten (W), niobium (Nb), tantalum (Ta), molybdenum (Mo), chromium (Cr), copper (Cu), gold ( Metals such as Au), silver (Ag), titanium (Ti), nickel (Ni), cobalt (Co), zirconium (Zr), iron (Fe), platinum (Pt), zinc (Zn); these metal elements Alloys (eg, MoW) or compounds (eg, nitrides such as TiN, silicides such as WSi ₂ , MoSi ₂ , TiSi ₂ , TaSi ₂ ); semiconductors such as silicon (Si); carbon thin films such as diamond; ITO ( Examples thereof include conductive metal oxides such as indium oxide-tin oxide, indium oxide, and zinc oxide. In addition, as a method for forming these electrodes, for example, a vapor deposition method such as an electron beam vapor deposition method or a hot filament vapor deposition method, a sputtering method, a combination of a CVD method, an ion plating method and an etching method; a screen printing method; Plating method and electroless plating method); lift-off method; laser ablation method; sol-gel method and the like. According to the screen printing method or the plating method, for example, a strip-like cathode electrode or gate electrode can be formed directly.

As a material for constituting the insulating layer and the interlayer insulating _{layer, SiO 2, BPSG, PSG,} BSG, AsSG, PbSG, SiON, SOG ( spin on glass), low-melting glass, SiO ₂ based materials such glass paste; SiN-based materials; polyimide These insulating resins can be used alone or in appropriate combination. For forming the insulating layer or the interlayer insulating layer, a known process such as a CVD method, a coating method, a sputtering method, or a screen printing method can be used.

  Planar shape of the first opening (opening formed in the gate electrode) or the second opening (opening formed in the insulating layer) (shape when the opening is cut in a virtual plane parallel to the support surface) ) Can be any shape such as a circle, an ellipse, a rectangle, a polygon, a rounded rectangle, a rounded polygon. The formation of the first opening can be performed by, for example, anisotropic etching, isotropic etching, a combination of anisotropic etching and isotropic etching, or, depending on the method of forming the gate electrode, The first opening can also be formed directly. The second opening can also be formed by, for example, anisotropic etching, isotropic etching, or a combination of anisotropic etching and isotropic etching.

  In the field emission device, depending on the structure of the field emission device, one electron emission portion may exist in one opening, or a plurality of electron emission portions may exist in one opening. In addition, a plurality of first openings are provided in the gate electrode, one second opening communicating with the first opening is provided in the insulating layer, and one or more are provided in one second opening provided in the insulating layer. There may be an electron emission portion.

In the field emission device, a resistor layer may be provided between the cathode electrode and the electron emission portion. By providing the resistor layer, it is possible to stabilize the operation of the field emission device and make the electron emission characteristics uniform. As a material constituting the resistor layer, a carbon-based material such as silicon carbide (SiC) or SiCN, a semiconductor material such as SiN or amorphous silicon, or a refractory metal oxide such as ruthenium oxide (RuO ₂ ), tantalum oxide, or tantalum nitride. It can be illustrated. Examples of the method for forming the resistor layer include a sputtering method, a CVD method, and a screen printing method. The electric resistance value per one electron emitting portion is approximately 1 × 10 ⁶ to 1 × 10 ¹¹ Ω, preferably several tens of gigaΩ.

As a support constituting the cathode panel or as a substrate constituting the anode panel, a glass substrate, a glass substrate with an insulating film formed on the surface, a quartz substrate, a quartz substrate with an insulating film formed on the surface, and a surface Examples of the semiconductor substrate include an insulating film. From the viewpoint of reducing manufacturing costs, it is preferable to use a glass substrate or a glass substrate having an insulating film formed on the surface. As a glass substrate, high strain point glass, soda glass (Na ₂ O · CaO · SiO ₂ ), borosilicate glass (Na ₂ O · B ₂ O ₃ · SiO ₂ ), forsterite (2MgO · SiO ₂ ), lead glass (Na ₂ O · PbO · SiO ₂ ) can be exemplified.

  In the cold cathode field emission display, as an example of the configuration of the anode electrode and the phosphor region, (1) a configuration in which the anode electrode is formed on the substrate and the phosphor region is formed on the anode electrode, (2) the substrate An example is a configuration in which a phosphor region is formed and an anode electrode is formed on the phosphor region. In the configuration (1), a so-called metal back film that is electrically connected to the anode electrode may be formed on the phosphor region. In the configuration (2), a metal back film may be formed on the anode electrode.

The anode electrode may be composed of one anode electrode as a whole, or may be composed of a plurality of anode electrode units. In the latter case, the anode electrode unit and the anode electrode unit need to be electrically connected by a resistor film. Resistor films are made of carbon-based materials such as silicon carbide (SiC) and SiCN; SiN-based materials; refractory metal oxides such as ruthenium oxide (RuO ₂ ), tantalum oxide, tantalum nitride, chromium oxide, and titanium oxide A semiconductor material such as amorphous silicon. Examples of the sheet resistance value of the resistor film include 1 × 10 ⁻¹ Ω / □ to 1 × 10 ¹⁰ Ω / □, preferably 1 × 10 ³ Ω / □ to 1 × 10 ⁸ Ω / □. The number (Q) of anode electrode units may be two or more. For example, when the total number of phosphor regions arranged in a straight line is q columns, Q = q or q = k · Q (K is an integer of 2 or more, preferably 10 ≦ k ≦ 100, more preferably 20 ≦ k ≦ 50), and 1 is set as the number of spacers (described later) arranged at a constant interval. It can be an added number, or it can be a number that matches the number of pixels or subpixels, or an integer fraction of the number of pixels or subpixels. The size of each anode electrode unit may be the same regardless of the position of the anode electrode unit, or may vary depending on the position of the anode electrode unit.

The anode electrode (including the anode electrode unit) may be formed using a conductive material layer. As a method for forming the conductive material layer, for example, various PVD methods such as an evaporation method such as an electron beam evaporation method and a hot filament evaporation method, a sputtering method, an ion plating method, and a laser ablation method; various CVD methods; a screen printing method; Sol-gel method and the like. That is, it is possible to form an anode electrode by forming a conductive material layer made of a conductive material and patterning the conductive material layer based on a lithography technique and an etching technique. Alternatively, the anode electrode can be obtained by forming a conductive material based on a PVD method or a screen printing method through a mask or screen having an anode electrode pattern. The resistor film can also be formed by the same method. That is, a resistor film may be formed from a resistor material, and the resistor film may be patterned based on lithography technology and etching technology, or the resistor material may be provided via a mask or screen having a resistor film pattern. A resistor film can be obtained by formation based on the PVD method or the screen printing method. 3 × 10 ⁻⁸ m (30 nm) to 1 as the average thickness of the anode electrode on the substrate (or above the substrate) (when the partition is provided as described later, the average thickness of the anode electrode on the top surface of the partition) And 5 × 10 ⁻⁷ m (150 nm), preferably 5 × 10 ⁻⁸ m (50 nm) to 1 × 10 ⁻⁷ m (100 nm). The configuration of the inspection electrode can be the same as that of the anode electrode, for example.

The constituent material of the anode electrode may be appropriately selected according to the configuration of the cold cathode field emission display. That is, when the cold cathode field emission display is a transmission type (the anode panel corresponds to the display surface), and the anode electrode and the phosphor region are laminated in this order on the substrate, the substrate is Originally, the anode electrode itself needs to be transparent, and a transparent conductive material such as ITO (indium tin oxide) is used. On the other hand, when the cold cathode field emission display is of a reflective type (the cathode panel corresponds to the display surface), and even in the transmissive type, the phosphor region and the anode electrode are laminated in this order on the substrate. In this case, molybdenum (Mo), aluminum (Al), chromium (Cr), tungsten (W), niobium (Nb), tantalum (Ta), gold (Au), silver (Ag), titanium (Ti), Metals such as cobalt (Co), zirconium (Zr), iron (Fe), platinum (Pt), zinc (Zn); alloys or compounds containing these metal elements (for example, nitrides such as TiN, WSi ₂ , MoSi _2, TiSi _2, silicides such as TaSi _2); thin carbon film such as diamond; silicon (semiconductor Si) such as ITO (indium - tin), indium oxide, conductive zinc oxide, etc. It can be exemplified genus oxide. When the resistor film is formed, the anode electrode is preferably made of a conductive material that does not change the resistance value of the resistor film. For example, when the resistor film is made of silicon carbide (SiC), the anode electrode is It is preferable to comprise from molybdenum (Mo).

  The phosphor region may be composed of monochromatic phosphor particles or may be composed of three primary color phosphor particles. Further, the phosphor region may be arranged in a dot shape or a belt shape. In the dot-like or belt-like arrangement pattern, a gap between adjacent phosphor regions may be embedded with a light absorption layer (black matrix) for the purpose of improving contrast.

  When the cold cathode field emission display is in color display, one row of the phosphor regions arranged in a straight line is a row occupied by the red light emitting phosphor region and a row occupied by the green light emitting phosphor region. And a row occupied by the blue light-emitting phosphor region, or a row in which the red light-emitting phosphor region, the green light-emitting phosphor region, and the blue light-emitting phosphor region are sequentially arranged. It may be. Here, the phosphor region is defined as a phosphor region that generates one bright spot on the anode panel. One pixel (one pixel) is composed of a set of one red light emitting phosphor region, one green light emitting phosphor region, and one blue light emitting phosphor region, and one subpixel is one phosphor. The region is composed of one red light emitting phosphor region, one green light emitting phosphor region, or one blue light emitting phosphor region. Furthermore, the size corresponding to one subpixel in the anode electrode unit means the size of the anode electrode unit surrounding one phosphor region.

  For the phosphor region, a luminescent crystal particle composition prepared from luminescent crystal particles (for example, phosphor particles having a particle size of about 5 to 10 nm) is used. For example, a red photosensitive luminescent crystal particle composition is used. (Red phosphor slurry) is applied to the entire surface, exposed and developed to form a red light emitting phosphor region, and then a green photosensitive luminescent crystal particle composition (green phosphor slurry) is applied to the entire surface. Then, it is exposed to light and developed to form a green light emitting phosphor region. Further, a blue photosensitive luminescent crystal particle composition (blue phosphor slurry) is coated on the entire surface, exposed to light and developed to emit blue light. It can be formed by a method of forming a phosphor region. Although the average thickness of the phosphor region on the substrate is not limited, it is desirably 3 μm to 20 μm, preferably 5 μm to 10 μm.

The phosphor material constituting the luminescent crystal particles can be appropriately selected from conventionally known phosphor materials. In the case of color display, a phosphor material whose color purity is close to the three primary colors specified by NTSC, white balance is achieved when the three primary colors are mixed, the afterglow time is short, and the afterglow time of the three primary colors is almost equal. It is preferable to combine them. As phosphor materials constituting the red light emitting phosphor region, (Y ₂ O ₃ : Eu), (Y ₂ O ₂ S: Eu), (Y ₃ Al ₅ O ₁₂ : Eu), (Y ₂ SiO ₅ : Eu) ) And (Zn ₃ (PO ₄ ) ₂ : Mn) can be exemplified, among which (Y ₂ O ₃ : Eu) and (Y ₂ O ₂ S: Eu) are preferably used. Further, as phosphor materials constituting the green light emitting phosphor region, (ZnSiO ₂ : Mn), (Sr ₄ Si ₃ O ₈ Cl ₄ : Eu), (ZnS: Cu, Al), (ZnS: Cu, Au, Al), [(Zn, Cd) S: Cu, Al], (Y ₃ Al ₅ O ₁₂ : Tb), (Y ₂ SiO ₅ : Tb), [Y ₃ (Al, Ga) ₅ O ₁₂ : Tb] , (ZnBaO ₄ : Mn), (GbBO ₃ : Tb), (Sr ₆ SiO ₃ Cl ₃ : Eu), (BaMgAl ₁₄ O ₂₃ : Mn), (ScBO ₃ : Tb), (Zn ₂ SiO ₄ : Mn) , (ZnO: Zn), (Gd ₂ O ₂ S: Tb), and (ZnGa ₂ O ₄ : Mn), (ZnS: Cu, Al), (ZnS: Cu, Au, Al), [(Zn, Cd ) S: Cu, Al], (Y 3 Al 5 O 12: Tb), [Y 3 ( _{l, Ga) 5 O 12:} Tb], (Y 2 SiO 5: it is preferable to use a Tb). Further, as phosphor materials constituting the blue light emitting phosphor region, (Y ₂ SiO ₅ : Ce), (CaWO ₄ : Pb), CaWO ₄ , YP _0.85 V _0.15 O ₄ , (BaMgAl ₁₄ O ₂₃ : Eu) , (Sr ₂ P ₂ O ₇ : Eu), (Sr ₂ P ₂ O ₇ : Sn), (ZnS: Ag, Al), (ZnS: Ag), ZnMgO, and ZnGaO _4. , (ZnS: Ag), (ZnS: Ag, Al) are preferably used.

  In the anode panel, electrons rebounding from the phosphor region or secondary electrons emitted from the phosphor region are incident on another phosphor region, and so-called optical crosstalk (color turbidity) is generated. In order to prevent this, or when an electron recoiled from the phosphor region or a secondary electron emitted from the phosphor region enters the other phosphor region beyond the barrier, these It is preferable that a plurality of partition walls are provided to prevent electrons from colliding with other phosphor regions.

  Examples of the planar shape of the partition walls include a lattice shape (cross-beam shape), that is, a shape corresponding to one subpixel, for example, a shape surrounding the four sides of a phosphor region having a substantially rectangular shape (dot shape), or A belt-like shape extending in parallel with two opposite sides of the substantially rectangular or belt-like phosphor region can be exemplified. In the case where the partition walls have a lattice shape, a shape that continuously surrounds four sides of one phosphor region may be used, or a shape that discontinuously surrounds them. When the partition wall has a strip shape, it may have a continuous shape or a discontinuous shape. After the partition wall is formed, the partition wall may be polished to flatten the top surface of the partition wall.

  Examples of the partition wall forming method include a screen printing method, a dry film method, a photosensitive method, and a sandblast forming method. Here, in the screen printing method, an opening is formed in a portion of the screen corresponding to a portion where a partition is to be formed, and the partition forming material on the screen is passed through the opening using a squeegee, and the partition is formed on the substrate. In this method, after the formation material layer is formed, the partition wall formation material layer is fired. The dry film method is a method of laminating a photosensitive film on a substrate, removing the photosensitive film at the part where the partition wall is to be formed by exposure and development, embedding a material for forming the partition wall in the opening formed by the removal, and baking. is there. The photosensitive film is burned and removed by baking, and the partition wall-forming material embedded in the openings remains to form partition walls. The photosensitive method is a method in which a barrier rib-forming material layer having photosensitivity is formed on a substrate, the barrier rib-forming material layer is patterned by exposure and development, and then fired. The sand blast forming method is, for example, for forming partition walls on which a partition wall forming material layer is formed on a substrate by using screen printing, a roll coater, a doctor blade, a nozzle discharge type coater or the like and dried. In this method, the material layer portion is covered with a mask layer, and then the exposed partition wall forming material layer portion is removed by sandblasting.

A light absorption layer that absorbs light from the phosphor region is preferably formed between the partition wall and the substrate from the viewpoint of improving the contrast of the display image. Here, the light absorption layer functions as a so-called black matrix. As a material constituting the light absorption layer, it is preferable to select a material that absorbs 99% or more of light from the phosphor region. Such materials include carbon, metal thin films (eg, chromium, nickel, aluminum, molybdenum, etc., or alloys thereof), metal oxides (eg, chromium oxide), metal nitrides (eg, chromium nitride), heat resistance Materials such as photosensitive organic resins, glass pastes, glass pastes containing conductive particles such as black pigments and silver, and specifically, photosensitive polyimide resins, chromium oxides, and chromium oxide / chromium laminated films Can be illustrated. In the chromium oxide / chromium laminated film, the chromium film is in contact with the substrate. Light absorbing layer, for example, a combination of a vacuum evaporation method or a sputtering method and an etching method, a vacuum evaporation method or a sputtering method, set combined with a spin coating method and a lift-off method, a screen printing method, a lithography technique or the like, the materials used It can be formed by a method appropriately selected depending on the method.

In the cold cathode field emission display device, since the space between the anode panel and the cathode panel is in a vacuum state (pressure P ₀ ), a spacer is arranged between the anode panel and the cathode panel. Otherwise, the cold cathode field emission display may be damaged by atmospheric pressure. The spacer can be made of ceramics, for example. When the spacer is made of ceramics, the ceramics include mullite, alumina, barium titanate, lead zirconate titanate, zirconia, cordiolite, borosilicate barium, iron silicate, glass ceramic materials, titanium oxide and chromium oxide. , Iron oxide, vanadium oxide, nickel oxide added, and the like. In this case, a spacer can be manufactured by forming a so-called green sheet, firing the green sheet, and cutting the fired green sheet. Further, a conductive material layer made of metal or alloy may be formed on the surface of the spacer, or a high resistance layer may be formed, or a thin layer made of a material having a low secondary electron emission coefficient may be formed. . For example, the spacer may be fixed by being sandwiched between the partition walls, or alternatively, for example, by forming a spacer holding portion on the anode panel and sandwiching and fixing between the spacer holding portion and the spacer holding portion. Good.

  In the cold cathode field emission display, a strong electric field generated by a voltage applied to the cathode electrode and the gate electrode is applied to the electron emission portion, and as a result, electrons are emitted from the electron emission portion by the quantum tunnel effect. The electrons are attracted to the anode panel by the anode electrode provided on the anode panel, and collide with the phosphor region. As a result of the collision of electrons with the phosphor region, the phosphor region emits light and can be recognized as an image.

In the cold cathode field emission display, the cathode electrode is connected to the cathode electrode control circuit, the gate electrode is connected to the gate electrode control circuit, and the anode electrode is connected to the anode electrode control circuit. Note that these control circuits can be constituted by known circuits. During actual operation, the output voltage v _A of the anode electrode control circuit is normally constant, and can be, for example, 5 kilovolts to 10 kilovolts. Alternatively, when the distance between the anode panel and the cathode panel is d (where 0.5 mm ≦ d ≦ 10 mm), the value of v _A / d (unit: kilovolt / mm) is 0.5 or more and 20 Hereinafter, it is desirable to satisfy 1 or more and 10 or less, and more preferably 5 or more and 10 or less.

In the actual operation of the cold cathode field emission display device, regarding the voltage v _C applied to the cathode electrode and the voltage v _G applied to the gate electrode, when the voltage modulation method is adopted as the gradation control method,
(1) A method of changing the voltage v _G applied to the gate electrode while keeping the voltage v _C applied to the cathode electrode constant (2) A voltage v _G applied to the gate electrode by changing the voltage v _C applied to the cathode electrode (3) There is a method in which the voltage v _C applied to the cathode electrode is changed and the voltage v _G applied to the gate electrode is also changed.

The cathode panel and the anode panel are joined at the peripheral edge. The joining may be performed using an adhesive layer, or a frame made of an insulating rigid material such as glass or ceramics and an adhesive layer are used in combination. May be. When using a frame and an adhesive layer together, the opposing distance between the cathode panel and the anode panel is set longer than when only the adhesive layer is used by appropriately selecting the height of the frame. Is possible. As a constituent material of the adhesive layer, frit glass is generally used, but a so-called low melting point metal material having a melting point of about 120 to 400 ° C. may be used. Such low melting point metal materials include In (indium: melting point 157 ° C.); indium-gold based low melting point alloy; Sn ₈₀ Ag ₂₀ (melting point 220-370 ° C.), Sn ₉₅ Cu ₅ (melting point 227-370 °). C) tin (Sn) -based high-temperature solder; Pb _97.5 Ag _2.5 (melting point 304 ° C.), Pb _94.5 Ag _5.5 (melting point 304 to 365 ° C.), Pb _97.5 Ag _1.5 Sn _1.0 (melting point 309 ° C.), etc. Lead (Pb) -based high-temperature solder; zinc (Zn) -based high-temperature solder such as Zn ₉₅ Al ₅ (melting point 380 ° C.); Sn ₅ Pb ₉₅ (melting point 300-314 ° C.), Sn ₂ Pb ₉₈ (melting point 316-322) Tin-lead standard solder such as ° C); brazing material such as Au ₈₈ Ga ₁₂ (melting point 381 ° C) (the above subscripts all represent atomic%).

  When joining the three of the cathode panel, the anode panel and the frame, the three may be joined at the same time, or in the first stage, either the cathode panel or the anode panel and the frame are joined, In the second stage, the other of the cathode panel or the anode panel and the frame may be joined. When the three-party simultaneous bonding or the second-stage bonding is performed in a high vacuum atmosphere, the space surrounded by the cathode panel, the anode panel, the frame, and the adhesive layer becomes a vacuum simultaneously with the bonding. Alternatively, the space surrounded by the cathode panel, the anode panel, the frame body, and the adhesive layer can be exhausted and vacuumed after the completion of the joining of the three parties. When the conditioning method of the cold cathode field emission display according to the first aspect or the second aspect of the present invention is performed after bonding, and then evacuation is performed, the atmospheric pressure at the time of bonding is either normal pressure or reduced pressure. The gas constituting the atmosphere may be air or an inert gas containing nitrogen gas or a gas belonging to group 0 of the periodic table (for example, Ar gas).

  When exhaust is performed, exhaust can be performed through a tip tube connected in advance to the cathode panel and / or the anode panel. The tip tube is typically configured by using a glass tube, and an ineffective area of the cathode panel and / or the anode panel (a display area in the central portion that performs a practical function as a cold cathode field emission display device) It is joined to the periphery of the through-hole provided in the frame-like region) using frit glass or the above-mentioned low melting point metal material, and after the space has reached a predetermined degree of vacuum, it is sealed by thermal fusion. Cut off. In addition, if the entire cold cathode field emission display is once heated and then cooled before sealing, the residual gas can be released into the space, and the residual gas can be removed out of the space by exhaust. This is preferable.

  As combinations of the cathode panel conditioning method and the cold cathode field emission display device according to the present invention, the combinations shown in Table 1 below can be given.

In the cathode panel conditioning method, the cold cathode field emission display device conditioning method, and the cold cathode field emission display device manufacturing method according to the first aspect of the present invention, the number of gate electrodes is M. For example, when the maximum voltage value V _G-MAX is applied to the mth gate electrode, the first to (m−1) th gate electrodes and the (m + 1) th gate electrode are applied. The minimum voltage value V _G-MIN is applied to the first to Mth gate electrodes, and this minimum voltage value V _G-MIN is lower than the voltage V _C applied to the cathode electrode. It is. Therefore, in the electron emission region included in the mth gate electrode, electrons are emitted from the electron emission portion based on the quantum tunnel effect based on an electric field generated by applying a voltage to the cathode electrode and the gate electrode. On the other hand, from the electron emission region included in the first gate electrode to the (m−1) th gate electrode and the electron emission region included in the (m + 1) th gate electrode to the Mth gate electrode. Does not emit electrons.

Thus, the cold cathode field emission device that emits electrons even in the cut-off voltage v _CUT or near existing in the electron emission region included in the m-th gate electrode (low voltage electron emitting field emission device) Then, as a result of an excessive current flowing through the electron emission portion, the function of emitting electrons can be stopped. That is, the low voltage electron emission field emission device can be removed in operation. On the other hand, the electron emission region included in the first gate electrode to the (m−1) th gate electrode and the electron emission region included in the (m + 1) th gate electrode to the Mth gate electrode No electrons are emitted from the existing low voltage electron emission field emission device. Accordingly, during the execution of the conditioning process in the cathode panel conditioning method, cold cathode field emission display device conditioning method, and cold cathode field emission display device manufacturing method according to the first aspect of the present invention, it is undesirable. The phenomenon that a direct current continues to flow between the cold cathode field emission device and the inspection electrode or anode electrode does not occur, and the cathode panel or anode caused by the temperature rise in the cold cathode field emission device or anode electrode It is possible to prevent problems such as damage to the panel, discharge breakdown in the cold cathode field emission display device and the cathode panel.

Further, in the cathode panel conditioning method, the cold cathode field emission display device conditioning method, and the cold cathode field emission display device manufacturing method according to the second aspect of the present invention, a gate electrode and an insulating layer are provided. Electrons are emitted from a substance that emits electrons left as a residue (referred to as an electron emitting substance for convenience) on the basis of the electric field formed by the voltages V _IE and V _A applied to the inspection electrode and the anode electrode. As a result, an excessive current flows through the electron-emitting material left as a residue on the gate electrode or the insulating layer, which is removed.

Moreover, the voltage V _G applied to the gate electrode is lower than the voltage V _C applied to the cathode electrode. Accordingly, no electrons are emitted from the electron emission portion. That is, during the execution of the conditioning process in the cathode panel conditioning method, the cold cathode field emission display device conditioning method, and the cold cathode field emission display device manufacturing method according to the second aspect of the present invention, The phenomenon that a direct current continues to flow between the field electron emission device and the inspection electrode or the anode electrode does not occur, and the cathode panel or the anode panel is damaged due to the temperature rise in the cold cathode field electron emission device or the anode electrode. It is possible to prevent the occurrence of problems such as generation and discharge breakdown in the cold cathode field emission display or in the cathode panel. That is, the electron-emitting substance left as a residue on the gate electrode or the insulating layer can be reliably removed without causing a problem such as damage to the cathode panel or the anode panel.

In the obtained cold cathode field emission display, even when the operation is at or near the cut-off voltage v _CUT , that is, the entire cold cathode field emission display has the darkest display. Even in such a case, there is no pixel (electron emission region) recognized as a bright spot, and an image with excellent uniformity can be obtained. Further, the manufacturing yield of the cold cathode field emission display can be improved, the process throughput is high, and no additional circuit is required to be added to the cold cathode field emission display.

  Hereinafter, the present invention will be described based on examples with reference to the drawings.

Example 1 relates to a cathode panel conditioning method according to the first aspect of the present invention and a cold cathode field emission display device manufacturing method according to the first aspect of the present invention. FIGS. 1A and 1B are conceptual diagrams of the conditioning process in the cathode panel conditioning method of the first embodiment and the cold cathode field emission display manufacturing method of the first embodiment. Here, (A) in FIG. 1 is a diagram conceptually showing a voltage application state to the cathode electrode, the gate electrode, and the inspection electrode, and (B) in FIG. A voltage V _C (indicated by a dotted line) and pulsed voltages V _G-MAX and V _G-MIN (indicated by a solid line) applied to the gate electrode are schematically illustrated.

The cold cathode field emission display device (hereinafter abbreviated as display device) and cathode panel CP in Example 1 have the same configuration and structure as the display device and cathode panel CP described with reference to FIG. 8 or FIG. . That is, FIG. 8 is a conceptual partial end view of the cathode panel CP and the display device in which the Spindt type field emission device is formed, and the conceptual diagram of the cathode panel CP and the display device in which the flat field emission device is formed. A partial end view is shown in FIG.
(A) A plurality of strip-like cathode electrodes 11 formed on the support 10 and extending in the first direction;
(B) an insulating layer 12 formed on the cathode electrode 11 and the support 10;
(C) a plurality of strip-shaped gate electrodes 13 formed on the insulating layer 12 and extending in a second direction different from the first direction;
(D) A plurality of openings 14 (provided in the gate electrode 13) that are provided in the gate electrode 13 and the insulating layer 12 located in the overlapping region where the cathode electrode 11 and the gate electrode 13 overlap and are exposed at the bottom. The first opening 14A and the second opening 14B provided in the insulating layer 12, and
(E) An electron emission region EA having electron emission portions 15 and 115 provided on the cathode electrode 11 located in the overlapping region where the cathode electrode 11 and the gate electrode 13 overlap and exposed at the bottom of the opening 14;
It has.

A cold cathode field emission device (hereinafter abbreviated as a field emission device)
(A) a strip-shaped cathode electrode 11 formed on the support 10 and extending in the first direction;
(B) an insulating layer 12 formed on the cathode electrode 11 and the support 10;
(C) a strip-shaped gate electrode 13 formed on the insulating layer 12 and extending in a second direction different from the first direction;
(D) An opening 14 (provided in the gate electrode 13) provided in a portion of the gate electrode 13 and the insulating layer 12 located in the overlapping region where the cathode electrode 11 and the gate electrode 13 overlap, with the cathode electrode 11 exposed at the bottom. 14A of 1st opening parts, 2nd opening part 14B provided in the insulating layer 12, and
(E) electron emission portions 15 and 115 provided on the cathode electrode 11 exposed at the bottom of the opening 14;
Consists of. Here, the electron emission portion 15 is a conical electron emission portion, and the electron emission portion 115 is composed of, for example, a large number of carbon nanotubes partially embedded in a matrix.

  In these display devices or cathode panels CP, the N cathode electrodes 11 have a strip shape extending in the first direction (a direction parallel to the drawing sheet), and the M gate electrodes 13 are different from the first direction. It is a strip shape extending in the second direction (direction perpendicular to the drawing sheet) (see also FIG. 10). In general, the cathode electrode 11 and the gate electrode 13 are each formed in a strip shape in a direction in which the projected images of both the electrodes 11 and 13 are orthogonal to each other. A plurality of field emission elements are provided in the electron emission area EA corresponding to one subpixel. Then, M × N such electron emission areas EA are usually arranged in a two-dimensional matrix within the effective area of the cathode panel CP (area that functions as an actual display portion).

In the display device of Example 1, the cathode panel CP and the anode panel AP are joined at their peripheral portions, and the space sandwiched between the cathode panel CP and the anode panel AP is in a vacuum state (pressure P ₀ ). ing. A schematic exploded perspective view of a part of the cathode panel CP and the anode panel AP when the cathode panel CP and the anode panel AP are disassembled is the same as that shown in FIG.

  The anode panel AP includes a substrate 20 and phosphor regions 22 formed on the substrate 20 (in the case of color display, a red light-emitting phosphor region 22R, a green light-emitting phosphor region 22G, and a blue light-emitting phosphor region 22B), The anode electrode 24 covers the phosphor region 22. That is, the anode panel AP is more specifically formed on the substrate 20 and the substrate 20 between the partition walls 21 formed on the substrate 20 and the partition walls 21, and the phosphor region 22 composed of a large number of phosphor particles. (Red light emitting phosphor region 22R, green light emitting phosphor region 22G, blue light emitting phosphor region 22B), and an anode electrode 24 formed on the phosphor region 22 are provided. The anode electrode 24 is in the form of a thin sheet that covers the effective area, and is connected to the anode electrode control circuit 33. The anode electrode 24 is made of aluminum having a thickness of about 70 nm, and is provided so as to cover the partition wall 21 and the phosphor region 22. Between the phosphor region 22 and the phosphor region 22, and between the partition wall 21 and the substrate 20, a light absorption layer (black) is used to prevent the occurrence of color turbidity and optical crosstalk in the display image. Matrix) 23 is formed.

  An example of the arrangement | positioning state of the partition 21, the spacer 25, and the fluorescent substance area | region 22 is typically shown in FIGS. The arrangement of the phosphor regions and the like in the schematic partial end view of the anode panel AP shown in FIG. 8 or FIG. 9 has the configuration shown in FIG. 12 or FIG. Also, the anode electrode is not shown in FIGS. The planar shape of the partition wall 21 is a lattice shape (cross-beam shape), that is, a shape corresponding to one subpixel, for example, a shape surrounding the four sides of the phosphor region 22 having a substantially rectangular shape (FIGS. 11, 12, 13, 14), or a belt-like shape extending in parallel with two opposing sides of the substantially rectangular (or belt-like) phosphor region 22 (see FIGS. 15 and 16). In the phosphor region 22 shown in FIG. 15, the phosphor regions 22R, 22G, and 22B can be formed in a strip shape extending in the vertical direction in FIG. A part of the partition wall 21 also functions as a spacer holding portion 26 for holding the spacer 25.

In the display device of Example 1, the cathode electrode 11 is connected to the cathode electrode control circuit 31, the gate electrode 13 is connected to the gate electrode control circuit 32, and the anode electrode 24 is connected to the anode electrode control circuit 33. These control circuits can be constituted by known circuits. During actual operation of the display device, the output voltage v _A of the anode electrode control circuit 33 is normally constant, and can be, for example, 5 kilovolts to 10 kilovolts. On the other hand, regarding the voltage v _C applied to the cathode electrode 11 and the voltage v _G applied to the gate electrode 13 during actual operation of the display device,
(1) A method in which the voltage v _C applied to the cathode electrode 11 is constant and the voltage v _G applied to the gate electrode 13 is changed. (2) The voltage v _C applied to the cathode electrode 11 is changed and applied to the gate electrode 13. the voltage v _G changing the voltage v _C is applied to the method (3) a cathode electrode 11, fixed to, and may employ any voltage v method in which _G is also changed to be applied to the gate electrode 13.

During actual operation of the display device, a relatively negative voltage is applied to the cathode electrode 11 from the cathode electrode control circuit 31, a relatively positive voltage is applied to the gate electrode 13 from the gate electrode control circuit 32, and the anode electrode 24 A positive voltage higher than that of the gate electrode 13 is applied from the anode electrode control circuit 33. When performing display in such a display device, for example, a scanning signal is input from the cathode electrode control circuit 31 to the cathode electrode 11, and a video signal is input from the gate electrode control circuit 32 to the gate electrode 13. Note that a video signal may be input to the cathode electrode 11 from the cathode electrode control circuit 31, and a scanning signal may be input to the gate electrode 13 from the gate electrode control circuit 32. Electrons are emitted from the electron emission portions 15 and 115 based on the quantum tunnel effect by an electric field generated when a voltage is applied between the cathode electrode 11 and the gate electrode 13, and the electrons are attracted to the anode electrode 24. 24 passes through and collides with the phosphor region 22. As a result, the phosphor region 22 is excited to emit light, and a desired image can be obtained. That is, the operation of this display device is basically controlled by the voltage v _G applied to the gate electrode 13 and the voltage v _C applied to the cathode electrode 11.

  FIG. 7 shows a conceptual diagram of a conditioning chamber suitable for use in Example 1 or Example 3 described later.

This chamber (conditioning device) 100 is
Housing 101 with an open top,
An inspection table 102 disposed in the housing 101 for mounting the cathode panel CP;
Vacuum means for evacuating the housing 101;
An inspection voltage (conditioning voltage) application unit 108 having a structure capable of contacting the ends of the cathode electrode 11 and the gate electrode 13;
An inspection substrate 110 which is attached to the opened upper portion of the housing 101 and has an inspection electrode (conditioning electrode) 111;
Voltage control means 112 for applying a voltage to the inspection electrode (conditioning electrode) 111, the cathode electrode 11 and the gate electrode 13,
It is composed of

  Specifically, the chamber (conditioning apparatus) 100 includes a housing 101 having an upper opening. An inspection table 102 is disposed in a housing 101 made of aluminum or stainless steel, and an inspection table elevating cylinder 103 is attached below the inspection table 102. The inspection table elevating cylinder 103 is placed on a movable base (not shown), and can be moved in the direction perpendicular to the paper surface of FIG. A pin elevating cylinder 104 is further attached below the inspection table 102, and the pin 105 moves up and down in a hole penetrating the inspection table 102 by the operation of the pin elevating cylinder 104. The housing 101 is connected to a vacuum means (not shown) including a turbo molecular pump and a dry pump through a valve 107, and the atmosphere of the housing 101 can be evacuated. In the housing 101, an inspection voltage application unit 108 having a structure capable of contacting the ends of the cathode electrode 11 and the gate electrode 13 is further disposed.

  If all the cathode electrodes 11 are short-circuited at their end portions, one inspection voltage applying unit 108 having a structure capable of contacting the end portions of the cathode electrode 11 is sufficient. If the end of the short-circuited cathode electrode 11 is separated from the cathode electrode 11 before the display device is assembled, voltage can be independently applied to each cathode electrode 11 during actual operation of the display device.

  An inspection substrate 110 having an inspection electrode 111 made of an aluminum layer is attached to the opened upper portion of the housing 101. The voltage control means 112 is connected to the inspection voltage application unit 108 and the inspection electrode 111.

  A cathode panel conditioning method and a cold cathode field emission display manufacturing method according to the first embodiment will be described below.

[Step-100]
First, a cathode panel CP is prepared in which a plurality of field emission elements are formed in each of M × N electron emission regions EA. A method for forming the field emission device will be described later.

[Step-110]
Then, the cathode panel CP is disposed in a chamber whose pressure is P _{1 so} that the electron emission area EA faces the inspection electrode 111.

Specifically, the cathode panel CP is placed on the pin 105 in the raised position, and the pin 105 is lowered by operating the pin lifting cylinder 104, and the cathode panel CP is placed on the inspection table 102. Then, after the cathode panel CP placed on the inspection table 102 is carried into the housing 101 via a door (not shown) provided on the housing 101, the inside of the housing 101 is evacuated by vacuum means (for example, a pressure P ₁ = ₁ × 10 ^-4 about Pa). The pressure in the housing 101 can be measured by a pressure gauge 106 such as a Pirani gauge or an ion gauge.

When the inside of the housing 101 has a desired atmosphere (pressure P ₁ ), the inspection table elevating cylinder 103 is operated to raise the inspection table 102, and the electron emission area EA provided in the cathode panel CP is inspected. The cathode panel CP is disposed so as to face the electrode 111 for use. The distance between the cathode panel CP and the inspection substrate 110 is, for example, 1.0 mm. In addition, the inspection voltage application unit 108 is brought into contact with the ends of the cathode electrode 11 and the gate electrode 13.

Then, while evacuating the housing 101 of the chamber (conditioning apparatus) 100, a constant voltage V _C (= 0 volts) is applied from the voltage control means 112 to all the cathode electrodes 11 via the inspection voltage application unit 108. With the constant voltage V _IE (= 10 kilovolts) applied to the inspection electrode 111, the minimum voltage value V _G-MIN (= −20 volts) and the maximum voltage value V _G-MAX (= 60) are applied to the gate electrode 13. A pulsed voltage having a voltage (volt) is applied. In Example 1, the execution time of conditioning was set to 10 (minutes). Note that the value of V _G−MAX −V _C is such that an electric field of at least 8 volts / μm is formed in the vicinity of the electron emission portions 15 and 115. In actual operation, the cathode panel CP is driven by a line-sequential driving method with a field frequency T (= 60 Hz), and the frequency T _G (Hz) of the pulse voltage applied to the gate electrode 13 is T _G = T / α (where 2 ≦ α ≦ 10 and α = 5 in Example 1) is satisfied. Specifically, the values of T ⁻¹ and T _G ⁻¹ are T ⁻¹ = 16.6 milliseconds and T _G ⁻¹ = 83.0 milliseconds. Further, t (V _G−MAX ) = T ⁻¹ / M. Note that the DC voltage v _A applied to the anode electrode 24 during actual operation of the display device is 7 kilovolts, and the distance between the cathode panel CP and the anode panel AP in the display device is 1. mm, and the distance between the cathode electrode 11 and the gate electrode 13 is 5 μm.

  More specifically, the first gate electrode, the second gate electrode, the third gate electrode, ..., the (M-1) th gate electrode, the Mth gate electrode, A pulsed voltage is sequentially applied, and then the first gate electrode, the second gate electrode, the third gate electrode,..., The (M−1) th gate electrode, The operation of sequentially applying a pulse voltage to the Mth gate electrode is repeated.

For example, when the maximum voltage value V _G-MAX is applied to the mth gate electrode, the first gate electrode to the (m−1) th gate electrode and the (m + 1) th gate The minimum voltage value V _G-MIN is applied to the electrode to the Mth gate electrode, and the minimum voltage value V _G-MIN is lower than the voltage V _C applied to the cathode electrode. Accordingly, in the electron emission region EA included in the mth gate electrode, the electrons are emitted from the electron emission portions 15 and 115 based on the quantum tunnel effect based on the electric field generated by the voltage application to the cathode electrode 11 and the gate electrode 13. Is released. The electrons are attracted to the inspection electrode 111. Therefore, it is possible to reliably prevent an undesired portion of the cathode panel CP from being charged by the collision of electrons. On the other hand, the electron emission region EA included in the first gate electrode to the (m−1) th gate electrode, and the electron emission region included in the (m + 1) th gate electrode to the Mth gate electrode. No electrons are emitted from the EA.

Accordingly, in the field emission device (low voltage electron emission field emission device) that emits electrons even at or near the cutoff voltage v _CUT existing in the electron emission region EA included in the mth gate electrode. Can stop the function of emitting electrons as a result of an excessive current flowing through the electron emitters 15 and 115. That is, the low voltage electron emission field emission device can be removed in operation. On the other hand, the electron emission region EA included in the first to (m−1) th gate electrodes and the electron emission region included in the (m + 1) th gate electrode to the Mth gate electrode. No electrons are emitted from the low voltage electron emission field emission device present in the EA. Therefore, during the conditioning process, a phenomenon in which a direct current continues to flow between the undesired field emission device and the inspection electrode 111 does not occur, and the cathode panel CP is damaged due to the temperature rise in the field emission device. It is possible to prevent problems such as generation and discharge breakdown in the cathode panel CP.

  After completing the conditioning process of the cathode panel CP, the atmosphere in the housing 101 is changed to an atmospheric atmosphere, the inspection table lifting cylinder 103 is operated, the inspection table 102 is lowered, and the inspection table 102 on which the cathode panel CP is placed is moved to the housing 101. Unload from.

[Step-120]
On the other hand, an anode panel AP in which the phosphor region 22, the anode electrode 24, etc. are formed is prepared. Then, the display device is assembled. Specifically, for example, the spacer 25 is attached to the spacer holding portion 26 provided in the effective region of the anode panel AP, and the anode panel AP and the cathode panel CP are arranged so that the phosphor region 22 and the electron emission region EA face each other. And the anode panel AP and the cathode panel CP (more specifically, the substrate 20 and the support 10) are joined to each other at the peripheral portion via a frame body 27 made of ceramics or glass. At the time of joining, frit glass is applied to the joining portion between the frame body 27 and the anode panel AP and the joining portion between the frame body 27 and the cathode panel CP, and the anode panel AP, the cathode panel CP, and the frame body 27 are pasted. In addition, the frit glass is dried by preliminary baking, and then main baking is performed at about 450 ° C. for 10 to 30 minutes.

[Step-130]
Thereafter, the space surrounded by the anode panel AP, the cathode panel CP, the frame, and the frit glass (not shown) is exhausted through a through hole (not shown) and a tip tube (not shown), and the pressure P of the space _{When 0} reaches about 10 ⁻⁴ Pa, the tip tube is sealed by heating and melting. In this way, the space surrounded by the anode panel AP, the cathode panel CP, and the frame can be evacuated. Alternatively, for example, the frame, the anode panel AP, and the cathode panel CP may be bonded together in a high vacuum atmosphere. Alternatively, depending on the structure of the display device, the anode panel AP and the cathode panel CP may be bonded together by using only an adhesive layer without a frame. Thereafter, wiring connection with necessary external circuits is performed, and the display device of Example 1 is completed.

In the display device thus obtained, even when operated at or near the cut-off voltage v _CUT, that is, when the darkest display as a whole of the cold cathode field emission display device is performed. Thus, there is no electron emission region recognized as a bright spot, and an image with excellent uniformity can be obtained.

Example 2 relates to a conditioning method for a cold cathode field emission display according to the first aspect of the present invention. Since the configuration and structure of the display device in the second embodiment can be the same as the configuration and structure of the display device described in the first embodiment, detailed description thereof is omitted. 2A and 2B are conceptual diagrams of a conditioning method of the cold cathode field emission display device of Example 2. FIG. Here, (A) in FIG. 2 is a diagram conceptually showing a voltage application state to the cathode electrode, gate electrode, and anode electrode, and (B) in FIG. 2 is a constant voltage applied to the cathode electrode. V _C (indicated by a dotted line) and pulsed voltages V _G-MAX and V _G-MIN (indicated by a solid line) applied to the gate electrode are schematically illustrated.

  In the second embodiment, the cathode panel CP and the anode panel AP described in the first embodiment are prepared. Then, by performing [Step-120] of Example 1, it is possible to obtain a display device in which the cathode panel CP and the anode panel AP are joined at the peripheral edge thereof.

Thereafter, a constant voltage V _C is applied to the cathode electrode 11 while exhausting the space between the cathode panel CP and the anode panel AP through a through-hole (not shown) and a tip tube (not shown). With the voltage V _A applied to the electrode 24, the gate electrode 13 is applied with a pulse voltage having a minimum voltage value V _G-MIN and a maximum voltage value V _G-MAX (where V _G-MIN <V _C <V _G-MAX << V _A ) is applied. In Example 2, the execution time of conditioning was set to 10 (minutes).

Specifically, the same constant voltage V _C as that of the first embodiment is applied to all the cathode electrodes 11 and the same voltage V _{A as} that of the voltage V _{IE of the} first embodiment is applied to the anode electrode 24. A pulsed voltage having a minimum voltage value V _G-MIN and a maximum voltage value V _G-MAX similar to those in the first embodiment is applied to 13. Note that the value of V _G−MAX −V _C is such that an electric field of at least 8 volts / μm is formed in the vicinity of the electron emission portions 15 and 115. In actual operation, the cathode panel CP is driven by a line-sequential driving method with a field frequency T (= 60 Hz), and the frequency T _G (Hz) of the pulse voltage applied to the gate electrode 13 is T _G = T / α (where 2 ≦ α ≦ 10 is satisfied, and Example 2 has the same value as Example 1).

  More specifically, as in the first embodiment, the first gate electrode, the second gate electrode, the third gate electrode,..., The (M−1) th gate electrode, A pulsed voltage is sequentially applied to the Mth gate electrode, and then the first gate electrode, the second gate electrode, the third gate electrode,..., (M− 1) An operation of sequentially applying a pulsed voltage to the 1st gate electrode and the Mth gate electrode is repeated.

For example, when the maximum voltage value V _G-MAX is applied to the mth gate electrode, the first gate electrode to the (m−1) th gate electrode and the (m + 1) th gate The minimum voltage value V _G-MIN is applied to the electrode to the Mth gate electrode, and the minimum voltage value V _G-MIN is lower than the voltage V _C applied to the cathode electrode. Accordingly, in the electron emission region EA included in the mth gate electrode, the electrons are emitted from the electron emission portions 15 and 115 based on the quantum tunnel effect based on the electric field generated by the voltage application to the cathode electrode 11 and the gate electrode 13. Is released. The electrons are attracted to the anode electrode 24. Therefore, it is possible to reliably prevent an undesired portion of the cathode panel CP from being charged by the collision of electrons. On the other hand, the electron emission region EA included in the first gate electrode to the (m−1) th gate electrode, and the electron emission region included in the (m + 1) th gate electrode to the Mth gate electrode. No electrons are emitted from the EA.

  As a result, in the low voltage electron emission field emission device present in the electron emission region EA included in the mth gate electrode, electrons are emitted as a result of excessive current flowing through the electron emission portions 15 and 115. The function can be stopped. That is, the low voltage electron emission field emission device can be removed in operation. On the other hand, the electron emission region EA included in the first gate electrode to the (m−1) th gate electrode, and the electron emission region included in the (m + 1) th gate electrode to the Mth gate electrode. No electrons are emitted from the low voltage electron emission field emission device present in the EA. Therefore, during the conditioning process, a phenomenon in which a direct current continues to flow between the undesired field emission device and the anode electrode 24 does not occur, and the cathode panel due to the temperature rise in the field emission device or the anode electrode 24 occurs. It is possible to prevent problems such as the occurrence of damage to the CP and the anode panel AP and the breakdown of the discharge inside the display device and the cathode panel CP.

  Thereafter, the same process as [Step-130] of Example 1 is performed to complete the display device of Example 2.

Even in the display device obtained in this way, even in the operation at or near the cut-off voltage v _CUT, that is, when the darkest display is made as a whole of the cold cathode field emission display device. Thus, there is no electron emission region recognized as a bright spot, and an image with excellent uniformity can be obtained.

Example 3 relates to a cathode panel conditioning method according to the second aspect of the present invention and a cold cathode field emission display device manufacturing method according to the second aspect of the present invention. 3A and 3B are conceptual diagrams of the conditioning process in the cathode panel conditioning method of the third embodiment and the cold cathode field emission display manufacturing method of the third embodiment. Here, FIG. 3A conceptually shows a voltage application state to the cathode electrode, gate electrode, and inspection electrode, and FIG. 3B shows the cathode electrode, gate electrode, inspection. FIG. 4 schematically shows constant voltages V _C (indicated by a dotted line), V _G (indicated by a one-dot chain line), and V _IE (indicated by a solid line) to be applied to a working electrode.

  The display device and cathode panel CP in Example 3 have the same configuration and structure as the display device and cathode panel CP described with reference to FIG. That is, a flat type field emission device is formed on the cathode panel CP. The specific configuration and structure of the cathode panel CP and display device of Example 3 can be the same as the configuration and structure of the cathode panel CP and display device described in Example 1 with reference to FIG. Detailed description will be omitted.

  In the manufacturing process of the flat field emission device, as will be described in detail later, carbon nanotubes, which are electron emission materials, may be left as residues on the gate electrode 13 and the insulating layer 12 in some cases. As a result, electrons are emitted from the carbon nanotubes left as residues on the gate electrode 13 and the insulating layer 12 based on the electric field formed by the anode electrode 24, and the bright spots in the display device become non-uniform. The image quality may deteriorate.

  In the third embodiment, carbon nanotubes left as residues on the gate electrode 13 and the insulating layer 12 are removed.

  Hereinafter, a cathode panel conditioning method and a cold cathode field emission display manufacturing method of Example 3 will be described.

[Step-300]
First, a cathode panel CP is prepared in which a plurality of field emission elements are formed in each of M × N electron emission regions EA. A method for forming the field emission device will be described later.

[Step-310]
Then, in the same manner as in [Step-110] of Example 1, the cathode panel CP is disposed in the chamber whose pressure is P _{1 so} that the electron emission region EA faces the inspection electrode 111. .

Then, while continuing to exhaust the housing 101 of the chamber (conditioning apparatus) 100, a constant voltage V _C (= 20 volts) is applied from the voltage control means 112 to all the cathode electrodes 11 via the inspection voltage application unit 108, A constant voltage V _IE (= 10 kilovolts) is applied to the inspection electrode 111 while a constant voltage V _G (= 0 volts) is applied to the gate electrode 13. Note that the DC voltage v _A applied to the anode electrode 24 during actual operation of the display device is 7 kilovolts, the distance between the cathode panel CP and the anode panel AP in the display device is 1.0 mm, and the cathode electrode 11 and the gate. The distance between the electrodes 13 is 7 μm. In Example 3, the execution time of conditioning was set to 10 (minutes).

In Example 3, it is formed by the voltage V _IE applied to the inspection electrode 111 from the carbon nanotubes left as residues on the gate electrode 13 and the insulating layer 12 in the manufacture of the flat field emission device. Electrons are emitted based on the applied electric field, and an excess current flows through the carbon nanotubes left as residues on the gate electrode 13 and the insulating layer 12 and is removed by combustion. Moreover, although a V _C> V _G therefore will not be from the electron emission regions 115 are electrons are emitted. That is, during the conditioning process, a phenomenon in which a direct current flows between the field emission element and the inspection electrode 111 does not occur, and the cathode panel CP is damaged due to the temperature rise in the field emission element. It is possible to prevent problems such as discharge breakdown in the CP.

  After completing the conditioning process of the cathode panel CP, the atmosphere in the housing 101 is changed to an atmospheric atmosphere, the inspection table lifting cylinder 103 is operated, the inspection table 102 is lowered, and the inspection table 102 on which the cathode panel CP is placed is moved to the housing 101. Unload from.

[Step-310]
Thereafter, the same steps as [Step-120] and [Step-130] of Example 1 are performed to complete the display device of Example 3.

  In the display device thus obtained, the electron emission material (specifically, carbon nanotubes) remained as a residue on the gate electrode 13 and the insulating layer 12 without causing the problem of damage to the cathode panel CP. ) Can be reliably removed.

Instead of applying the constant voltage V _IE to the inspection electrode 111, a pulse voltage having a minimum voltage value V _IE-MIN and a maximum voltage value V _IE may be applied. In this case, in actual operation, the cathode panel CP is driven by a line-sequential driving method with a field frequency T (= 60 Hz), and the frequency T _IE (Hz) of the pulse voltage applied to the inspection electrode 111 is , T _IE = T / β (where a 10 ≦ β ≦ 100, for example, beta = 20) may be configured to satisfy the.

4A and 4B are conceptual diagrams of a modification of the cathode panel conditioning method of Example 3 and a modification of the conditioning process in the method of manufacturing a cold cathode field emission display device of Example 3. FIG. Shown in B). 4A is a diagram conceptually showing a voltage application state to the cathode electrode, the gate electrode, and the inspection electrode, and FIG. 4B is a diagram showing the cathode electrode, the gate electrode, and the inspection. The voltages V _C (indicated by the dotted line), V _G (indicated by the alternate long and short dash line), V _IE-MIN , and V _IE (indicated by the solid line) to be applied to the working electrode are schematically illustrated.

Specifically, a constant voltage V _C (= 20 volts) is applied from the voltage control means 112 to all the cathode electrodes 11 via the inspection voltage application unit 108, and a constant voltage V _G ( In a state where = 0 volts) is applied, a pulse voltage having a minimum voltage value V _IE-MIN (= 0 volt) and a maximum voltage value V _IE (= 10 kilovolts) is applied to the inspection electrode 111. Conditioning execution time may be 10 (minutes).

Example 4 relates to a conditioning method for a cold cathode field emission display according to the second aspect of the present invention. Since the configuration and structure of the display device in the fourth embodiment can be the same as the configuration and structure of the display device described in the third embodiment, detailed description thereof is omitted. 5A and 5B show conceptual diagrams of a conditioning method for the cold cathode field emission display of Example 4. FIG. Here, FIG. 5A is a diagram conceptually showing a voltage application state to the cathode electrode, the gate electrode, and the anode electrode, and FIG. 5B is a cathode electrode, the gate electrode, and the anode electrode. A constant voltage V _C (indicated by a dotted line), V _G (indicated by an alternate long and short dash line), and V _A (indicated by a solid line) to be applied to are schematically illustrated.

  In the fourth embodiment, the cathode panel CP and the anode panel AP described in the third embodiment are prepared. Then, by performing [Step-120] of Example 1, it is possible to obtain a display device in which the cathode panel CP and the anode panel AP are joined at the peripheral edge thereof.

Then, a constant voltage V _C is applied to the cathode electrode 11 while exhausting the space between the cathode panel CP and the anode panel AP through a through hole (not shown) and a tip tube (not shown), and the gate _A voltage V _A (provided that V _C << V _A ) is applied to the anode electrode 24 with a constant voltage V _G (provided that V _G <V _C ) is applied to the electrode 13. In Example 4, the execution time of conditioning was set to 10 (minutes).

Specifically, the same constant voltage V _C as in the third embodiment is applied to all the cathode electrodes 11, and the same constant voltage V _G as in the third embodiment is applied to the gate electrode 13. _A constant voltage V _A equal to the voltage V _{IE of} 3 is applied.

Even in the fourth embodiment, since V _C > V _G , no electrons are emitted from the electron emission portion 115. Therefore, during the conditioning process, a phenomenon in which a direct current flows between the field emission device and the anode electrode 24 does not occur, and the cathode panel CP or anode panel caused by the temperature rise in the field emission device or the anode electrode 24 does not occur. It is possible to prevent problems such as the occurrence of damage to the AP and the breakdown of the discharge inside the display device or the cathode panel CP. In addition, electrons are emitted from the carbon nanotubes left as residues on the gate electrode 13 and the insulating layer 12 in the manufacture of the flat field emission device based on the electric field formed by the voltage V _A applied to the anode electrode 24. As a result of excessive current flowing through the carbon nanotubes left as residues on the gate electrode 13 and the insulating layer 12, they are removed by combustion.

  Thereafter, the same process as [Process-130] of Example 1 is performed to complete the display device of Example 4.

  In the display device thus obtained, the electron emission material (specifically, the residue left on the gate electrode 13 or the insulating layer 12 without causing the problem of damage to the cathode panel CP or the anode panel AP) , Carbon nanotubes) can be reliably removed.

Specifically, even when a voltage of 10 kilovolts is applied to the anode electrode as a voltage v _A , the bright spot in the display device is not uniform due to the carbon nanotubes left as residues on the gate electrode 13 or the insulating layer 12. The occurrence of the phenomenon was not observed. In the case where such a conditioning process is not performed, when 4 kV is applied as the voltage v _A to the anode electrode, the display caused by the carbon nanotubes left as a residue on the gate electrode 13 or the insulating layer 12 is displayed. Occurrence of phenomena such as non-uniformity of bright spots in the device was observed.

Instead of applying a constant voltage V _A to the anode electrode 24, a pulse voltage having a minimum voltage value V _A-MIN and a maximum voltage value V _A may be applied. In this case, the cathode panel CP is driven by a line-sequential driving method with a field frequency T (= 60 Hz) in actual operation, and the frequency T _A (Hz) of the pulse voltage applied to the anode electrode 24 is _A configuration satisfying T _A = T / β (where 10 ≦ β ≦ 100, for example, β = 20) may be employed.

6A and 6B are conceptual diagrams of a modification of the conditioning method of the cold cathode field emission display according to the fourth embodiment. Here, FIG. 6A is a diagram conceptually showing a voltage application state to the cathode electrode, the gate electrode, and the anode electrode, and FIG. 6B is a cathode electrode, the gate electrode, and the anode electrode. 1 schematically shows voltages V _C (indicated by a dotted line), V _G (indicated by an alternate long and short dash line), V _A-MIN , and V _A (indicated by a solid line) applied to. The specific values of the voltages V _C , V _G , V _A-MIN , V _A are the same as the values of the voltages V _C , V _G , V _IE-MIN , V _IE in the modified example of the third embodiment. do it. In addition, the conditioning execution time may be 10 (minutes).

[Method of manufacturing Spindt-type field emission device]
Hereinafter, a method for manufacturing a Spindt-type field emission device is shown in FIGS. 17A, 17B, and 18A, which are schematic partial end views of the support 10 and the like constituting the cathode panel CP. A description will be given with reference to (B).

  This Spindt-type field emission device can be basically obtained by a method of forming the conical electron emission portion 15 by vertical vapor deposition of a metal material. That is, the vapor deposition particles are perpendicularly incident on the first opening 14A provided in the gate electrode 13, but use the shielding effect by the overhanging deposit formed near the opening end of the first opening 14A. Thus, the amount of vapor deposition particles reaching the bottom of the second opening 14B is gradually reduced, and the electron emission portion 15 that is a conical deposit is formed in a self-aligning manner. Here, a method for forming the separation layer 16 in advance on the gate electrode 13 and the insulating layer 12 in order to facilitate removal of unnecessary overhanging deposits will be described. In the drawing for explaining the method of manufacturing the field emission device, only one electron emission portion is shown.

[Step-A0]
First, a cathode electrode conductive material layer made of, for example, polysilicon is formed on the support 10 made of, for example, a glass substrate by a plasma CVD method, and then the cathode electrode conductive material layer is formed based on a lithography technique and a dry etching technique. Is patterned to form a strip-like cathode electrode 11. Thereafter, an insulating layer 12 made of SiO _{2 is} formed on the entire surface by a CVD method.

[Step-A1]
Next, a gate electrode conductive material layer (for example, an Al layer) is formed on the insulating layer 12 by a sputtering method, and then the gate electrode conductive material layer is patterned by a lithography technique and a dry etching technique. Thus, the strip-shaped gate electrode 13 can be obtained. The strip-shaped cathode electrode 11 extends in the left-right direction in the drawing, and the strip-shaped gate electrode 13 extends in the direction perpendicular to the drawing.

  The gate electrode 13 is formed by a well-known thin film formation method such as a PVD method such as a vacuum deposition method, a CVD method, a plating method such as an electroplating method or an electroless plating method, a screen printing method, a laser ablation method, a sol-gel method, a lift-off method. If necessary, it may be formed by a combination with an etching technique. According to the screen printing method or the plating method, for example, a strip-shaped gate electrode can be directly formed.

[Step-A2]
Thereafter, a resist layer is formed again, the first opening 14A is formed in the gate electrode 13 by etching, the second opening 14B is formed in the insulating layer, and the cathode electrode 11 is formed at the bottom of the second opening 14B. After the exposure, the resist layer is removed. In this way, the structure shown in FIG. 17A can be obtained.

[Step-A3]
Next, the peeling layer 16 is formed by obliquely vacuum-depositing nickel (Ni) on the insulating layer 12 including the gate electrode 13 while rotating the support 10 (see FIG. 17B). At this time, by selecting a sufficiently large incident angle of the vapor deposition particles with respect to the normal of the support 10 (for example, an incident angle of 65 to 85 degrees), nickel is hardly deposited on the bottom of the second opening 14B. A release layer 16 can be formed on the gate electrode 13 and the insulating layer 12. The release layer 16 protrudes in a bowl shape from the opening end of the first opening 14A, whereby the diameter of the first opening 14A is substantially reduced.

[Step-A4]
Next, for example, molybdenum (Mo) is vertically deposited as an electrically conductive material on the entire surface (incident angle: 3 to 10 degrees). At this time, as shown in FIG. 18A, as the conductive material layer 17 having an overhang shape grows on the release layer 16, the substantial diameter of the first opening 14A is gradually reduced. The vapor deposition particles that contribute to the deposition at the bottom of the second opening 14B are gradually limited to those that pass near the center of the first opening 14A. As a result, a conical deposit is formed at the bottom of the second opening 14 </ b> B, and this conical deposit becomes the electron emission portion 15.

[Step-A5]
Thereafter, as shown in FIG. 18B, the peeling layer 16 is peeled off from the surfaces of the gate electrode 13 and the insulating layer 12 by a lift-off method, and the conductive material layer 17 above the gate electrode 13 and the insulating layer 12 is selected. To remove. Next, it is preferable to recede the side wall surface of the second opening 14B provided in the insulating layer 12 by isotropic etching from the viewpoint of exposing the opening end of the gate electrode 13. The isotropic etching can be performed by dry etching using radicals as a main etching species, such as chemical dry etching, or wet etching using an etchant. As the etchant, for example, a 1: 100 (volume ratio) mixed solution of 49% hydrofluoric acid aqueous solution and pure water can be used. Thus, a Spindt type field emission device can be obtained.

[Manufacturing method of flat-type field emission device]
Next, a method for manufacturing a flat field emission device is shown in FIGS. 19A to 19C and FIG. 20A which are schematic partial end views of the support 10 and the like constituting the cathode panel CP. , (B), and FIGS. 21 (A) and (B). The electron emission portion 115 includes a matrix 41 and a carbon nanotube structure (specifically, the carbon nanotube 40) embedded in the matrix 41 with the tip portion protruding. The matrix 41 is made of indium-tin oxide.

[Step-B0]
First, a conductive material layer for forming a cathode electrode is formed on a support 10 made of, for example, a glass substrate, and then the conductive material layer is patterned based on a well-known lithography technique and a reactive ion etching method (RIE method). Then, a strip-like cathode electrode 11 is formed on the support 10 (see FIG. 19A). The strip-shaped cathode electrode 11 extends in the horizontal direction of the drawing. The conductive material layer is made of, for example, a chromium (Cr) layer having a thickness of about 0.2 μm formed by a sputtering method.

[Step-B1]
Thereafter, a metal compound solution made of an organic acid metal compound in which a carbon nanotube structure is dispersed is applied to the entire surface by, for example, a spray method. Specifically, a metal compound solution exemplified in Table 2 below is used. In the metal compound solution, the organic tin compound and the organic indium compound are dissolved in an acid (for example, hydrochloric acid, nitric acid, or sulfuric acid). Carbon nanotubes are manufactured by the arc discharge method, and have an average diameter of 30 nm and an average length of 1 μm. At the time of application, the support 10 is heated to 70 to 150 ° C. The coating atmosphere is an air atmosphere. After the application, the support 10 is heated for 5 to 30 minutes to sufficiently evaporate butyl acetate. As described above, by heating the support 10 at the time of coating, drying of the coating solution starts before the carbon nanotubes self-level in the direction approaching the horizontal with respect to the surface of the cathode electrode 11. Carbon nanotubes can be arranged on the surface of the cathode electrode 11 without being horizontal. In other words, the carbon nanotube structure can be oriented in a state in which the tip of the carbon nanotube faces the direction of the anode electrode 24, in other words, in a direction approaching the normal direction of the support 10. In addition, a metal compound solution having the composition shown in Table 2 may be prepared in advance, or a metal compound solution to which carbon nanotubes are not added is prepared, and before application, the carbon nanotubes and the metal compound are prepared. You may mix with a solution. In addition, in order to improve the dispersibility of carbon nanotubes, ultrasonic waves may be irradiated when preparing the metal compound solution.

[Table 2]
Organotin compound and organoindium compound: 0.1 to 10 parts by weight Dispersant (sodium dodecyl sulfate): 0.1 to 5 parts by weight Carbon nanotube: 0.1 to 20 parts by weight Butyl acetate: remaining

  If an organic acid metal compound solution in which an organic tin compound is dissolved in an acid is used, tin oxide is obtained as a matrix. If an organic indium compound is dissolved in an acid, indium oxide is obtained as a matrix. If a zinc compound dissolved in an acid is used, zinc oxide can be obtained as a matrix. If an organic antimony compound dissolved in an acid is used, antimony oxide can be obtained as a matrix. The organic antimony compound and the organic tin compound can be converted into an acid. Antimony-tin oxide can be obtained as a matrix. In addition, when an organic tin compound is used as the organometallic compound solution, tin oxide is obtained as a matrix. When an organic indium compound is used, indium oxide is obtained as a matrix. When an organic zinc compound is used, zinc oxide is obtained as a matrix. When an organic antimony compound is used, antimony oxide is obtained as a matrix, and when an organic antimony compound and an organic tin compound are used, antimony-tin oxide is obtained as a matrix. Alternatively, a metal chloride solution (eg, tin chloride, indium chloride) may be used.

  Depending on the case, the remarkable unevenness | corrugation may be formed in the surface of the metal compound layer after drying a metal compound solution. In such a case, it is desirable to apply the metal compound solution again on the metal compound layer without heating the support.

[Step-B2]
Thereafter, by firing a metal compound composed of an organic acid metal compound, a matrix (specifically, a metal oxide) derived from metal atoms (specifically, In and Sn) constituting the organic acid metal compound. More specifically, the composite layer 42 in which the carbon nanotubes 40 are fixed to the surface of the cathode electrode 11 is obtained with the ITO 41. Firing is performed in an air atmosphere at 350 ° C. for 20 minutes. Thus, the volume resistivity of the obtained matrix 41 was 5 × 10 ⁻⁷ Ω · m. By using an organic acid metal compound as a starting material, the matrix 41 made of ITO can be formed even at a low temperature of 350 ° C. When a metal chloride solution (for example, tin chloride or indium chloride) is used instead of the organometallic compound solution, a matrix 41 made of ITO is formed while tin chloride and indium chloride are oxidized by firing. The

[Step-B3]
Next, a resist layer (not shown) is formed on the entire surface, and a circular resist layer having a diameter of, for example, 30 μm is left above a desired region of the cathode electrode 11. Then, the matrix 41 is etched for 1 to 30 minutes using 10 to 60 ° C. hydrochloric acid to remove unnecessary portions of the electron emission portion. Further, when carbon nanotubes still exist outside the desired region, the carbon nanotubes are etched by an oxygen plasma etching process under the conditions exemplified in Table 3 below. The bias power may be 0 watt, that is, it may be a direct current, but it is desirable to add the bias power. Further, the support may be heated to about 80 ° C., for example.

[Table 3]
Equipment used: RIE equipment introduction gas: Gas plasma excitation power containing oxygen: 500W
Bias power: 0 to 150W
Processing time: 10 seconds or more

  Alternatively, the carbon nanotubes may be etched by wet etching under the conditions exemplified in Table 4.

[Table 4]
Working solution: KMnO ₄
Temperature: 20-120 ° C
Processing time: 10 seconds to 20 minutes

  Then, the structure shown in FIG. 19B can be obtained by removing the resist layer. Note that the present invention is not limited to leaving a circular electron emission portion having a diameter of 30 μm. For example, the electron emission portion may be left on the cathode electrode 11. Thereafter, a buffer layer may be formed on the composite layer 42. By forming the buffer layer, when the opening 14B is formed in the insulating layer 12, the completion of the formation of the opening 14B can be reliably detected. The material constituting the buffer layer may be appropriately selected from materials having an etching selectivity with respect to the material constituting the insulating layer 12, and may be a conductive material or an insulating material.

[Step-B4]
Next, the insulating layer 12 is formed on the composite layer 42, the support 10 and the cathode electrode 11. Specifically, the insulating layer 12 having a thickness of about 5 μm is formed on the entire surface by, for example, a CVD method using TEOS (tetraethoxysilane) as a source gas.

[Step-B5]
Thereafter, the gate electrode 13 having the first opening 14 </ b> A is formed on the insulating layer 12. Specifically, after a conductive material layer made of chromium (Cr) for forming a gate electrode is formed on the insulating layer 12 by a sputtering method, a first mask material layer (patterned on the conductive material layer ( The conductive material layer is etched using the first mask material layer as an etching mask to pattern the conductive material layer into a strip shape, and then the first mask material layer is removed. Next, a patterned second mask material layer 46 is formed on the conductive material layer and the insulating layer 12, and the conductive material layer and the insulating layer 12 are etched using the second mask material layer 46 as an etching mask. . Thus, the gate electrode 13 having the first opening 14A on the insulating layer 12 can be obtained, and further, the second opening 14B can be formed in the insulating layer 12 (see FIG. 19C). ). The strip-shaped gate electrode 13 extends in a direction different from the cathode electrode 11 (for example, a direction perpendicular to the drawing in the drawing). The first opening 14A and the second opening 14B have a one-to-one correspondence. That is, one second opening 14B is formed corresponding to one first opening 14A. The planar shape of the first and second openings 14A and 14B is, for example, a circle having a diameter of 20 μm. For example, about several hundreds of these openings 14A and 14B may be formed in one pixel. For example, when a buffer layer is formed on the composite layer 42, the buffer layer is etched.

[Step-B6]
Thereafter, the matrix 41 on the surface of the composite layer 42 exposed at the bottom of the second opening 14B is removed, and the electron emission portion 115 in which the carbon nanotubes 40 are embedded in the matrix 41 with the tip portion protruding is formed. It is preferable to do this (see FIG. 20A), but this step is not essential. Specifically, it is preferable to remove the surface layer portion of the matrix 41 under the conditions exemplified in Table 5 below to obtain the carbon nanotubes 40 with the tip portion protruding from the matrix 41. In some cases, the entire matrix 41 may be removed by etching.

[Table 5]
Etching solution: hydrochloric acid Etching time: 10 to 30 seconds Etching temperature: 10 to 60 ° C

[Step-B7]
Thereafter, it is preferable to recede the side wall surface of the second opening 14B provided in the insulating layer 12 by isotropic etching from the viewpoint of exposing the opening end of the gate electrode 13. The isotropic etching can be performed by dry etching using radicals as a main etching species, such as chemical dry etching, or wet etching using an etchant. As the etchant, for example, a 1: 100 (volume ratio) mixed solution of 49% hydrofluoric acid aqueous solution and pure water can be used. Next, the second mask material layer 46 is removed. Thus, the field emission device shown in FIG. 20B can be completed.

[Step-B8]
Next, a release layer 43 is attached to the surface of the composite layer 42 (see FIG. 21A). Then, the release layer 43 is mechanically peeled off. As a result, the carbon nanotubes 40, which are carbon nanotube structures, are embedded in the matrix 41 in a state in which the tip portion protrudes and the tip portion is oriented in a direction approaching the normal direction of the support 10. In addition, an electron emission portion 115 can be obtained (see FIG. 21B). Here, the release layer 43 includes a pressure-sensitive adhesive layer 44 and a holding film 45 that holds the adhesive layer 44. More specifically, the release layer 43 is made of cellophane tape. As a method of attaching the release layer 43 to the surface of the composite layer 42, a method of pressing the adhesive layer 44 constituting the release layer 43 to the surface of the composite layer 42 was adopted. The pressure bonding is performed manually, and specifically, the pressure-sensitive adhesive layer 44 is pressure-bonded to the surface of the composite layer 42 by pressing a rubber roller against the holding film 45. Moreover, the mechanical peeling of the peeling layer 43 is performed in a state where the peeling force has a component in the normal direction of the support 10. More specifically, a so-called 90-degree peel was applied, and the method of applying the peeling force was by human power.

[Step-B9]
Etching of the matrix 41 or peeling of the peeling layer 43 changes the surface state of some or all of the carbon nanotubes 40 (for example, oxygen atoms, oxygen molecules, or fluorine atoms are adsorbed on the surface) and is inactive with respect to field emission. It may be. Therefore, after that, it is preferable to perform a plasma treatment in a hydrogen gas atmosphere on the electron emission portion 115, thereby activating the electron emission portion 115 and further increasing the efficiency of electron emission from the electron emission portion 115. Can be improved. The conditions for the plasma treatment are illustrated in Table 6 below.

[Table 6]
Gas used: H ₂ = 100 sccm
Power supply: 1000W
Support power applied: 50V
Reaction pressure: 0.1 Pa
Support temperature: 300 ° C

  Thereafter, in order to release the gas from the carbon nanotube 40, heat treatment or various plasma treatments may be performed, or a substance to be adsorbed to intentionally adsorb the adsorbed material on the surface of the carbon nanotube 40 may be selected. The carbon nanotubes 40 may be exposed to the contained gas. In order to purify the carbon nanotube 40, oxygen plasma treatment or fluorine plasma treatment may be performed.

  Alternatively, a flat field emission device can be manufactured based on the method described below.

[Step-C0]
First, in the same manner as in [Step-B0], a strip-like cathode electrode 11 is formed on the support 10 on the support 10 made of, for example, a glass substrate. Next, the insulating layer 12 is formed on the support 10 and the cathode electrode 11 in the same manner as in [Step-B4]. Specifically, the insulating layer 12 having a thickness of about 5 μm is formed on the entire surface by, for example, a CVD method using TEOS (tetraethoxysilane) as a source gas. Thereafter, in the same manner as in [Step-B5], the gate electrode 13 having the first opening 14A is formed on the insulating layer 12, and further, the second opening 14B is formed in the insulating layer 12 (FIG. 22). (See (A)).

[Step-C1]
Next, the mask layer 47 covers the insulating layer 12, the gate electrode 13 and the side walls of the openings 14A and 14B, and the portion of the cathode electrode 11 that does not form the electron emission portion at the bottom of the second opening 14B (FIG. 22). (See (B)).

[Step-C2]
Thereafter, the electron emission portion 115 is formed on the surface of the cathode electrode 11 in the same manner as in [Step-B1] to [Step-B2]. Next, the composite layer above the insulating layer 12 and the gate electrode 13 is removed by peeling the mask layer 47.

[Step-C3]
Thereafter, in the same manner as in [Step-B6], the matrix 41 on the surface of the composite layer exposed at the bottom of the second opening 14B is removed, and the carbon nanotubes 40 are placed in the matrix 41 with the tip protruding. An embedded electron emission portion 115 is formed. In this way, the structure shown in FIG. 22C can be obtained.

[Step-C4]
Then, the flat type field emission device is completed by performing the same steps as [Step-B7] to [Step-B9].

  In the same step as [Step-B8] in [Step-B8] or [Step-C4], when the peeling layer 43 is mechanically peeled off from the surface of the composite layer 42 (the peeling force is shown in FIG. 21). In (A), indicated by a white arrow), the release layer 43 exhibits a clockwise rotational movement centered on the “A” mark in FIG. In general, since the diameter of the first opening 14A is shorter than the distance from the “A” mark to the “B” mark in FIG. 21A, the release layer 43 is rotated clockwise around the “A” mark. When the adhesive layer 44 is peeled off from the composite layer 42 by the movement and comes out of the first opening 14A, the portion of the adhesive layer 44 indicated by “B” is often located at the opening end of the first opening 14A. Collide or get caught. At this time, a part of the carbon nanotube 40 peeled off from the composite layer 42 and adhered to the adhesive layer 44 may be detached from the adhesive layer 44 and left as a residue on the gate electrode 13 or the insulating layer 12. is there. However, the carbon nanotubes left as residues on the gate electrode 13 and the insulating layer 12 can be removed by the conditioning method described in Example 3 or Example 4.

  As described above, the mechanical peeling of the peeling layer 43 is preferably performed in a state where the peeling force has a component in the normal direction of the support 10. Note that the ratio of the component in the normal direction of the support 10 in the peeling force only needs to exceed 0% of the value of the peeling force, and is approximately 100% (that is, so-called 90 degree peel). You can also. The method of applying the peeling force may be by human power or using a machine.

  As described above, the release layer is composed of a pressure-sensitive adhesive layer or a pressure-sensitive adhesive layer and a holding film (supporting film) that holds the adhesive layer or the adhesive layer, and the release layer is attached to the surface of the composite layer. The method of making it can be comprised from the method of crimping | bonding the adhesion layer or contact bonding layer which comprises a peeling layer to the surface of a composite layer. Specifically, the pressure may be applied to the holding film while the pressure-sensitive adhesive layer or adhesive layer is in contact with the surface of the composite layer. As a method for applying pressure, for example, a method using a roller having elasticity on the contact surface can be cited. If part of the adhesive layer or adhesive layer remains on the surface of the composite layer after mechanically peeling off the release layer, remove the adhesive layer or part of the adhesive layer with an organic solvent that dissolves the adhesive layer or adhesive layer. That's fine. Depending on the resin constituting the adhesive layer, for example, there is a type of resin in which the adhesive force of the adhesive layer to the surface of the composite layer is significantly reduced by applying heat or irradiating ultraviolet rays. When such a resin is used, a part of the adhesive layer left on the surface of the composite layer can be easily removed by washing with water or the like after applying heat or irradiating with ultraviolet rays. Examples of the holding film include film substrates made of polyolefin, PVC, and PET. What is necessary is just to determine the thickness of the whole peeling layer suitably.

  Alternatively, the release layer is composed of an adhesive layer and a holding film (supporting film) that holds the adhesive layer, and the method of attaching the release layer to the surface of the composite layer is bonded to the surface of the composite layer. After forming the layer, the holding film can be placed on the release layer, and then the adhesive layer can be adhered to the surface of the composite layer and the holding film. In this case, the adhesive layer can be composed of, for example, a thermoplastic resin, a thermosetting resin, an ultraviolet curable resin, or a pressure sensitive resin. An example of the method for forming the adhesive layer is a method of applying the adhesive layer to the surface of the composite layer. A specific coating method may be a coating method suitable for the material constituting the adhesive layer to be used, such as a spin coating method, a spray method, a dipping method, a diquarter method, or a screen printing method. When a part of the adhesive layer remains on the surface of the composite layer after mechanically peeling the release layer, the part of the adhesive layer may be removed with an organic solvent that dissolves the adhesive layer. Depending on the resin constituting the adhesive layer, for example, there is a type of resin in which the adhesive force of the adhesive layer to the surface of the composite layer is significantly reduced by applying heat or irradiating ultraviolet rays. When such a resin is used, a part of the adhesive layer left on the surface of the composite layer can be easily removed by washing with water or the like after applying heat or irradiating with ultraviolet rays. Examples of the holding film include film substrates made of polyolefin, PVC, and PET. What is necessary is just to determine the thickness of the whole peeling layer suitably.

The thickness of the composite layer may be sufficient if the carbon nanotube structure or the like is embedded in the matrix. For example, the average thickness of the matrix is 5 × 10 ⁻⁸ m to 1 × 10 ⁻⁴ m. Can be illustrated. The protruding amount of the tip of the carbon / nanotube structure or the like is desirably 1.5 times or more the diameter of the carbon / nanotube structure or the like, for example. Further, the weight ratio of the carbon / nanotube structure and the like occupying the electron emission portion is preferably 0.001 to 40 when the total weight of the carbon / nanotube structure and the matrix is 100.

  As mentioned above, although this invention was demonstrated based on the preferable Example, this invention is not limited to these Examples. The configurations and structures of the cathode panel and anode panel, cold cathode field emission display device and cold cathode field emission device described in the embodiments are examples, and can be changed as appropriate. The anode panel, cathode panel, The manufacturing method of the cathode field emission display device and the cold cathode field emission device is also an example, and can be appropriately changed. Furthermore, various materials used in the manufacture of the anode panel and the cathode panel are also examples, and can be changed as appropriate. The display device has been described by taking color display as an example, but it may also be a single color display.

  In the field emission device, a mode in which one electron emission portion corresponds to one opening has been described. However, depending on the structure of the field emission device, a mode in which a plurality of electron emission portions correspond to one opening. Alternatively, one electron emission portion may correspond to a plurality of openings. Alternatively, a plurality of first openings are provided in the gate electrode, a plurality of second openings connected to the plurality of first openings in the insulating layer are provided, and one or a plurality of electron emission portions are provided. You can also.

  In the field emission device, an interlayer insulating layer 52 may be further provided on the gate electrode 13 and the insulating layer 12, and a focusing electrode 53 may be provided on the interlayer insulating layer 52. FIG. 23 shows a schematic partial end view of a field emission device having such a structure. The interlayer insulating layer 52 is provided with a third opening 54 that communicates with the first opening 14A. The convergence electrode 53 is formed by, for example, forming the band-shaped gate electrode 13 on the insulating layer 12, forming the interlayer insulating layer 52, and then patterning the interlayer insulating layer 52 in [Step-A2]. After the convergence electrode 53 is formed, the third opening 54 may be provided in the convergence electrode 53 and the interlayer insulating layer 52, and the first opening 14 </ b> A may be provided in the gate electrode 13. Depending on the patterning of the focusing electrode, it may be a focusing electrode of a type in which one or a plurality of electron emission portions or a focusing electrode unit corresponding to one or a plurality of pixels is assembled, or an effective area. Can be a converging electrode of the type covered with a sheet of conductive material. In FIG. 23, the Spindt-type field emission device is illustrated, but it is needless to say that other field emission devices can be used.

The electron emission region can also be constituted by a field emission device commonly called a surface conduction type field emission device. This surface conduction type field emission device is formed on a support made of glass, for example, tin oxide (SnO ₂ ), gold (Au), indium oxide (In ₂ O ₃ ) / tin oxide (SnO ₂ ), carbon, palladium oxide ( A pair of electrodes made of a conductive material such as (PdO), having a small area and arranged with a predetermined gap (gap) are formed in a matrix. A carbon thin film is formed on each electrode. The row direction wiring is connected to one electrode of the pair of electrodes, and the column direction wiring is connected to the other electrode of the pair of electrodes. By applying a voltage to the pair of electrodes, an electric field is applied to the carbon thin films facing each other across the gap, and electrons are emitted from the carbon thin film. By causing the electrons to collide with the phosphor region on the anode panel, the phosphor region is excited to emit light, and a desired image can be obtained.

FIG. 1A conceptually shows voltage application states to the cathode electrode, the gate electrode, and the inspection electrode in the conditioning process in the cathode panel conditioning method and the cold cathode field emission display manufacturing method of Example 1. FIG. 1B shows a constant voltage applied to the cathode electrode and a gate electrode in the conditioning process in the cathode panel conditioning method and the cold cathode field emission display device manufacturing method of the first embodiment. 2 schematically shows a pulsed voltage applied to. 2A is a diagram conceptually illustrating a voltage application state to the cathode electrode, the gate electrode, and the anode electrode in the conditioning method of the cold cathode field emission display device of Example 2, and FIG. B) schematically shows a constant voltage applied to the cathode electrode and a pulsed voltage applied to the gate electrode in the conditioning method of the cold cathode field emission display of the second embodiment. FIG. 3A conceptually shows the voltage application state to the cathode electrode, gate electrode, and inspection electrode in the conditioning process in the cathode panel conditioning method and cold cathode field emission display manufacturing method of Example 3. FIG. 3B shows a constant voltage applied to the cathode electrode and the gate electrode in the conditioning process in the cathode panel conditioning method and the cold cathode field emission display device manufacturing method of Example 3. FIG. 2 schematically shows a constant voltage applied to the anode electrode. FIG. 4A shows a voltage application state to the cathode electrode, the gate electrode, and the inspection electrode in the modification example of the conditioning process in the cathode panel conditioning method and the cold cathode field emission display manufacturing method according to the third embodiment. FIG. 4B is a diagram showing a cathode electrode and a gate electrode in a modification of the conditioning process in the cathode panel conditioning method and the cold cathode field emission display manufacturing method of Example 3. FIG. 2 schematically shows a constant voltage applied to the electrode and a pulsed voltage applied to the anode electrode. FIG. 5A is a diagram conceptually illustrating a voltage application state to the cathode electrode, the gate electrode, and the inspection electrode in the conditioning method of the cold cathode field emission display device of Example 4. FIG. (B) schematically illustrates a constant voltage applied to the cathode electrode and the gate electrode and a constant voltage applied to the anode electrode in the conditioning method of the cold cathode field emission display device of Example 4. FIG. . FIG. 6A is a diagram conceptually illustrating a voltage application state to the cathode electrode, the gate electrode, and the inspection electrode in a modification of the conditioning method of the cold cathode field emission display device of Example 4. FIG. 6B schematically shows a constant voltage applied to the cathode electrode and the gate electrode and a pulsed voltage applied to the anode electrode in a modification of the conditioning method of the cold cathode field emission display device of the fourth embodiment. This is schematically illustrated. FIG. 7 is a conceptual diagram of a conditioning chamber suitable for use in the first or third embodiment. FIG. 8 is a conceptual partial end view of a cold cathode field emission display having a Spindt type cold cathode field emission device. FIG. 9 is a conceptual partial end view of a cold cathode field emission display having a flat type cold cathode field emission device. FIG. 10 is a schematic exploded perspective view of a part of a cathode panel and an anode panel in a cold cathode field emission display. FIG. 11 is a layout diagram schematically showing the layout of the barrier ribs, spacers, and phosphor regions in the anode panel constituting the cold cathode field emission display. FIG. 12 is a layout diagram schematically showing the layout of the barrier ribs, spacers, and phosphor regions in the anode panel constituting the cold cathode field emission display. FIG. 13 is a layout diagram schematically showing the layout of barrier ribs, spacers, and phosphor regions in an anode panel constituting a cold cathode field emission display. FIG. 14 is a layout diagram schematically showing the layout of the barrier ribs, spacers, and phosphor regions in the anode panel constituting the cold cathode field emission display. FIG. 15 is a layout diagram schematically showing the layout of the barrier ribs, spacers, and phosphor regions in the anode panel constituting the cold cathode field emission display. FIG. 16 is a layout diagram schematically showing the layout of barrier ribs, spacers, and phosphor regions in an anode panel constituting a cold cathode field emission display. 17A and 17B are schematic partial end views of a support and the like for explaining a method of manufacturing a Spindt-type cold cathode field emission device. 18 (A) and 18 (B) are schematic partial end views of a support and the like for explaining the manufacturing method of the Spindt-type cold cathode field emission device following FIG. 17 (B). . 19A to 19C are schematic partial end views of a support and the like for explaining a method of manufacturing a flat cold cathode field emission device. 20A and 20B are schematic partial end views of a support and the like for explaining a method for manufacturing a flat cold cathode field emission device following FIG. 19C. . FIGS. 21A and 21B are schematic partial end views of a support and the like for explaining a method for manufacturing a flat cold cathode field emission device, following FIG. 20B. . 22A to 22C are schematic partial end views of a support and the like for explaining another method of manufacturing a flat cold cathode field emission device. FIG. 23 is a schematic partial end view of a Spindt-type cold cathode field emission device having a focusing electrode.

Explanation of symbols

CP ... cathode panel, AP ... anode panel, 10 ... support, 11 ... cathode electrode, 12 ... insulating layer, 13 ... gate electrode, 14, 14A, 14B ... Opening part, 15, 115 ... Electron emission part, 16 ... Release layer, 17 ... Conductive material layer, 20 ... Substrate, 21 ... Partition, 22, 22R, 22G, 22B ... Phosphor region, 23 ... black matrix, 24 ... anode electrode, 25 ... spacer, 26 ... spacer holding part, 31 ... cathode electrode control circuit, 32 ... gate electrode control circuit, 33 ... Anode electrode control circuit, 40 ... carbon nanotube, 41 ... matrix, 42 ... composite layer, 43 ... release layer, 44 ... adhesive layer, 45 ... hold Film, 46 ... second Disc material layer, 47 ... Mask layer, 52 ... Interlayer insulating layer, 53 ... Converging electrode, 54 ... Third opening, 100 ... Chamber (conditioning device), 101 ... Housing , 102 ... Inspection table, 103 ... Inspection table lifting cylinder, 104 ... Pin lifting cylinder, 105 ... Hole, 106 ... Pressure gauge, 107 ... Valve, 108 ... Inspection voltage Application unit, 110 ... inspection substrate, 111 ... inspection electrode (conditioning electrode), 112 ... voltage control means

Claims (15)

(A) A plurality of strip-like cathode electrodes formed on the support and extending in the first direction;
(B) an insulating layer formed on the cathode electrode and the support;
(C) a plurality of strip-shaped gate electrodes formed on the insulating layer and extending in a second direction different from the first direction;
(D) one or a plurality of openings provided in a portion of the gate electrode and the insulating layer located in an overlapping region where the cathode electrode and the gate electrode overlap, and the cathode electrode exposed at the bottom; and
(E) an electron emission region having an electron emission portion located on the cathode electrode, which is located in the overlapping region where the cathode electrode and the gate electrode overlap and is exposed at the bottom of the opening,
A cathode panel comprising: a conditioning panel provided with an inspection electrode facing the electron emission region;
While evacuating the chamber for the conditioning, the application of a constant voltage V _C to the cathode electrodes, while applying a voltage V _IE to the inspection electrode, to the each gate electrode, the minimum voltage value V _{G- Apply} a pulse voltage having _MIN and maximum voltage value V _G-MAX (where V _G-MIN <V _C <V _G-MAX and V _IE is higher than V _G-MAX ) Attracting electrons emitted from the emission part to the inspection electrode ,
In actual operation, the cathode panel is driven by a line-sequential driving method with a field frequency T (Hz),
A cathode panel conditioning method in which a frequency T _G (Hz) of the pulse voltage applied to each gate electrode satisfies T _G = T / α (where 2 ≦ α ≦ 10) . (A) A plurality of strip-like cathode electrodes formed on the support and extending in the first direction;
(B) an insulating layer formed on the cathode electrode and the support;
(C) a plurality of strip-shaped gate electrodes formed on the insulating layer and extending in a second direction different from the first direction;
(D) one or a plurality of openings provided in a portion of the gate electrode and the insulating layer located in an overlapping region where the cathode electrode and the gate electrode overlap, and the cathode electrode exposed at the bottom; and
(E) an electron emission region having an electron emission portion located on the cathode electrode, which is located in the overlapping region where the cathode electrode and the gate electrode overlap and is exposed at the bottom of the opening,
A cathode panel comprising: a conditioning panel provided with an inspection electrode facing the electron emission region;
While evacuating the conditioning chamber, a constant voltage V _C is applied to each cathode electrode, and a constant voltage V _G (where V _G <V _C ) is applied to each gate electrode. From a substance that applies a voltage V _IE higher than the voltage V _C to the inspection electrode and emits electrons left as residues on the gate electrode and the insulating layer based on the electric field formed by the inspection electrode A cathode panel conditioning method that emits electrons. The method for conditioning a cathode panel according to claim 2 , wherein V _C -V _G ≥10 (volts) is satisfied. The cathode panel conditioning method according to claim 2 , wherein a constant voltage V _IE is applied to the inspection electrode. The cathode panel conditioning method according to claim 2 , wherein a pulse voltage having a minimum voltage value V _IE-MIN and a maximum voltage value V _IE is applied to the inspection electrode. In actual operation, the cathode panel is driven by a line-sequential driving method with a field frequency T (Hz),
6. The cathode panel conditioning according to claim 5 , wherein a frequency T _IE (Hz) of the pulse voltage applied to the inspection electrode satisfies T _IE = T / β (where 10 ≦ β ≦ 100). Method. (A) A plurality of strip-like cathode electrodes formed on the support and extending in the first direction;
(B) an insulating layer formed on the cathode electrode and the support;
(C) a plurality of strip-shaped gate electrodes formed on the insulating layer and extending in a second direction different from the first direction;
(D) one or a plurality of openings provided in a portion of the gate electrode and the insulating layer located in an overlapping region where the cathode electrode and the gate electrode overlap, and the cathode electrode exposed at the bottom; and
(E) an electron emission region having an electron emission portion located on the cathode electrode, which is located in the overlapping region where the cathode electrode and the gate electrode overlap and is exposed at the bottom of the opening,
And a cathode cathode electron emission display device comprising: a cathode panel comprising: a cathode panel; and an anode panel comprising a phosphor region and an anode electrode joined together at the periphery thereof,
Each gate electrode has a minimum voltage value V _G-MIN and a maximum voltage value V _G-MAX with a constant voltage V _C applied to each cathode electrode and a voltage V _A applied to the anode electrode. A pulsed voltage (where V _G-MIN <V _C <V _G-MAX is satisfied, and V _A is higher than V _G-MAX ) is applied, and electrons emitted from the electron emission unit are converted into the anode electrode Attracted to
In actual operation, the cathode panel is driven by a line-sequential driving method with a field frequency T (Hz),
A cold cathode field emission display conditioning method in which the frequency T _G (Hz) of the pulse voltage applied to each gate electrode satisfies T _G = T / α (2 ≦ α ≦ 10). . The conditioning method of a cold cathode field emission display according to claim 7 , wherein the conditioning is performed while exhausting a space between the cathode panel and the anode panel. (A) A plurality of strip-like cathode electrodes formed on the support and extending in the first direction;
(B) an insulating layer formed on the cathode electrode and the support;
(C) a plurality of strip-shaped gate electrodes formed on the insulating layer and extending in a second direction different from the first direction;
(D) one or a plurality of openings provided in a portion of the gate electrode and the insulating layer located in an overlapping region where the cathode electrode and the gate electrode overlap, and the cathode electrode exposed at the bottom; and
(E) an electron emission region having an electron emission portion located on the cathode electrode, which is located in the overlapping region where the cathode electrode and the gate electrode overlap and is exposed at the bottom of the opening,
And a cathode cathode electron emission display device comprising: a cathode panel comprising: a cathode panel; and an anode panel comprising a phosphor region and an anode electrode joined together at the periphery thereof,
In a state where a constant voltage V _C is applied to each cathode electrode and a constant voltage V _G (where V _G <V _C ) is applied to each gate electrode, the anode electrode is higher than the voltage V _{C. A} cold cathode field emission display device that emits electrons from a substance that emits electrons left as residues on the gate electrode and the insulating layer based on an electric field formed by the anode electrode by applying a voltage V _A Conditioning method. The conditioning method of the cold cathode field emission display according to claim 9 , wherein V _C -V _G ≥10 (volt) is satisfied. The conditioning method of a cold cathode field emission display according to claim 9 , wherein a constant voltage V _A is applied to the anode electrode. The conditioning method of the cold cathode field emission display according to claim 9 , wherein a pulse voltage having a minimum voltage value V _A-MIN and a maximum voltage value V _A is applied to the anode electrode. In actual operation, the cathode panel is driven by a line-sequential driving method with a field frequency T (Hz),
13. The cold cathode field emission according to claim 12 , wherein a frequency T _A (Hz) of the pulse voltage applied to the anode electrode satisfies T _A = T / β (10 ≦ β ≦ 100). A method for conditioning a display device. The conditioning method for a cold cathode field emission display according to claim 9 , wherein the conditioning is performed while exhausting a space between the cathode panel and the anode panel. (A) A plurality of strip-like cathode electrodes formed on the support and extending in the first direction;
(B) an insulating layer formed on the cathode electrode and the support;
(C) a plurality of strip-shaped gate electrodes formed on the insulating layer and extending in a second direction different from the first direction;
(D) one or a plurality of openings provided in a portion of the gate electrode and the insulating layer located in an overlapping region where the cathode electrode and the gate electrode overlap, and the cathode electrode exposed at the bottom; and
(E) an electron emission region having an electron emission portion located on the cathode electrode, which is located in the overlapping region where the cathode electrode and the gate electrode overlap and is exposed at the bottom of the opening,
After disposing the cathode panel provided with the inside of the conditioning chamber provided with the inspection electrode facing the electron emission region,
While evacuating the conditioning chamber, a constant voltage V _C is applied to each cathode electrode, and a constant voltage V _G (where V _G <V _C ) is applied to each gate electrode. From a substance that applies a voltage V _IE higher than the voltage V _C to the inspection electrode and emits electrons left as residues on the gate electrode and the insulating layer based on the electric field formed by the inspection electrode Conditioning process to emit electrons,
A method for manufacturing a cold cathode field emission display device, wherein the cathode panel obtained in this manner and an anode panel provided with a phosphor region and an anode electrode formed on a substrate are joined at the peripheral edge thereof.

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