JP4671470B2 - 有機ランド・グリッド・アレイ・パッケージ、基板、有機基板、集積回路パッケージ及び回路アセンブリ - Google Patents

有機ランド・グリッド・アレイ・パッケージ、基板、有機基板、集積回路パッケージ及び回路アセンブリ Download PDF

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Publication number
JP4671470B2
JP4671470B2 JP2000173780A JP2000173780A JP4671470B2 JP 4671470 B2 JP4671470 B2 JP 4671470B2 JP 2000173780 A JP2000173780 A JP 2000173780A JP 2000173780 A JP2000173780 A JP 2000173780A JP 4671470 B2 JP4671470 B2 JP 4671470B2
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Japan
Prior art keywords
layer
apertures
substrate
spacing
degassing
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Expired - Fee Related
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JP2000173780A
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English (en)
Japanese (ja)
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JP2001015643A (ja
JP2001015643A5 (https=
Inventor
ロンキアン・エル・ズウ
ヒューオン・ティー・ド
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Intel Corp
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Intel Corp
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Publication of JP2001015643A5 publication Critical patent/JP2001015643A5/ja
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/0245—Lay-out of balanced signal pairs, e.g. differential lines or twisted lines
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
    • H05K1/0253—Impedance adaptations of transmission lines by special lay-out of power planes, e.g. providing openings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/20—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
    • H10W42/261—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons characterised by their shapes or dispositions
    • H10W42/267—Patterned shielding planes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H05K1/0224—Patterned shielding planes, ground planes or power planes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09227—Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09681—Mesh conductors, e.g. as a ground plane
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1178—Means for venting or for letting gases escape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
    • H10W44/203—Electrical connections
    • H10W44/216—Waveguides, e.g. strip lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/655—Fan-out layouts
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S428/00—Stock material or miscellaneous articles
    • Y10S428/901—Printed circuit
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2000173780A 1999-06-11 2000-06-09 有機ランド・グリッド・アレイ・パッケージ、基板、有機基板、集積回路パッケージ及び回路アセンブリ Expired - Fee Related JP4671470B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/330648 1999-06-11
US09/330,648 US6303871B1 (en) 1999-06-11 1999-06-11 Degassing hole design for olga trace impedance

Publications (3)

Publication Number Publication Date
JP2001015643A JP2001015643A (ja) 2001-01-19
JP2001015643A5 JP2001015643A5 (https=) 2005-09-02
JP4671470B2 true JP4671470B2 (ja) 2011-04-20

Family

ID=23290678

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000173780A Expired - Fee Related JP4671470B2 (ja) 1999-06-11 2000-06-09 有機ランド・グリッド・アレイ・パッケージ、基板、有機基板、集積回路パッケージ及び回路アセンブリ

Country Status (3)

Country Link
US (1) US6303871B1 (https=)
JP (1) JP4671470B2 (https=)
TW (1) TW463338B (https=)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20080024239A (ko) * 1998-09-17 2008-03-17 이비덴 가부시키가이샤 다층빌드업배선판
US6225687B1 (en) * 1999-09-02 2001-05-01 Intel Corporation Chip package with degassing holes
US20020003049A1 (en) * 1999-12-29 2002-01-10 Sanjay Dabral Inline and "Y" input-output bus topology
US6496081B1 (en) * 2001-09-28 2002-12-17 Lsi Logic Corporation Transmission equalization system and an integrated circuit package employing the same
JP3864093B2 (ja) * 2002-01-10 2006-12-27 シャープ株式会社 プリント配線基板、電波受信用コンバータおよびアンテナ装置
JP4154391B2 (ja) * 2003-01-30 2008-09-24 富士通株式会社 半導体装置
US7292452B2 (en) * 2004-06-10 2007-11-06 Intel Corporation Reference layer openings
US20060060379A1 (en) * 2004-09-20 2006-03-23 Mao Tseng F Printed circuit board structure
KR101077410B1 (ko) * 2009-05-15 2011-10-26 삼성전기주식회사 방열부재를 구비한 전자부품 내장형 인쇄회로기판 및 그 제조방법
US9864829B2 (en) * 2015-04-20 2018-01-09 Toshiba Memory Corporation Multilayer substrate, design method of multilayer substrate, manufacturing method of semiconductor device, and recording medium
KR102495574B1 (ko) 2018-12-18 2023-02-03 삼성전자주식회사 반도체 패키지
US11417821B2 (en) * 2019-03-07 2022-08-16 Northrop Grumman Systems Corporation Superconductor ground plane patterning geometries that attract magnetic flux

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4859806A (en) * 1988-05-17 1989-08-22 Microelectronics And Computer Technology Corporation Discretionary interconnect
JPH0397973U (https=) * 1990-01-29 1991-10-09
JPH07123150B2 (ja) * 1992-03-06 1995-12-25 インターナショナル・ビジネス・マシーンズ・コーポレイション ハイブリッド半導体モジュール
US5410107A (en) * 1993-03-01 1995-04-25 The Board Of Trustees Of The University Of Arkansas Multichip module
JPH06291216A (ja) * 1993-04-05 1994-10-18 Sony Corp 基板及びセラミックパッケージ
CA2099477A1 (en) * 1993-06-30 1994-12-31 Guy M. Duxbury Printed circuit board
AU5238898A (en) * 1996-11-08 1998-05-29 W.L. Gore & Associates, Inc. Method for reducing via inductance in an electronic assembly and device
US6184477B1 (en) * 1998-12-02 2001-02-06 Kyocera Corporation Multi-layer circuit substrate having orthogonal grid ground and power planes

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Publication number Publication date
JP2001015643A (ja) 2001-01-19
US6303871B1 (en) 2001-10-16
TW463338B (en) 2001-11-11

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