JP4663852B2 - Image data converter for time-division gradation display in frame - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an image data conversion apparatus for an intra-frame time-division gradation display system, particularly two or more frame memories, and when writing image data to one frame memory, The present invention relates to an image data conversion apparatus that can continuously convert image data of an intra-frame time-division gradation display system by reading image data from the frame memory.
[0002]
[Prior art]
Recently, a flat type display device such as a plasma display panel has attracted attention as a display device. This type of display device display driving method is an intra-frame time-division gray scale display method, in which an image of one frame is divided into images of a plurality of subfields having different weights, and is divided during a display period of one frame. A system is adopted in which the images of all subfields are sequentially displayed one subfield at a time.
[0003]
However, since the received image signal has a signal form suitable for a display that is displayed by a raster scan method such as a CRT, the time-division gradation display method in the frame is used when the image signal is displayed by the flat display device. It is necessary to convert it into image data suitable for. In this conversion, first, without changing the time axis of the received image data, for each pixel data, a first conversion process is performed to re-express the value with the weight of each subfield constituting one frame, Subsequently, the image data subjected to the first conversion process is accumulated for one screen, and the second conversion process for sequentially extracting the weight data belonging to the same subfield as one subfield data is performed on the entire surface elementary data. Executed.
[0004]
In the signal conversion, in order to continuously perform the second conversion process without interruption between frames, two frame memories are provided, while image data is accumulated in one frame memory, It is necessary to read image data from one frame memory in units of subframes.
FIG. 5 shows a conventional circuit for performing the above-described second conversion process without interruption between frames. In the figure, 510 and 520 are frame memories, 530 is an image data writing circuit, 540 is a reading circuit, and 550 is a control signal switching control circuit. The image data writing circuit 530 includes a writing buffer memory 5301, a writing operation control circuit 5302, and bus control circuits 5303 and 5304. The read circuit 540 includes a read operation control circuit 5401, an input selection circuit 5402, and a read buffer 5403.
[0005]
The write buffer memory 5301 includes two line memories. Under the control of the write operation control circuit 5302, the input write data is alternately written into the two line memories in synchronization with the operation clock. The frame memory 510 (520) in which the image data is read out from the line memory after writing in synchronization with the operation clock and the writing is permitted by the bus control circuits 5303 and 5304 and the control signal switching circuit 550 because of the opposite phase. ), Image data is written line by line. When the image for one frame is completely written to one frame memory 510 (520), the control signal switching circuit 550 switches the frame memory and starts writing image data to the other frame memory 520 (510). To do.
[0006]
On the other hand, with respect to the frame memory for which writing has been completed, the input selection circuit 5402 reads image data under the control of the reading operation control circuit 5401.
Reading performed by the input selection circuit 5402 is performed in units of subfields. That is, data belonging to the same subfield is read from all lines in the frame memory in synchronization with the operation clock from the image data written in the frame memory. The read subfield data is sequentially stored in the read buffer 5403 , and when the subfield data for all lines has been stored, the subfield data is output to the subsequent plasma display driving circuit (not shown). Thus, the input selection circuit 5402 reads out the next-order subfield data from the frame memory, outputs the subfield data from the read buffer 5403, and repeats this until the last subfield data is read out. Execute.
[0007]
[Problems to be solved by the invention]
By the way, when performing the process of converting the image data into the subfield data as described above, a higher frequency operation clock is required because the image data is repeatedly read for each subfield rather than being written into the frame memory. become.
For example, VGA wide (480 × 852 pixels), the number of subfields is Sn = 1
2. When the read cycle is Ta = 1.5 μs , the write horizontal frequency is fh = 32 kHz, and the data bus width of the frame memory is 32 bits, the operation clock frequency fw at the time of write is
fw = f h × 852 × 3 × Sn / 32 = about 30 MHz
It becomes. On the other hand, the operating clock frequency during reading is
f r = (1 / Ta) × 852 × 3/32 = about 53 MHz
It becomes.
[0008]
This way the frequency of the read clock of the write clock is the different ing, conventional did not give due to the use of single operation clock, forced using the high-speed side clock (read clock) .
However, if a single clock is used, the writing circuit side must perform processing faster than necessary, and in addition to the operational and energy loss issues that power and heat generation increase accordingly. As a write buffer, a type that operates at high speed is required, and an increase in circuit cost is inevitable.
[0009]
SUMMARY OF THE INVENTION In view of the above-described problems, the present invention provides an image data conversion apparatus that can use a low-speed write buffer and that consumes less power and heat and that is practical for an intra-frame time-division gradation display method. Objective.
[0010]
[Means for solving the problems]
In order to achieve the above object, an image data conversion apparatus to an intra-frame time-division gradation display system according to the present invention writes image data in time series for each scan line in two or more frame memories and the frame memory. A writing circuit, a reading circuit that divides the image data in the frame memory into a plurality of gradation data, and sequentially reads out each divided gradation data, and when image data is written to one frame memory, A switching control circuit for switching the frame memory so as to read the image data from the one frame memory, and a write operation clock for the frame memory switched to write the image data to read the image data the frame memory switching was to perform read frequency is higher than the write operation clock Provided to a clock switching circuit for switching the operating clock to supply an operation clock, the clock switching circuit, during clock switching, the other from the time the one transitions to a low level of a write operation clock and the read operation clock It includes a configuration in which the clock to the frame memory is stopped for a period of at least one clock period until the time of transition to the high level .
[0011]
Here, before Symbol clock switching circuit may be in the blanking period without transferring data to the frame memory for switching clock.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows an embodiment of an image data conversion apparatus to an intra-frame time division gradation display system according to the present invention.
[0013]
[Overall configuration]
Basically, it consists of two frame memories 10 and 20, a write circuit 30, a read circuit 40 and a frame memory switching control circuit 50.
The frame memories 10 and 20 have a storage area for each subfield, and the storage area of each subfield has a capacity for storing binary data corresponding to the number of pixels of the plasma display panel. Therefore, in order to visualize this in an easy-to-understand manner in the drawing, each frame memory 10, 20 is drawn by the number of subfields.
[0014]
The write circuit 30 includes a write buffer memory 301, a write operation control circuit 302, and bus control circuits 303 and 304 similar to those shown in the conventional example. The difference from the conventional write circuit is that a write-only operation clock is used as the operation clock, and the phase assurance circuit 305 is provided due to this.
The read circuit 40 includes the same input selection circuit 401, read buffer 402, and read operation control circuit 403 as those shown in the conventional example. The difference from the conventional read circuit is that a read-only operation clock is used as the operation clock, and the phase assurance circuit 404 is provided due to this.
[0015]
The frame memory switching control circuit 50 includes a clock switching circuit 501 for switching the operation clock between writing and reading to the frame memories 10 and 20, and a chip select signal for selecting which frame memory to operate. Control signal switching circuits 502 and 503 that are switched in synchronization with the switching.
In addition to the above circuit, the present embodiment includes a blanking detection circuit 601. This circuit 601 detects a vertical synchronization signal of the received image data and generates a clock switching signal at the start of the retrace time.
[0016]
[Configuration Specific to this Embodiment]
The write operation clock has a frequency of about 30 MHz, and the read operation clock has a frequency of about 53 MHz. The reason why the write operation clock is set to the above frequency is based on the calculation described in the prior art. The clock of this frequency can be used as it is the dot clock used when processing the video signal on the upper side of this circuit, or it can be generated by extracting the horizontal sync signal and multiplying it. I can do it. As the read operation clock, a conventionally used clock is used.
[0017]
Of the control signals supplied to the frame memories 10 and 20, the phase assurance circuits 305 and 404 output a chip select (CS) signal in the phase shown in FIG. 2B, but control signals other than the CS signal are shown in FIG. As shown in FIG. 2 (d), this is a circuit that guarantees the phase so as to keep the “Valid” state for a period of one clock cycle before and after the period when the chip select (CS) signal is low.
[0018]
Although this circuit is not shown, for example, a counter that counts the write operation clock and the read operation clock and is reset by the CS signal, and when the counter reaches a count value “K1” corresponding to one clock cycle and When the value “R−K1” smaller than the reset value “R” by a count corresponding to one clock cycle is reached, the control signal other than the CS signal is changed from “Don`t care” to “Valid”, or Can be composed of a circuit for performing the reverse process and a circuit for outputting the CS signal as it is.
[0019]
In this way, control signals other than the CS signal are held in “Valid” for a period longer than the “Valid” period of the CS signal. Therefore, even if the control signal other than the chip select (CS) signal is delayed, the clock setup is performed. • A hold period margin can be secured. As a result, it is sufficient to use a delay adjustment circuit only for the CS signal, and a high-speed frame memory operation can be guaranteed even if a clock switching circuit is added in the subsequent stage. 2A is a write or read operation clock, and FIG. 2C is a waveform diagram of control signals other than the CS signal used in the conventional apparatus.
[0020]
The control signal switching circuits 502 and 503 are configured to switch between a control signal output from the write side phase assurance circuit 305 and a control signal output from the read side phase assurance circuit 404 in accordance with the switching signal supplied from the blanking detection circuit 601. Switch. In this case, the two control signal switching circuits 502 and 503 are exactly reversed so that when one selects the control signal output from the write side phase assurance circuit 305, the other selects the read side phase assurance circuit 404. It is switched according to the phase relationship.
[0021]
The clock switching circuit 501 switches between supplying a write operation clock to the frame memory at the time of writing and supplying a read operation clock at the time of reading. In this embodiment, the write operation clock and the read operation clock are switched. Since it is asynchronous, one clock cycle or more is guaranteed for switching. FIG. 3 shows a specific example of the clock switching circuit 501 that guarantees such clock switching. In the figure, T _R and T _W are flip-flops. The write operation clock WCLK and the read operation clock RCLK are output as post-switching clocks SGCLKA and SGCLKB through four AND circuits and two OR circuits. FIG. 4 is a waveform diagram for explaining the switching operation of the clock switching circuit 501. In the illustrated example, a case where a switching signal is issued at the timing “A” is shown. Then, the state of the clock transitioning to the low level is captured to switch the clock. If switching from reading to writing, the read operation clock is stopped at the timing “B”, and the output of the write operation clock is started at the timing “E”. When switching from writing to reading, the write operation clock is stopped at the timing “C”, and the output of the read operation clock is started at the timing “D”. In either case, a period of one or more clock cycles is ensured for switching. A clock SGCLKA output from the clock switching circuit 501 is supplied to the frame memory 10, and SGCLKB is supplied to the frame memory 20.
[0022]
[Operation]
According to the above configuration, the image data is written to the write buffer memory 301 line by line in synchronization with the dot clock, while the image data written to the write buffer memory 301 is read and the bus control circuit 303, The data is written into the frame memory 10 (20) selected at 304. The writing speed to the frame memory at this time is determined by the writing operation clock. In the case of this embodiment, since it is a low speed of about 30 MHz and the same speed as the dot clock, writing is performed using almost the entire period in which one frame memory is selected on the writing side.
[0023]
On the other hand, at this time, image data is sequentially read from one subfield selected by the input selection circuit 401 from the remaining frame memory 20 (10), and the plasma display panel drive (not shown) in the subsequent stage is driven through the read buffer 402. Output to the circuit. The speed at the time of reading from the frame memory at this time is as high as about 53 MHz.
[0024]
When one frame of image data has been written and read to each frame memory 10 and 20, the frame memories 10 and 20 are operated by the operations of the bus control circuits 303 and 304, the control signal switching circuits 502 and 503, and the clock switching circuit 501. Are switched, a write operation is performed on the frame memory 20 (10) that has been read, and a read operation is performed on the frame memory 10 (20) that has been written. In this switching, although the write operation clock and the read operation clock are asynchronous, the clock switching circuit 501 guarantees one clock period or more to perform the clock switching, so that the write and read operations to the frame memory are performed by the clock. It is made orderly immediately after switching.
[0025]
In the above embodiment, two frame memories are used. However, three or more frame memories can be used, and image data can be written and read using these frame memories in sequence.
In the embodiment, the clock is switched during the vertical blanking period. However, this is for normal image data captured by a scanning method in which horizontal scanning is repeated during one vertical scanning. This is because if image data captured by a scanning method in which vertical scanning is repeated during one horizontal scanning is performed, the clock may be switched during the horizontal blanking period. .
[0026]
【The invention's effect】
As described above, the image data conversion apparatus to the intra-frame time-division gradation display method according to the present invention writes the image data to the frame memory in time series for each line and the weight from the frame memory. Since the frequency of the operation clock is changed when reading data divided into data, the high-speed clock required for reading is used, while the low-speed clock is used to write image data using the full writing period when writing. As a result, the write-side circuit has the advantage that the restriction on high frequency is relaxed, the degree of freedom of design is high, and the circuit cost is low. As compared with the case where a high-speed read operation clock is used as the write operation clock, Only the power consumption reduced amount heat generation amount decreases, the stability of operation, reduction of energy loss is effective such realized.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a circuit of an image conversion apparatus to an intra-frame time division gradation display system as an embodiment of the present invention.
FIG. 2 is a waveform diagram for explaining the operation of the phase assurance circuit in FIG. 1;
FIG. 3 is a logic circuit diagram showing a specific example of a clock switching circuit.
FIG. 4 is a waveform diagram showing a clock switching operation of the clock switching circuit.
FIG. 5 is a block diagram showing a conventional image data conversion apparatus.
[Explanation of symbols]
10, 20 ... Frame memory,
30 ..... writing circuit,
40... Read circuit,
50 ... Frame memory switching control circuit,
301 ... write buffer memory,
302 ... write operation control circuit,
303, 304 ... bus control circuit,
305, 404 ... Phase assurance circuit,
401 ... Input selection circuit,
402 ... Read buffer,
403 ... Read operation control circuit,
501 ... Clock switching circuit ,
502, 503 ... Control signal switching circuit ,
601 ... Blanking detection circuit,

Claims (2)

Two or more frame memories;
A writing circuit for writing image data in time series for each scanning line to the frame memory;
A readout circuit that divides image data in the frame memory into a plurality of gradation data, and sequentially reads out the divided gradation data;
A switching control circuit for switching the frame memory so that the image data is read from the other one frame memory when the image data is being written to the one frame memory;
A write operation clock is supplied to the frame memory switched to write image data, and a read operation with a frequency higher than the write operation clock is performed to the frame memory switched to read image data. A clock switching circuit for switching the operation clock to supply a clock ,
In the clock switching, the clock switching circuit applies to the frame memory for a period of at least one clock cycle from the time when one of the write operation clock and the read operation clock changes to the low level to the time when the other changes to the high level. An apparatus for converting image data into an intra-frame time-division gradation display system, comprising a configuration for stopping a clock . Said clock switching circuit, the image data conversion apparatus into frames in the time division gray scale display method of claim 1 Symbol mounting, characterized in that the blanking period without transferring data to the frame memory for switching clock.

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