KR100578833B1 - Address data processing apparatus on plasma display panel and method thereof - Google Patents

Abstract

The present invention relates to an address data processing apparatus of a plasma display panel for efficiently using a frame memory in processing address data, and a method thereof. The data delay unit for implementing the variable subfield and applying the algorithm for reducing the image pseudo contour and the data switching unit for converting the pixel data into subfield data and rearranging the address data into the address data share the frame memory with each other. Each operation can be used. In this case, when the data delay unit and the data conversion unit are implemented as one IC, the three frame memories may be shared with each other to perform their respective functions. Through this, there is a unique effect that can further reduce the number of frame memories as compared to the conventional.

PDP, frame memory, address data

Description

Address data processing apparatus of plasma display panel and method thereof {ADDRESS DATA PROCESSING APPARATUS ON PLASMA DISPLAY PANEL AND METHOD THEREOF}

1 is a partial perspective view of an AC plasma display panel.

2 is a block diagram of an address data processing apparatus in a conventional plasma display panel.

3 is a diagram illustrating a method of reading and writing data to a frame memory by a data delay unit and a data switch unit of a conventional address data processing apparatus.

FIG. 4 is a block diagram of an address data processing apparatus in a plasma display panel according to an exemplary embodiment of the present invention, together with another driving apparatus of a plasma display panel.

5 is a diagram illustrating a method of writing and reading frame data into a frame memory in an address data processing apparatus of a plasma display panel according to an exemplary embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address data processing apparatus and method for a plasma display panel (PDP), and an address data processing apparatus and method for a plasma display panel for efficiently using a frame memory in processing address data. It is about.

Recently, flat display devices such as a liquid crystal display (LCD), a field emission display (FED), and a plasma display panel have been actively developed. Among these flat panel display devices, the plasma display panel has advantages of higher luminance and luminous efficiency and wider viewing angle than other flat panel display devices. Therefore, the plasma display panel is in the spotlight as a display device to replace a conventional cathode ray tube (CRT) in a large display device of 40 inches or more.

A plasma display panel is a flat panel display device that displays characters or images using plasma generated by gas discharge, and tens to millions or more of pixels are arranged in a matrix form according to their size. The plasma display panel is classified into a direct current type and an alternating current type according to a shape of a driving voltage waveform applied and a structure of a discharge cell.

In the DC plasma display panel, the electrode is exposed without the discharge space insulated, so that the current flows in the discharge space while the voltage is applied, and there is a disadvantage in that a resistance for current limitation must be made. On the other hand, in the AC plasma display panel, since the electrode covers the dielectric layer, the current is limited by the formation of a natural capacitance component, and thus, the electrode is protected from the impact of ions during discharge.

1 is a partial perspective view of an AC plasma display panel.

As shown in FIG. 1, the scan electrode 4 and the sustain electrode 5 covered with the dielectric layer 2 and the protective film 3 on the glass substrate 1 are formed in pairs in parallel. On the glass substrate 6, a plurality of address electrodes 8 covered with the insulator layer 7 are formed. The partition 9 is formed on the insulator layer 7 between the address electrodes 8 in parallel with the address electrode 8, and the phosphor 10 is formed on the surface of the insulator layer 7 and on both sides of the partition 9. Is formed. The glass substrates 1 and 6 are disposed to face each other with the discharge space 11 therebetween so that the scan electrode 4, the address electrode 8, the sustain electrode 5, and the address electrode 8 are orthogonal to each other. The discharge space at the intersection of the scan electrode 4 and the sustain electrode 5 paired with the address electrode 8 forms a discharge cell 12.

 In order to show performance as a color display element in such a plasma display panel, gray scale display should be possible. As a method of implementing the gray scale display, a gray scale implementation method of dividing one field into a plurality of subfields and controlling the time division is used.

At this time, each subfield can be largely divided into an address period and a sustain period. In the address period, data for each pixel is transmitted to each scan electrode and the address electrode to selectively discharge or erase each cell, and in the sustain period. The gray level is implemented while maintaining the data of each pixel.

Among these methods, the ADS (Address Display Separated) method, which is a method of completely separating an address section and a sustain section, is used as a gray scale representation method of a general plasma display panel.

In the ADS driving method, the gray scale of the plasma display panel is represented by adjusting the amount of light of sustain only, and the gray scale (level 0 to 255) of the image data is expressed using 10 to 16 subfields within one frame. .

In order to display the input RGB image data as address data of the PDP, conversion to subfield data must be performed. For example, in the case of representing RED 149 gray scales, values converted into subfield data using 12 subfields are shown in Table 1 below.

TABLE 1

On the other hand, in order to improve low gradation power or reduce pseudo contours, a variable subfield arrangement method of modifying the number of subfields or the weight (weight) of the subfields is used. In this case, a problem of data mismatch is solved. You need to use frame memory to do this. In addition, the subfield data generated for the gradation representation needs to be rearranged into address data in order to drive the plasma display panel. In this process, the subfield data needs to be stored. You need to use

2 is a block diagram of an address data processing apparatus in a conventional plasma display panel.

As shown in FIG. 2, the address data processing apparatus of the conventional plasma display panel includes an image processor 10 and a variable subfield configured to perform inverse gamma correction and error diffusion on input image signal (R, G, B) data. Subtract the pixel data output from the data delay unit 20 and the data delay unit 20 to solve the data mismatch problem generated during the arrangement and delay the frame data when applying the algorithm of moving picture pseudo contour reduction. And a data switching unit 30 generating field data and rearranging the generated subfield data into address data to drive the plasma display panel. In this case, the address data output from the data switching unit 30 is transferred to the address driver and applied to the address electrode to select a cell to be selected in the address period.

In this case, the data delay unit 20 needs two frame memories 22 and 24 to delay the frame data, and the data switching unit 30 also rearranges the generated subfield data into address data. Two frame memories 32 and 34 are required. Although the number of frame memories shown in FIG. 1 is four, more frame memories are required to process R, G, and B data separately.

3 is a diagram illustrating a method of reading and writing data into a frame memory by the data delay unit 20 and the data switch unit 30 of the conventional address data processing apparatus.

As shown in FIG. 3, the conventional data delay unit 20 and the data switching unit 30 each require two frame memories.

First, in the Nth frame, the data delay unit 20 writes the Nth frame data to the frame memory A 22 and reads the N-1th frame data from the frame memory B 24, and the data switching unit 30 The N-th frame data read from the data delay unit 20 is written to the frame memory C 32, and the N-second frame data stored in the frame memory D 34 is read.

In the next N + 1th frame, the data delay unit 20 writes the N + 1th frame data to the frame memory B 24 and reads the Nth frame data from the frame memory A 22, and the data switching unit 30 ) Writes the N-th data read from the data delay unit 20 to the frame memory D 34 and reads the N-th frame data stored in the frame memory C 32.

In the N + 2th frame, the data delay unit 20 writes the N + 2th frame data to the frame memory A 22 and reads the N + 1th frame data from the frame memory B 24, and the data switching unit ( 30 writes the N + 1th data read from the data delay unit 20 to the frame memory C 32 and reads the Nth frame data stored in the frame memory D 34.

The above method is used to repeatedly read / write the frame data and to arrange the pseudo contour reduction, the variable subfield array, and the address data. As described above, in the conventional method, Four frame memories are used. In addition, when processing R, G, and B data separately, the number of memories required is further increased. As such, when the number of the frame memories is unnecessarily large, a problem arises in that the cost increases.

SUMMARY OF THE INVENTION The present invention has been made in an effort to solve the above-described problems of the related art, and to provide a method of reducing the number of frame memories used in generating address data in a plasma display panel.

The address data processing apparatus of the plasma display panel according to the characteristics of the present invention for achieving the above object

In the plasma display panel displaying an image corresponding to the image signal by dividing an image of each field displayed on the plasma display panel into a plurality of subfields in correspondence to an input image signal, and displaying a gray scale according to the combination of the subfields. In the apparatus for processing data,

A frame memory unit including first, second and third frame memories respectively storing frame data of an input video signal;

A variable server field in which the number or weight of the subfields is changed and a data delay unit for delaying frame data of an input video signal by using the frame memory unit to reduce pseudo pseudo contours;

And a data switching unit for storing or reading frame data output from the data delay unit in order to rearrange the address data necessary for the address of each subfield. In this case, in the N-th frame of the input video signal, the data delay unit stores the N-th frame data of the input video signal in the first frame memory, and the day switching unit N-th frame stored in the third frame memory. The data is read, and the N-th frame data is stored in the second frame memory.

The address data processing method of the plasma display panel according to another aspect of the present invention

In the method of processing the address data in the plasma display panel,

(a) In the Nth frame of the input video signal, the Nth frame data is stored in the first frame memory for data delay, and the N-2th frame data stored in the second frame memory is read for address data rearrangement. Coming steps;

(b) In the N + 1 th frame of the input video signal, the N + 1 th frame data is stored in the second frame memory for data delay, and the N-1 th frame data stored in the third frame memory is address data. Reading for rearrangement;

(c) In the N + 2th frame of the input video signal, store the N + 2th frame data in the third frame memory for data delay, and rearrange the Nth frame data stored in the first frame memory. Includes steps for reading.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 4 is a block diagram of an address data processing apparatus in a plasma display panel according to an exemplary embodiment of the present invention, together with another driving apparatus of a plasma display panel.

As shown in FIG. 4, an address data processing apparatus of a plasma display panel according to an exemplary embodiment of the present invention includes an image processing unit 100 and a data processing unit 200, and the data processing processing unit includes three frame memories 700, 720, and 740. It is composed of At this time, the address data processing apparatus in the plasma display panel, and other driving apparatuses include an address driver 300, a sustain / scan pulse driver controller 400, and a sustain / scan pulse driver 400. Here, the plasma display panel 600 includes a plurality of address electrodes A1-Am arranged in the column direction, and a plurality of scan electrodes Y1-Yn and sustain electrodes X1-Xn arranged in a zigzag pattern in the row direction. It includes.

The image processor 100 appropriately performs signal processing on an externally input image signal, and includes an image signal processor 120 and a gamma correction and error diffusion unit 140.

The image signal processor 120 digitizes an image signal input from the outside and generates digital image data.

The gamma correction and error diffusion unit 140 receives the digital image data output from the image signal processing unit 120 to correct the gamma value according to the characteristics of the PDP and to diffuse the display error to the surrounding pixels for error diffusion processing. Process and output.

The data processor 200 processes address data for display on the plasma display panel 300 using an input image signal, and includes a data delay unit 220 and a data switch unit 240. In this case, the data delay unit 200 includes a data delay unit 220 and a data switching unit 240, which are included in one integrated circuit (IC) to perform their respective functions.

The data delay unit 220 generates a variable subfield array when the video signal output from the image processing unit 100 is generated as subfield data (that is, the number of subfields or the subfield weights change according to the input video signal). In the case of generating a PDP or applying a pseudo contour reduction algorithm, the frame data is delayed using a frame memory. In other words, in order to solve the data mismatch problem generated in generating the variable subfield, the frame data (meaning the pixel data of one frame) is delayed using the frame memory, and the current input is performed to reduce the pseudo image contour. In order to compare the data of the frame to be inputted with the data of a previously input frame, the frame data (meaning pixel data of one frame) is delayed using the frame memory.

The data switching unit 240 generates delayed frame data (meaning pixel data) transmitted from the data delay unit 220 as subfield data, and converts the generated subfield data into address data to drive the plasma display panel. Rearrange Here, the data switcher 240 includes a subfield generator 242 and a memory controller 244.

The subfield generator 242 receives the frame data delayed by the data delay unit 220 and generates subfield data corresponding to the frame data. In this case, the subfield generator 242 may generate a variable subfield array using the frame data delayed by the data delay unit 220, and may appropriately change the subfield weights to reduce video pseudo contours. Since the method of generating the variable subfield array and the specific method of reducing the video pseudo contour are not directly related to the present invention, the detailed description thereof will be omitted below.

The memory controller 224 rearranges the subfield data transmitted from the subfield generator 242 into address data for driving the plasma display panel. The subfields are separated for each subfield for all subfields of one frame. The address data for all pixels of each subfield is read from the frame memory by storing them in the frame memory as stars (that is, subfield data information of all the pixels of one frame are separated for each subfield and stored according to the subfields). .

5 is a diagram illustrating a method of writing and reading frame data into a frame memory in an address data processing apparatus of a plasma display panel according to an exemplary embodiment of the present invention.

As shown in FIG. 5, the data delay unit 220 and the data switching unit 240 are implemented in one IC called the data processing unit 200, and write frame data using three frame memories 700, 720, and 730. Read.

First, in the Nth frame, the data delay unit 220 writes the Nth frame data to the frame memory A '700 for the variable subfield arrangement and the video pseudo contour, and the data switching unit 240 stores each of the address data. The N-2 th frame data stored in the frame memory C ′ 740 is read in advance for rearrangement by subfield. In this case, the N-1 th frame data is stored in the frame memory B'720, and the subfield generator 242 compares the N-1 th frame data with the N th frame currently input, The subfield for reducing the pseudo pseudo contour of the moving picture is generated and stored to transmit the subfield to the memory controller 244.

In the N + 1 th frame, the data delay unit 220 writes the N + 1 th frame data into the frame memory C'700 for the variable subfield arrangement and the pseudo pseudo contour, and the data switching unit 240 performs the address data. The N−1 th frame data stored in the frame memory B ′ 720 is read in advance for rearrangement. In this case, the N th frame data is stored in the frame memory A '700, and the subfield generator 242 compares the N th frame data with the N + 1 th frame that is currently input to form a variable subfield array and a video pseudo. The subfields for contour reduction are generated and stored for transmission to the memory controller 244.

Next, in the N + 2th frame, the data delay unit 220 writes the N + 2th frame data to the frame memory B'700 for the variable subfield arrangement and the pseudo pseudo contour, and the data switching unit 240 The N th frame data stored in the frame memory A '700 is read in advance in order to rearrange the address data. In this case, the N + 1 th frame data is stored in the frame memory C'720, and the subfield generator 242 compares the N + 1 th frame data with the N + 2 th frame currently input to the variable subfield. Subfield data for array and video pseudo contour reduction are generated and stored for transmission to the memory controller 244.

As described above, since the data delay unit 220 and the data switching unit 240 are implemented in one IC and share the frame memory, it can be seen that address data can be processed using three frame memories.

The address driver 300 applies the address electrodes A1, A2, ... Am of the plasma panel 600 in response to the address data output from the memory controller 244.

On the other hand, the sustain / scan pulse drive control unit 400 generates and maintains the number of sustain pulses corresponding to the subfield array (which is determined according to the load ratio detected by the APC unit although not shown in FIG. 4) and the subfield array structure. The scan pulse driver 500 outputs the scan pulse.

The sustain / scan pulse driver 500 generates sustain pulses and scan pulses based on the subfield array structure output from the sustain / scan pulse drive controller 400 to generate the scan electrodes X1, X2, and the scan pulses of the plasma panel 600. Xn) and sustain electrodes Y1, Y2, ..., Yn.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, since the data delay unit and the data switching unit are implemented as one, it can be seen that address data can be processed using three frame memories because the frame memories are shared. This reduces the number of memory, which has the unique effect of reducing the price.

Claims (9)

In the plasma display panel displaying an image corresponding to the image signal by dividing an image of each field displayed on the plasma display panel into a plurality of subfields in correspondence to an input image signal, and displaying a gray scale according to the combination of the subfields. In the apparatus for processing data, A frame memory unit including first, second and third frame memories respectively storing frame data of an input video signal; A data delay unit configured to delay frame data of an input video signal by using the frame memory unit to reduce pseudo server contours and variable server fields in which the number or weight of the subfields is changed; And a data switching unit for storing or reading frame data output from the data delay unit in order to rearrange the address data necessary for the address of each subfield, The data delay unit and the data switching unit share the first, second and third frame memories of the frame memory unit, In the Nth frame of the input video signal, the data delay unit stores the Nth frame data of the input video signal in the first frame memory, and the day switching unit stores the N-2th frame data stored in the third frame memory. And an N-th frame data is stored in the second frame memory. delete The method of claim 1, The data delay unit and the data switching unit is implemented by one IC (IC) address data processing apparatus of the plasma display panel. The method of claim 1, The data conversion unit A subfield generation unit receiving frame data delayed by the data delay unit and generating subfield data corresponding to the frame data; Address data of the plasma display panel including a memory controller which stores or reads frame data in the frame memory unit to rearrange the subfield data transmitted from the subfield generator into address data for driving the plasma display panel. Processing unit. delete In the method of processing the address data in the plasma display panel, (a) In the Nth frame of the input video signal, the Nth frame data is stored in the first frame memory for data delay, and the N-2th frame data stored in the second frame memory is read for address data rearrangement. Coming steps; (b) In the N + 1 th frame of the input video signal, the N + 1 th frame data is stored in the second frame memory for data delay, and the N-1 th frame data stored in the third frame memory is address data. Reading for rearrangement; (c) In the N + 2th frame of the input video signal, store the N + 2th frame data in the third frame memory for data delay, and rearrange the Nth frame data stored in the first frame memory. Include steps to read for And the first, second and third frame memories are shared with each other for the data delay and the rearrangement of the address data. delete The method of claim 6, The data delay may be implemented as a variable subfield in driving the image displayed on the plasma display panel into a plurality of subfields or delaying data of the input image signal to reduce video pseudo contour. The address data processing method of the panel. delete

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