KR100536220B1 - A driving apparatus of plasma panel, a method for displaying pictures on plasma display panel and a plasma display panel - Google Patents

Abstract

The present invention relates to a driving apparatus of a plasma display panel for controlling address power consumption and an image processing method of the plasma display panel. When it is determined that the input image signal data is data having high address power consumption, and determines that the power consumption is high, the subfield data is generated such that the data of the low weight subfield are the same. At this time, whether the address power consumption is high or not is determined using a system of adjacent upper and lower lines of the same column or using subfield data. Accordingly, when it is determined that the power consumption is high, the address power consumption can be further reduced by making the data of the subfield having the low subfield weight equal.

Description

A driving apparatus of a plasma display panel, an image processing method of a plasma display panel, and a plasma display panel {A DRIVING APPARATUS OF PLASMA PANEL, A METHOD FOR DISPLAYING PICTURES ON PLASMA DISPLAY PANEL AND A PLASMA DISPLAY PANEL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving apparatus for a plasma display panel (PDP) and an image processing method for a plasma display panel, and more particularly to an apparatus for driving a plasma display panel for controlling address power consumption and an image processing method for a plasma display panel. It is about.

Recently, flat display devices such as a liquid crystal display (LCD), a field emission display (FED), and a plasma display panel have been actively developed. Among these flat panel display devices, the plasma display panel has advantages of higher luminance and luminous efficiency and wider viewing angle than other flat panel display devices. Therefore, the plasma display panel is in the spotlight as a display device to replace a conventional cathode ray tube (CRT) in a large display device of 40 inches or more.

A plasma display panel is a flat panel display device that displays characters or images using plasma generated by gas discharge, and tens to millions or more of pixels are arranged in a matrix form according to their size. The plasma display panel is classified into a direct current type and an alternating current type according to a shape of a driving voltage waveform applied and a structure of a discharge cell.

In the DC plasma display panel, the electrode is exposed without the discharge space insulated, so that the current flows in the discharge space while the voltage is applied, and there is a disadvantage in that a resistance for current limitation must be made. On the other hand, in the AC plasma display panel, since the electrode covers the dielectric layer, the current is limited by the formation of a natural capacitance component, and the electrode is protected from the impact of ions during discharge.

1 is a partial perspective view of an AC plasma display panel.

As shown in FIG. 1, the scan electrode 4 and the sustain electrode 5 covered with the dielectric layer 2 and the protective film 3 on the glass substrate 1 are formed in pairs in parallel. The dielectric layer 2 is formed on the back of the scan electrode 4 and the back of the sustain electrode 5 so as to control the discharge current during discharge and to easily generate wall charges. The protective film 3 is made of magnesium oxide (MgO) and protects the panel from a strong electric field. On the glass substrate 6, a plurality of address electrodes 8 covered with the insulator layer 7 are formed. The partition 9 is formed on the insulator layer 7 between the address electrodes 8 in parallel with the address electrode 8, and the phosphor 10 is formed on the surface of the insulator layer 7 and on both sides of the partition 9. Is formed. The glass substrates 1 and 6 are disposed to face each other with the discharge space 11 therebetween so that the scan electrode 4, the address electrode 8, the sustain electrode 5, and the address electrode 8 are orthogonal to each other. The discharge space at the intersection of the scan electrode 4 and the sustain electrode 5 paired with the address electrode 8 forms a discharge cell 12.

2 shows an electrode arrangement diagram of the plasma display panel.

As shown in FIG. 2, the electrodes of the plasma display panel are arranged in a matrix of m × n. Specifically, the address electrodes A1 -Am are arranged in the column direction and n rows of scan electrodes in the row direction ( Y1-Yn and sustain electrodes X1-Xn are arranged in a zigzag. The discharge cell 12 of FIG. 2 corresponds to the discharge cell 12 of FIG.

In general, the driving method of the AC plasma display panel includes a reset period, an address period, and a sustain period.

The reset period is a period for initializing the state of each cell in order to smoothly perform an addressing operation on the cell. The address period is an address voltage for a cell (addressed cell) that is turned on to select a cell that is turned on and a cell that is not turned on. It is a period of time to perform the operation of accumulating wall charge by applying a. The sustain period is a period in which a discharge is applied to actually display an image in the addressed cells by applying a sustain pulse.

Here, when each operation of each subfield is performed in the above manner, the discharge space between the scan electrode and the sustain electrode, the surface on which the address electrode is formed and the surface on which the scan and sustain electrode are formed act as a capacitive load. There is capacitance in the panel. Therefore, in order to apply the waveform for addressing, a lot of reactive power for charge injection that generates a predetermined voltage in capacitance other than power for address discharge is required. At this time, when the number of switching of the address electrodes is large, address power is consumed even more.

As described above, the address power is generated more due to the number of switching of the address electrode, which will be described in detail below.

3 is a view showing image data at full white.

Referring to FIG. 3, when full white, all data is 1, there is little data variation of the address electrode, pulse switching is small, and power consumption increases in proportion to the number of switching, thereby reducing charge / discharge reactive power. The driving waveform at this time is as shown in FIG. As shown in FIG. 4, at full white, only one switching is required for one column indicated by a thick solid line in FIG. 4.

By the way, the dot pattern image data is as follows.

5 is a diagram illustrating dot pattern image data.

Referring to FIG. 5, since data continuously changes from 1 to 0 and 0 to 1, a lot of switching occurs, and the driving waveform at this time is shown in FIG. 6.

As shown in FIG. 6, in the dot pattern, data variation of the address electrode is large, and pulse switching of the driving waveform occurs frequently, thereby increasing power consumption. In addition, not only the dot pattern image data but also the line image data in which the image pattern fluctuates for each line, the data fluctuates for each line, so the number of switching increases and the address power consumption increases.

As in the above process, as the difference between the pixels (cells) of all the lines and the pixels (cells) of the current line in the address data increases, switching occurs more frequently, which increases power consumption.

SUMMARY OF THE INVENTION The present invention has been made in an effort to solve the above-described problems of the related art. The present invention provides a driving apparatus of a plasma display panel and an image processing method of a plasma display panel for controlling address power consumption according to a pattern of input image data. It is to provide.

A driving apparatus of a plasma display panel according to a feature of the present invention for achieving the above object is

An address automatic power control unit which determines whether the image signal data of one frame to be input is data having high address power consumption, and controls to equalize data of a low weight subfield when it is determined that the data has high address power consumption;

An address data generation unit for generating address data to transmit data of an address driving control signal to equalize data of a low weight subfield when the address automatic power controller determines that the address power consumption is high; And

And an address driver for applying address data to an address electrode of a cell to be displayed in response to an address driving control signal transmitted from the address data generator.

In this case, the address automatic power control unit may determine whether the address power consumption is high by using a system of adjacent upper and lower lines of the same column among the image signal data of one frame.

The automatic address controller may determine whether the address power consumption is high by using subfield data of adjacent up and down lines of the same column among the image signal data of one frame.

The image processing method of the plasma display panel according to another aspect of the present invention

An image processing method of a plasma display panel in which an image of each frame displayed on a plasma display panel in response to an input video signal is divided into a plurality of subfields, and a gray level is displayed by combining luminance weights of the plurality of subfields.

(a) determining whether image data of one frame to be input is data having high address power consumption;

(b) generating and transmitting a control signal to make the data of the subfield having the low weight equal to the data having the high address power consumption in step (a);

(c) generating address data corresponding to the control signal of step (b) and transmitting an address driving control signal;

(d) applying address data to address electrodes of cells to be displayed in correspondence with the address driving control signal of step (d).

Plasma display panel according to another aspect of the present invention

A plasma panel including first and second electrodes formed on a first substrate, and a third electrode intersecting the first and second electrodes and formed on a second substrate;

It is determined whether the video signal data of one frame to be input is data having high address power consumption, and when it is determined that the data has high address power consumption, address data is generated to equalize data of a low weight subfield, and A control unit measuring load ratio and outputting sustain discharge pulse information corresponding to the measured load ratio;

An address driver which applies a voltage corresponding to the address data output from the controller to a third electrode of the plasma panel;

And a sustain / scan driver for generating sustain pulses and scan pulses corresponding to sustain discharge pulse information output from the controller, and applying the sustain pulses and scan pulses to the first and second electrodes of the plasma panel.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification.

A driving apparatus of a plasma display panel and an image processing method of the plasma display panel according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

7 is a schematic plan view of a plasma display panel according to an embodiment of the present invention.

As shown in FIG. 7, the plasma display panel according to the exemplary embodiment of the present invention includes a plasma panel 100, an address driver 200, a scan / hold driver 300, and a controller 400.

The plasma panel 100 includes a plurality of address electrodes A1-Am arranged in the column direction, and a plurality of scan electrodes Y1-Yn and sustain electrodes X1-Xn arranged in a zigzag pattern in the row direction. . The address driver 200 receives an address drive control signal from the controller 400 and applies a display data signal for selecting a discharge cell to be displayed to each address electrode A1-Am. The scan / hold driver 300 receives a control signal from the controller 400 and alternately inputs a sustain voltage to the scan electrodes Y1-Yn and the sustain electrodes X1-Xn to perform sustain discharge for the selected discharge cell. .

The control unit 400 receives R, G, B image signals and a synchronization signal from the outside, divides one frame into several subfields, and divides each subfield into a reset period, an address period, and a sustain discharge period (sustain period). Drive the display panel. At this time, the controller 400 adjusts the number of sustain pulses in each sustain period of the subfield in one frame and supplies the necessary control signals to the address driver 200 and the scan sustain driver 300.

Hereinafter, the controller 400 according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 8 to 11.

8 is a schematic block diagram of a controller of a plasma display panel for reducing address power consumption according to an embodiment of the present invention.

As shown in FIG. 8, the control unit 400 of the plasma display panel according to an exemplary embodiment of the present invention includes an inverse gamma correction unit 410, an error diffusion unit 420, an APC unit 430, and a sustain number generator 440. ), A sustain / scan drive control unit 450, an address APC unit 460, and an address data generation unit 470. In this case, the control unit of the plasma display panel is included in the driving device of the plasma display panel for driving the plasma display panel.

The inverse gamma correction unit 410 maps n-bit R, G, and B image input data, which is currently input image data, to an inverse gamma curve and corrects the m-bit (m≥n) image signal. In a typical plasma display panel, n is 8 and m is 10 or 12.

In this case, the image signal input to the inverse gamma correction unit 410 is a digital signal. When an analog image signal is input to the plasma display panel, the analog image signal may be converted into a digital image signal by an analog-to-digital converter (not shown). There is a need. The inverse gamma correction unit 410 may be a logic circuit for generating a lookup table (not shown) or data corresponding to an inverse gamma curve that stores data corresponding to an inverse gamma curve for mapping an image signal. (Not shown).

The error diffusion unit 420 is inversely gamma corrected by the inverse gamma correction unit 410 and error-diffuses the lower m-n bit image of the extended bit m image to surrounding pixels. Error diffusion is a method of displaying an image of a lower bit by separating an image of a lower bit to be diffused into adjacent pixels and a detailed description thereof is described in Korean Patent Laid-Open Publication No. 2002-0014766.

The APC unit 430 detects the load ratio using the image data output from the error diffusion unit 420, calculates the APC level according to the detected load ratio, calculates the number of sustain pulses corresponding to the calculated APC level, and the like. Output

The sustain number generator 440 allocates the number of sustain pulses of each subfield by using the sustain pulse number information transmitted from the APC unit 330.

The sustain / scan drive control unit 450 generates a control signal corresponding to the number of sustain (sustain) discharge pulses output from the sustain number generator 440 and outputs the control signal to the sustain / scan driver 300. In this case, although the sustain number generator 460 and the sustain and scan drive controller 480 have been described separately, the two may be simultaneously implemented in one block.

The address APC unit 460 (that is, the address automatic power control unit) determines whether the data of one frame is data that consumes a lot of address power consumption from the output data of the inverse gamma correction unit 410, and thus the address power consumption is increased. In the case of a large consumption, that is, in the case of the dot pattern as shown in FIG. 5, in order to control the power consumption, both the data gain value for resetting the address data and the address data value of the lowest subfield are turned on or off. A control signal (address APC flag) is outputted to the address data generation unit 470. At this time, the address APC unit 460 even determines whether the data of one frame consumes a lot of address power or data (refers to the difference between the gray level of the previous cell and the gray level of adjacent cells in the column direction in the address electrodes of the same column). Can be determined based on whether or not each subfield data is on / off (the difference between the subfield data of the previous cell and the subfield data of the adjacent cell in the column direction at the address electrodes of the same column). Find out.

9 is a block diagram showing an internal configuration of the address APC unit 460 according to the first embodiment of the present invention.

As shown in Fig. 9, the address APC section 460 according to the first embodiment of the present invention includes a line memory section 461, a sum sum section 462, a gain storage section 463, and a gain determination section 464. And a mode determination unit 465.

Even the sum of the address APC unit 460 adder 462 obtains even the system by comparing the gray level value of the previous line stored in the line memory unit 461 with the gray level value of the currently input line in the same column direction. Add up. That is, the sum of even the system of each line in one frame is obtained by the following equation (1).

Here, P denotes a gray scale value of a pixel, i denotes a line, j denotes a column, and Equation 1 denotes even a system of pixels between each line of image data having N lines and M columns. Represents the sum. Equation 1 may be modified in various ways, may be modified to calculate in a line unit, or may be modified to obtain a sum of all at once.

 Even the sum adding unit 462 obtains the sum of the even system between the lines in the same manner as in Equation 1 above, and outputs the sum to the gain determining unit 464.

Then, the gain determination unit 464 determines an automatic power control (APC) level corresponding to the sum S of the system, and refers to the end gain corresponding to the APC level by referring to the lookup table of the gain storage unit 463. Determine and output At this time, the value corresponding to the APC level is shown in FIG. 10, but this is not exemplary and it is apparent to those skilled in the art that the value may be changed.

Here, the gain value is inversely proportional to the sum of the gradation differences (Sum), and is between 0 and 1. A large sum of the differences means a large difference in data (gradation) between pixels, which increases power consumption, so the data difference between pixels should be reduced by multiplying the gain value.

If the sum Sum of the differences is zero, the gain value is 1, and as the sum Sum of the differences increases, the gain value becomes smaller. This gain value can be set through experimentation and stored in the form of lookup table. Such a gain value may be changed in a range that does not deform the original video signal as needed, and may be designed to be one or more.

On the other hand, the mode determining unit 465 uses the sum of the values of the lines between the lines obtained by the adder 462 to equalize the data values of the least significant bits of the address data. It is determined whether to output the address APC flag signal. In this case, the LSB data value refers to the data value of the subfield having the lowest weight only when the input video signal is converted into the address data. That is, when the sum of gray level differences between the lines is greater than or equal to the threshold value, it is determined that the address power consumption is consumed a lot, and the address APC flag signal is output. It is determined that the address APC flag signal is not output. At this time, the threshold value stores the sum value even in the case where a large amount of address power consumption is generated based on experimental data. Here, even the value between the lines is determined to be equal to or greater than the threshold value, so that the mode determining unit 465 makes the LSB data value of the address data the same (on or off at the same time). In the case of outputting the LB bit, the data value of the LSB bit is equally set at the rear end. Therefore, when the LSB bit is displayed on the plasma panel, the switching is reduced, thereby reducing the power consumption.

The address data generator 470 outputs correction data by multiplying the image signal by the data gain value output from the address APC unit 460, generates subfield data corresponding to the correction data, and displays the subfield data in a plasma display. By rearranging the address data to drive the panel, an address control signal for controlling the address driver 200 is generated and output to the address driver 200.

At this time, when the address APC flag signal is input from the mode determining unit 465 of the address data generating unit 460, the corrected data is recalibrated so that the LSB bits are the same (that is, the same is turned on or off). After generating the subfield data or generating the data corrected by the product of the gain values as the subfield data, the data of the lowest subfield corresponding to the LSB bit is the same (that is, the same on or off). do.

Thus, address power consumption can be further reduced by multiplying the gain value and simultaneously controlling the address power consumption by simultaneously turning on / off the LSB bit.

In this case, in general, even a lot of line-based systems consume a lot of power, and as in the first embodiment of the present invention, the address APC unit 460 consumes a lot of address power by even a line-based system. Although it is determined whether the data is data, the address power consumption is not an accurate determination because it is directly related to the address data, that is, the subfield data. Therefore, a method of determining whether the address power consumption is large or small through the subfield data will be described below.

11 is a block diagram showing an internal configuration of the address APC unit 460 according to the second embodiment of the present invention.

As shown in Fig. 11, the address APC section 460 according to the second embodiment of the present invention includes a line memory section 461, a subfield data difference summing section 466, a gain storage section 463, and a gain determining section 464. ) And a mode determination unit 465. In this case, the address APC unit 460 according to the second embodiment of the present invention includes the subfield data difference adding unit 466 instead of the adding unit 462 even in the first embodiment. Since it is substantially the same as the first embodiment, description of overlapping portions will be omitted below.

The subfield data difference adding unit 466 uses the signal converted into on / off data for each subfield, that is, the vertical lines adjacent to each other in the column direction using the data converted into subfield data (that is, the row line). The difference between the subfield data). At this time, it is preferable that a data processing unit (not shown in Fig. 10) is located at the front end of the subfield data difference adding unit 466. That is, the data processor converts the input video signal into on / off data for each subfield. In order to express 256 gray scales in a plasma display panel, one frame is divided into eight subfields (1SF to 8SF) having a weight of 1, 2, 4, 8, 16, 32, 64, and 128, respectively. Assuming that the data processing unit 410 converts the image signal of gradation 100 into 8-bit data of "00100110", for example. In the "00100110", the numbers '0' and '1' correspond to eight subfields (1SF to 8SF) in sequence, and '0' indicates that the discharge cells (dots) do not discharge (off) in the corresponding subfields. '1' indicates that the discharge cell discharges (on) in the corresponding subfield.

The subfield data difference adding unit 466 sums the difference between subfield data values of adjacent up and down lines (meaning a row line) from the image signal converted by the day processing unit 410 into on / off data for each subfield, The values for each summed subfield are summed for all subfields in one frame. The change in the switching state that generates a large amount of address power consumption occurs when one of the two discharge cells adjacent to each other in the column direction (vertical direction in FIG. 3) is on and the other discharge cell is off, so the subfield data difference is summed. The unit 466 may calculate a sum of the difference between the on / off data of two discharge cells adjacent in the column direction as a subfield, as shown in Equation (2).

Here, R _ij , G _ij , and B _ij are on / off data of R (red), G (green), and B (blue) discharge cells of i rows and j columns, respectively. At this time, the subfield data difference adding unit 466 obtains the value of each subfield by using Equation 2, and adds the values of each subfield to all subfields forming one frame. In this case, Equation 2 represents the sum of the subfield data differences for each subfield. As shown in Equation 2, the sum of the subfield data differences for each subfield may be used to determine whether the address power consumption is large or small. The sum of the values obtained as shown in Equation 2 for the subfield may determine whether the address consumption power is large or small.

In general, since the image signals are serially inputted in a row order, a line memory 461 is included as shown in FIG. 11 to store one row of image signals in order to calculate a difference between on / off data of two adjacent discharge cells. When on / off data for each subfield of a row (line) video signal is input through the line memory unit 461, the subfield data difference adder 466 stores the data sequentially. The difference of on / off data is calculated for each subfield in two adjacent discharge cells by reading the data of the previous row (line) stored in. In addition, the address power consumption determiner 420 may calculate a difference between on / off data for each subfield in two discharge cells by using an exclusive OR (XOR) operation of the on / off data.

The gain determination unit 464 then determines an automatic power control (APC) level (step) corresponding to the sum of the on / off differences between the lines of the mode subfield (or each subfield) of one frame, and the APC level. The end gain corresponding to is determined and output by referring to the lookup table of the gain storage unit 463 as in the first embodiment of the present invention.

If the value determined by the subfield data difference adding unit 466 is greater than or equal to the threshold value, the mode determining unit 465 generates an address APC flag signal and outputs the address APC flag signal. It is determined that the address power consumption is low, and no address APC flag signal is generated. At this time, the threshold value is obtained by storing the value corresponding to the sum of the subfield data difference between the lines in the case where a lot of address power consumption occurs based on experimental data. At this time, as described above, as shown in Equation 2, the mode determining unit 465 may determine whether the address APC flag signal is generated through the sum of the on / off difference of the subfield data for each subfield.

The address data generator 470 outputs correction data by multiplying the image signal by the data gain value output from the address APC unit 460, generates subfield data corresponding to the correction data, and displays the subfield data in a plasma display. By rearranging the address data to drive the panel, an address control signal for controlling the address driver 200 is generated and output to the address driver 200. At this time, when the address APC flag signal is input from the mode determining unit 465 of the address data generating unit 460, the corrected data is recalibrated so that the LSB bits are the same (that is, the same is turned on or off). When the field data is generated or the correction data is generated as the subfield data, the data of the subfield having the lowest weight corresponding to the LSB bit is the same (that is, the same is turned on or off).

In this case, the address APC unit 460 may include a data processor (not shown in FIG. 11) for converting the input image signal into subfield data. Using the generated subfield data, the sum of subfield data differences may be obtained as shown in Equation 2.

Here, although the address APC unit 460 according to the first and second embodiments of the present invention shown in FIGS. 9 and 11 is shown in a different block from the address data generating unit 460, it is included in the same block and implemented as one block. It will be apparent to one skilled in the art.

In this case, in the first and second embodiments of the present invention, the value of the input image signal data is changed using the gain determiner 464, but only the mode determiner 465 is excluded except the gain determiner 464. The power consumption can be reduced by controlling the LSB bits to be the same.

In addition, the address APC unit 460 according to the first and second embodiments may determine whether power consumption is large or small as described above using the output data of the inverse gamma correction unit 410, but the error diffusion unit ( Using the output signal of 420, it is possible to determine the magnitude of power consumption.

In addition, when the mode determining unit 465 determines that the power consumption is high as in the first and second embodiments of the present invention, the address data generator 470 uses the LSB bit (ie, the lowest weight subfield). Although only the data) is the same, the lower few bits can be made the same so as not to affect the gradation.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, the presence or absence of address power consumption is determined by using the difference between the line-based systems or the line-by-line subfield data values, and the data of the subfield having the minimum weight according to the determined power consumption. By controlling to be the same, address power consumption can be improved in a double manner.

1 is a partial perspective view of an AC plasma display panel.

2 is a diagram illustrating an electrode array of a plasma display panel.

3 is a view showing image data at full white.

4 is a switching waveform diagram of FIG. 3.

5 is a diagram illustrating dot pattern image data.

6 is a switching waveform diagram of FIG. 5.

7 is a schematic plan view of a plasma display panel according to an embodiment of the present invention.

8 is a schematic block diagram of a controller of a plasma display panel for reducing address power consumption according to an embodiment of the present invention.

9 is a block diagram showing an internal configuration of an address APC unit according to the first embodiment of the present invention.

FIG. 10 is a diagram illustrating a gain value according to the address APC level of FIG. 9.

11 is a block diagram showing an internal configuration of an address APC unit according to a second embodiment of the present invention.

Claims (14)

An address automatic power control unit which determines whether the image signal data of one frame to be input is data having high address power consumption, and controls to equalize data of a low weight subfield when it is determined that the data has high address power consumption; An address data generation unit for generating address data to transmit data of an address driving control signal to equalize data of a low weight subfield when the address automatic power controller determines that the address power consumption is high; And And an address driver for applying address data to an address electrode of a cell to be displayed in response to an address driving control signal transmitted from the address data generating unit. The method of claim 1, And the address automatic power controller determines whether the address power consumption is high by using a system of adjacent upper and lower lines of the same column among the image signal data of one frame. The method according to claim 1 or 2, The address automatic power control unit A summation unit that sums even the systems of adjacent upper and lower lines of the same column among the image signal data of one frame; A gain determination section for determining an address APC level corresponding to the summation section and outputting a data gain value corresponding to the address APC level even in the system; And a mode determination unit for outputting a signal for controlling the data of the subfield having the lower weight to be equal when the system even added by the adding unit is higher than a threshold value. The method of claim 1, And the address automatic power controller determines whether the address power consumption is high by using subfield data of adjacent upper and lower lines of the same column among the image signal data of one frame.  The method according to claim 1 or 4, The address automatic power control unit A subfield data difference summing unit for adding up subfield data value differences of adjacent upper and lower lines of the same column among video signal data of one frame; A gain determiner which determines an address APC level corresponding to the subfield data difference adder and outputs a data gain value corresponding to the address APC level; And a mode determination unit for outputting a signal for controlling the data of the subfield having the lower weight to be equal when the subfield data value difference summed by the subfield data difference adding unit is higher than a threshold value. The method of claim 1, And the address automatic power controller controls the data of the subfield having the lowest weight to be the same when it is determined that the data having the high address power consumption is the same. The method of claim 5, And the subfield data difference adder adds a value difference of all subfield data with respect to image signal data of one frame. An image processing method of a plasma display panel in which an image of each frame displayed on a plasma display panel in response to an input video signal is divided into a plurality of subfields, and a gray level is displayed by combining luminance weights of the plurality of subfields. (a) determining whether image data of one frame to be input is data having high address power consumption; (b) generating and transmitting a control signal to make the data of the subfield having the low weight equal to the data having the high address power consumption in step (a); (c) generating address data corresponding to the control signal of step (b) and transmitting an address driving control signal; and (d) applying address data to address electrodes of cells to be displayed in correspondence with the address driving control signal of step (d). The method of claim 8, And determining whether or not the address power consumption is high using the system of adjacent upper and lower lines of the same column among the image signal data of one frame in the step (a). The method of claim 8, And determining whether or not the address power consumption is high by using subfield data of adjacent upper and lower lines of the same column among the image signal data of one frame in the step (a). The method according to any one of claims 8 to 10, The subfield data having the low weight in step (b) is the subfield data having the lowest weight. A plasma panel including first and second electrodes formed on a first substrate, and a third electrode intersecting the first and second electrodes and formed on a second substrate; It is determined whether the video signal data of one frame to be input is data having high address power consumption, and when it is determined that the data has high address power consumption, address data is generated to equalize data of a low weight subfield, and A control unit measuring load ratio and outputting sustain discharge pulse information corresponding to the measured load ratio; An address driver which applies a voltage corresponding to the address data output from the controller to a third electrode of the plasma panel; And a sustain / scan driver configured to generate sustain pulses and scan pulses corresponding to sustain discharge pulse information output from the controller, and to apply the sustain pulses and scan pulses to the first and second electrodes of the plasma panel. The method of claim 12, And the control unit determines whether the address power consumption is high by using a system of adjacent upper and lower lines of the same column among image signal data of one frame. The method of claim 12, And the control unit determines whether the address power consumption is high by using subfield data of adjacent upper and lower lines of the same column among the image signal data of one frame.