KR100658625B1 - Plasma display device and method for displaying pictures thereof - Google Patents

Abstract

The present invention relates to a plasma display device for reducing address power consumption and an image processing method thereof.

According to the present invention, according to the present invention, the sum of the sum of even systems between adjacent row lines and the sum of even systems between adjacent column lines or the sum of the subfield data differences between adjacent row lines and the subfield data difference between adjacent column lines The sum is used to determine the APC level, which is large or small in address power consumption, and the video signal data is adjusted according to the determined APC level. Accordingly, address power consumption can be reduced.

Address power consumption, APC, gradation, subfield data

Description

Plasma display device and image processing method {PLASMA DISPLAY DEVICE AND METHOD FOR DISPLAYING PICTURES THEREOF}

1 is a diagram illustrating an electrode arrangement diagram of a plasma display device according to an exemplary embodiment of the present invention.

2 is a schematic plan view of a plasma display device according to an exemplary embodiment of the present invention.

3A is a diagram conceptually illustrating a white dot on / off pattern, and FIG. 3B is a diagram conceptually illustrating an RGB dot on / off pattern.

4 is a block diagram showing the overall configuration of a control unit according to an embodiment of the present invention.

5 is a block diagram showing the configuration of the address APC unit according to the first embodiment of the present invention.

6 is a graph illustrating data gain values according to address APC levels.

7 is a block diagram showing the configuration of the address APC unit according to the second embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display device and an image processing method thereof, and more particularly to a plasma display device for controlling address power consumption and an image processing method thereof.

Recently, flat display devices such as a liquid crystal display (LCD), a field emission display (FED), and a plasma display have been actively developed. Among these flat panel display devices, the plasma display device has advantages of higher luminance and luminous efficiency and a wider viewing angle than other flat panel display devices. Therefore, the plasma display panel is in the spotlight as a display device to replace a conventional cathode ray tube (CRT) in a large display device of 40 inches or more.

In the DC plasma display device, the electrode is exposed without the discharge space insulated, so that the current flows in the discharge space while the voltage is applied, and there is a disadvantage in that a resistance for limiting the current must be made. On the other hand, in the AC plasma display device, since the electrode covers the dielectric layer, the current is limited by the formation of a natural capacitance component, and the electrode is protected from the impact of ions during discharge.

In general, the driving method of the AC plasma display device includes a reset period, an address period, and a sustain period.

The reset period is a period of initializing the state of each cell in order to smoothly perform an addressing operation on the cell, and the address period is an address for a cell (addressed cell) that is turned on to select a cell that is turned on and a cell that is not turned on. This is a period of time in which wall charges are accumulated by applying a voltage. The sustain period is a period in which a discharge for actually displaying an image in the addressed cells by applying a sustain discharge pulse is performed.

Here, when each operation of each subfield is performed in the above manner, the discharge space between the scan electrode and the sustain electrode, the surface on which the address electrode is formed and the surface on which the scan and sustain electrode are formed act as a capacitive load. There is capacitance in the panel. Therefore, when an address voltage is applied to select a cell to be turned on in an address period, in addition to the power for address discharge, a lot of reactive power for charge injection that generates a predetermined voltage in capacitance is required. In particular, in the case where the input gray level is a white dot on / off pattern and an RGB dot on / off pattern, the address power consumption increases further by repeating the switching operation of the address driving circuit.

SUMMARY OF THE INVENTION The present invention has been made in an effort to solve the above-described problems of the related art, and to provide a plasma display device and an image processing method thereof for controlling address power consumption.

An image processing method of a plasma display device according to a feature of the present invention for achieving the above object

An image processing method of a plasma display device which divides a plurality of subfields corresponding to an input video signal of one frame and displays gray levels by combining the weights of the plurality of subfields. Calculating, from the signal data, first data that is the sum of the grayscale data differences between adjacent row lines and second data that is the sum of the grayscale data differences between adjacent column lines; (b) resetting the video signal data corresponding to the first data and the second data calculated in the step (a); And (c) displaying the image signal data reset in the step (b) on the plasma display.

The image processing method of the plasma display device according to another aspect of the present invention

An image processing method of a plasma display device which divides a plurality of subfields corresponding to an input video signal of one frame and displays gray levels by combining the weights of the plurality of subfields. In signal data, a second sum of the sum of subfield data differences between adjacent row lines for the plurality of subfields and the sum of subfield data differences between adjacent column lines for the plurality of subfields. Calculating data; (b) resetting the video signal data corresponding to the first data and the second data calculated in the step (a); And (c) displaying the image signal data reset in the step (b) on the plasma display.

Plasma display device according to another aspect of the present invention,

A plasma panel including a plurality of first and second electrodes and a plurality of third electrodes crossing the first and electrodes; The second data, which is the sum of the data difference between adjacent column lines and the first data, which is the sum of the data differences between adjacent row lines, is calculated based on the input image signal data of one frame, and corresponding to the first data and the second data. A controller configured to reset image signal data and to generate and output a control signal to apply the reset image signal data to the plasma panel; An address driver configured to drive the third electrode in response to a control signal generated from the controller; And

And a holding and scanning driver for driving the first and second electrodes in response to a control signal generated from the controller. Here, the first data is the sum of gray data differences between adjacent row lines, and the second data is the sum of gray data differences between adjacent column lines. The first data is a sum of subfield data differences between adjacent row lines, and the second data is a sum of differences of subfield data between adjacent column lines.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification.

A plasma display device and an image processing method thereof according to an embodiment of the present invention will now be described in detail with reference to the drawings.

1 is a diagram illustrating an electrode arrangement diagram of a plasma display device according to an exemplary embodiment of the present invention.

As shown in FIG. 1, the electrodes of the plasma display device are arranged in a matrix of m × n. Specifically, the address electrodes A1-Am are arranged in the column direction and n rows of scan electrodes in the row direction ( Y1-Yn and sustain electrodes X1-Xn are arranged in a zigzag. In FIG. 1, a portion where the scan electrode, the sustain electrode, and the address electrode intersect forms one discharge cell 12.

2 is a schematic plan view of a plasma display device according to an exemplary embodiment of the present invention.

As shown in FIG. 2, the plasma display device according to the exemplary embodiment of the present invention includes a plasma panel 100, an address driver 200, a scan / hold driver 300, and a controller 400.

The plasma panel 100 includes a plurality of address electrodes A1-Am arranged in the column direction, and a plurality of scan electrodes Y1-Yn and sustain electrodes X1-Xn arranged alternately in the row direction. .

The address driver 200 receives an address drive control signal from the controller 400 and applies a display data signal for selecting a discharge cell to be displayed to each address electrode A1-Am.

The scan / hold driver 300 receives a control signal from the controller 400 and alternately inputs a sustain discharge pulse to the scan electrodes Y1-Yn and the sustain electrodes X1-Xn to sustain discharge for the selected discharge cell. Do this.

The controller 400 receives R, G, and B image signals and a synchronization signal from the outside, divides one frame into several subfields, and divides each subfield into a reset period, an address period, and a sustain discharge period. A control signal for driving is generated and supplied to the address driver 200 and the scan and sustain driver 300. Here, the control unit 400 according to an embodiment of the present invention determines the input image pattern to reduce the address power consumption to convert the image data to reduce the address power consumption will be described in detail below.

First, referring to FIGS. 3A and 3B, an image pattern that consumes a lot of address power will be described. 3A is a diagram conceptually illustrating a white dot on / off pattern, and FIG. 3B is a diagram conceptually illustrating an RGB dot on / off pattern. 3A and 3B, '1' indicates a case in which the corresponding pixel is turned on and '0' indicates a case in which the corresponding pixel is turned off. The row lines correspond to the lines of the scan electrodes Y1-Yn or the lines of the sustain electrodes X1-Xn, and the column lines correspond to the lines of the address electrodes A1-Am.

As shown in FIG. 3A, when the pixel data in the row direction (row line, used in the same sense) is the same, but the pixel data in the column direction (column line, used in the same meaning below) is repeatedly changed, an address driver which applies address data. The number of times of switching is increased in the driving circuit of C, which consumes a lot of address power. That is, as shown in FIG. 3A, the address data of the R1 column is 1, 0, 1, 0, 1, 0, 1. The driving circuit of the address region repeatedly applies and disapplies the address voltage Va, thereby increasing the number of switching. do. This consumes a lot of address power.

Next, as shown in FIG. 3B, when not only the pixel data in the column direction changes but also the pixel data in the row direction changes repeatedly, a lot of address power consumption is further consumed. In general, when pixel data in a column direction changes, address power consumption increases due to an increase in the number of switching.However, even when pixel data in a row direction changes, reactive power is consumed due to capacitance components between adjacent address electrodes. This increases. That is, as shown in FIG. 3B, when address data changes to 1, 0, 1, 0, 1, 0, 1, and 0 as the first row line, the power consumption of the address is increased due to the capacitance component between adjacent address electrodes. Increases.

In the embodiment of the present invention, in determining the degree of power consumption of the address, it is determined in consideration of the case where the data changes in the row direction and the case where the data changes in the column direction as shown in FIGS. 3A and 3B.

Hereinafter, the controller 400 according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 4 to 7. 4 is a block diagram showing an overall configuration of a control unit according to an embodiment of the present invention, FIG. 5 is a block diagram showing a configuration of an address APC unit according to a first embodiment of the present invention, and FIG. 7 is a graph showing a data gain value, and FIG. 7 is a block diagram showing the configuration of the address APC unit according to the second embodiment of the present invention.

As shown in FIG. 4, the control unit 400 according to the present embodiment is an inverse gamma correction unit 410, an error diffusion unit 420, and an automatic power controller 430 (hereinafter referred to as an “APC unit”). And a sustain number generator 440, a scan / sustain drive controller 450, an address APC unit 460, and an address data generator 470.

The inverse gamma correction unit 410 maps n-bit R, G, and B image input data, which is currently input image data, to an inverse gamma curve and corrects the m-bit (m≥n) image signal. In a typical plasma display device, n is 8 and m is 10 or 12.

In this case, the video signal input to the inverse gamma correction unit 410 is a digital signal. When an analog video signal is input to the plasma display device, the analog video signal may be converted into a digital video signal by an analog-to-digital converter (not shown). There is a need. The inverse gamma correction unit 410 may be a logic circuit for generating a lookup table (not shown) or data corresponding to an inverse gamma curve that stores data corresponding to an inverse gamma curve for mapping an image signal. (Not shown).

The error diffusion unit 420 is inversely gamma corrected by the inverse gamma correction unit 410 and error-diffuses the lower m-n bit image of the extended bit m image to surrounding pixels. Error diffusion is a method of displaying an image of a lower bit by separating an image of a lower bit to be diffused into an adjacent pixel.

The APC unit 430 detects a load rate using the image data output from the error diffusion unit 420, calculates an APC level according to the detected load rate, and applies sustain of one frame corresponding to the calculated APC level. The number of pulses is calculated and output.

The sustain number generator 440 allocates the number of sustain pulses to be applied to each subfield by using the sustain number information transmitted from the APC unit 330.

The scan and sustain drive control unit 450 generates a control signal corresponding to the number of sustain pulses output from the sustain number generator 440 and outputs the control signal to the scan and sustain drive unit 300. In this case, although the sustain number generator 440 and the scan and sustain drive controller 450 have been described separately, the two may be simultaneously implemented in one block.

The address APC unit 460 determines from the output data of the inverse gamma correction unit 410 whether the data of one frame is data that consumes a lot of address power, and thus consumes a lot of address power. In the case of the image pattern shown in FIG. 3B, in order to control power consumption, a data gain value for resetting address data is set and output to the address data generator 470. In this case, in determining whether the image data inputted by the address APC unit 460 consumes a lot of address power consumption, the address APC unit 460 considers not only the data change in the column direction but also the data change in the row direction. Also, whether the data of one frame is an image pattern that consumes a lot of address power consumption is determined through the system (even in the column direction and even in the row direction) or whether the corresponding pixel is turned on or off in each subfield. The determination may be made based on the determined subfield data difference (the subfield data difference in the column direction and the subfield data difference in the row direction).

As shown in FIG. 5, the address APC unit 460 according to the first embodiment of the present invention includes an adder 461 even in the column direction system, an adder 462 in the row direction system, and line memory units 463 and 464. And a gain determiner 465 and a gain store 466.

Even the column direction adding unit 461 is stored in the line memory unit 463 to compare the gray level values of adjacent row lines in the column direction by using the gray level data to obtain even the column direction system and sum them. That is, the sum S _{C of} even the column system between adjacent row lines in one frame is obtained by Equation 1 below.

Here, P denotes a gray scale value of each of R, G, and B pixels, and i and j denote row lines and column lines, respectively. N denotes the number of row lines, and M denotes the number of column lines (all of the address electrode lines of the R, G, and B pixels are considered). Equation 1 may be modified in various ways, may be modified to calculate in a row line unit, or may be modified to obtain a sum of all at once.

Even the row direction summing unit 461 uses the gradation data stored in the line memory unit 464 to compare the gradation values between adjacent column lines in the row direction to obtain even the row direction system and sum them. That is, the sum S _{R of} even the row system between adjacent column lines in one frame is obtained by Equation 2 below.

P, i, j in the equation (2) is the same as the symbol in the equation (1). That is, as shown in Equation 2, the sum S _{R of} even row systems may be obtained through the sum of even systems between adjacent row lines of the same column line. In addition, Equation 2 may be modified in various ways, may be modified to calculate in units of line lines, or may be modified to obtain a sum of all at once.

On the other hand, the sum Sc of even the column system calculated in the adding unit 461 and the row system calculated in the adding unit 462 even the column direction system S _R are the gain determining units. 465 is sent.

Then, the gain determiner 465 determines an automatic power control (APC) level corresponding to the sum Sc of even the column system and the sum S _R of the row system, and starts the start corresponding to the determined APC level. The gain and the end gain are output with reference to the lookup table of the gain storage unit 466. Here, the gain determiner 465 determines a higher APC level when there are many systems in determining the APC level corresponding to the sum of the column system and the sum of the row system. On the other hand, in general, since the address power consumption occupies even more of the column system, the APC level can be set to the lowest level when the sum of the column system is '0' and the sum of the row system is large.

The start gain and end gain corresponding to the APC level have a decreasing value as the APC level increases as shown in FIG. 6. The start gain corresponding to each APC level has a higher value than the end gain. The large sum of even column and even row systems is a case where the address power is consumed a lot, and thus the address power consumption is reduced by multiplying the low start gain and the end gain to reduce the even system between the column and row directions. The gain value shown in FIG. 6 is an example, and a gain value corresponding to the APC level may be set through an experiment and stored in the gain storage unit 466 in the form of a lookup table.

The address data generator 470 multiplies the data gain values (start gain and ed gain) output from the address APC unit 460 by the image signal output from the error diffusion unit 420 to output correction data. Subfield data corresponding to the subfield data is generated, the subfield data is rearranged into address data for driving the plasma display device, and an address control signal for controlling the address driver 200 is generated and output to the address driver 200. Here, when the address data generator 470 multiplies the data gain value by the image signal, the start gain is first multiplied. After a predetermined time, the address data generator 470 gradually multiplies the gain value lower than the start gain to finally multiply the AND gain value. That is, first, the correction data is output by multiplying the start gain, and the correction data is output by gradually multiplying the gain lower than the start gain, and finally, the end gain value is output to output the correction data. This corrected data can reduce the power consumption of the address by gradually reducing the system in the row and column directions.

In general, even a lot of line-based systems consume a lot of power, so as in the first embodiment of the present invention, the address APC unit 460 consumes a lot of address power by even row- and column-oriented systems. It is determined whether or not the address power consumption is correct, since the address power consumption is directly related to the address data, that is, the subfield data. Therefore, a method of determining whether the address power consumption is large or less through the subfield data will be described below with reference to FIG. 7.

 As shown in Fig. 7, the address APC section 460 according to the second embodiment of the present invention includes a column direction subfield data difference adder 461 ', a row direction subfield data difference adder 462', and a line memory. Section 463 'and 464', gain determining section 465 'and gain storing section 466'. The address APC unit 460 according to the second embodiment is the same as the first embodiment except that the APC level is determined using the subfield data, unlike the first embodiment. do.

First, although not shown in FIG. 7, it is preferable that a data processing unit (not shown in FIG. 7) be positioned in front of the column direction subfield data difference adding unit 461 and the row direction subfield data difference adding unit 462 ′. Do. That is, the data processor converts the input video signal into on / off data for each subfield. In order to express 256 gray scales in a plasma display panel, one frame is divided into eight subfields (1SF to 8SF) having a weight of 1, 2, 4, 8, 16, 32, 64, and 128, respectively. Assuming that the data processing unit converts the image signal of gradation 100 into 8-bit data of " 00100110 ", for example. In the "00100110", the numbers '0' and '1' correspond to eight subfields (1SF to 8SF) in sequence, and '0' indicates that the discharge cells (dots) do not discharge (off) in the corresponding subfields. '1' indicates that the discharge cell discharges (on) in the corresponding subfield.

The column subfield data difference adder 461 ′ converts the input image signal into on / off data of each pixel for each subfield (which is stored in the line memory unit 463 '), that is, the subfield data. The subfield data between adjacent row lines (rows i + 1 and i) are compared in the column direction using the data, and the sum of column direction subfield data differences is calculated for each subfield, and then summed for all subfields in one frame. . The sum Pc of the column subfield data differences in each subfield may be calculated by Equation 3 below.

In Equation 3, SD represents data of a subfield, and the meanings of i, j, N, and M are the same as in Equation 1 above. Since Equation 3 represents the column subfield data difference of any one subfield, the column subfield data difference adder 461 ′ sets the value Pc of each subfield to all subfields forming one frame. Summing up.

The row direction subfield data difference adder 462 'converts the input video signal into on / off data of each pixel for each subfield (which is pre-stored in the line memory section 464'), that is, subfield data. The difference between the subfield data between adjacent column lines (j + 1 column and j column) is obtained for each subfield using the obtained data, and then summed for all subfields of one frame. The sum P _R of the row direction subfield data differences in each subfield may be calculated by Equation 4 below.

In Equation 3, SD represents data of a subfield, and the meanings of i, j, N, and M are the same as in Equation 1 above. Since Equation 4 represents the sum of the row direction subfield data differences of any one subfield, the row direction subfield data difference adding unit 462 'includes all the subs that form the value P _R of each subfield in one frame. Sum for the fields.

The gain determiner 465 'is a sum of the column subfield data difference transmitted from the column subfield data difference adder 461' and the row direction subfield transmitted from the row direction subfield data difference adder 462 '. The automatic power control (APC) level is determined in response to the sum of the field data differences, and the start gain and end gain corresponding to the determined APC level are determined by looking up the lookup table of the gain storage unit 466 '. Output by referring. Here, the gain determining unit 465 ′ determines a higher APC level when there are many systems in determining the APC level corresponding to the sum of the column-based system and the sum of the row-based system.

The method of determining the start gain and the end gain corresponding to the APC level determined by the gain determiner 465 'and the method of generating the correction data by the address data generator 470 according to the first embodiment described above are described. The same description as in the following will be omitted.

In this case, the address APC unit 460 may include a data processing unit (not shown in FIG. 7) for converting the input image signal into subfield data by itself. Using the generated subfield data, the sum of column direction subfield data and the sum of row direction subfield data can be obtained as shown in Equations 3 and 4 below.

Here, although the address APC unit 460 according to the first and second embodiments of the present invention shown in Figs. 5 and 7 is shown in a different block from the address data generator 470, it is included in the same block to be implemented as one. It will be apparent to one skilled in the art.

In addition, although the address APC unit 460 according to the first and second embodiments may determine whether power consumption is large or small as described above, using the output data of the inverse gamma correction unit 410, the error diffusion unit 420 may be used. ) Can be used to determine the magnitude of power consumption.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, the sum of the sum of even systems between adjacent row lines and the sum of even systems between adjacent column lines or the sum of the subfield data difference between adjacent row lines and the subfield data between adjacent column lines. The sum of the differences can be used to determine the APC level, which is large or small in the address power consumption, and adjust the image signal data according to the determined APC level, thereby reducing the address power consumption.

Claims (11)

In the image processing method of the plasma display apparatus which divides into a plurality of subfields corresponding to an input video signal of one frame, and displays gray levels by combining the weights of the plurality of subfields. (a) calculating second data which is the sum of the first data which is the sum of the grayscale data differences between the adjacent row lines and the grayscale data difference between the adjacent column lines, from the image signal data of one frame input; (b) setting a gain corresponding to the first data and the second data; resetting the video signal data by multiplying the video signal data by the gain; And (d) displaying the image signal data reset in the step (c) on the plasma display, And the gain is set to a lower value when the first data and the second data are high values. delete delete  The method of claim 1, The gain includes a first gain and a second gain lower than the first gain, and decreases the gain little by little from the first gain to the second gain to multiply the image signal data to reset the image signal data. Image processing method. In the image processing method of the plasma display apparatus which divides into a plurality of subfields corresponding to an input video signal of one frame, and displays gray levels by combining the weights of the plurality of subfields. (a) In the video signal data of one frame input, the sum of the difference of subfield data between adjacent row lines and the sum of the subfield data difference between adjacent column lines and the first data obtained for the plurality of subfields. Calculating second data summed over the plurality of subfields; (b) setting gains corresponding to the first data and the second data calculated in step (a); resetting the video signal data by multiplying the video signal data by the gain; And (d) displaying the image signal data reset in the step (c) on the plasma display, And the gain is set to a lower value when the first data and the second data are high values.  The method of claim 5, And generating subfield data corresponding to the image signal data of the one frame inputted before the step (a). delete The method according to claim 5 or 6, The gain includes a first gain and a second gain lower than the first gain, and decreases the gain little by little from the first gain to the second gain to multiply the image signal data to reset the image signal data. Image processing method A plasma panel including a plurality of first and second electrodes and a plurality of third electrodes crossing the first and electrodes; The second data, which is the sum of the data difference between adjacent column lines and the first data, which is the sum of the data differences between adjacent row lines, is calculated based on the input image signal data of one frame, and corresponds to the first data and the second data. A controller configured to set a gain, multiply the image signal data by the gain, reset the image signal data, and generate and output a control signal to apply the reset image signal data to the plasma panel; An address driver configured to drive the third electrode in response to a control signal generated from the controller; And A holding and scanning driver for driving the first and second electrodes in response to a control signal generated from the controller, And the gain is set to a lower value when the first data and the second data are high values. The method of claim 9, Wherein the first data is a sum of gray scale data differences between adjacent row lines, and the second data is a sum of gray scale data differences between adjacent column lines. The method of claim 9, Wherein the first data is a sum of subfield data differences between adjacent row lines, and the second data is a sum of differences of subfield data between adjacent column lines.

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