JP4662680B2 - 埋め込みビット線および上昇されたソース線を持つ浮遊ゲート・メモリセルの半導体メモリ配列を形成するセルフアライメント方法及びその方法により製造されたメモリ配列 - Google Patents

埋め込みビット線および上昇されたソース線を持つ浮遊ゲート・メモリセルの半導体メモリ配列を形成するセルフアライメント方法及びその方法により製造されたメモリ配列 Download PDF

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JP4662680B2
JP4662680B2 JP2002291067A JP2002291067A JP4662680B2 JP 4662680 B2 JP4662680 B2 JP 4662680B2 JP 2002291067 A JP2002291067 A JP 2002291067A JP 2002291067 A JP2002291067 A JP 2002291067A JP 4662680 B2 JP4662680 B2 JP 4662680B2
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Japan
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region
regions
trench
layer
substrate
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Expired - Lifetime
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JP2002291067A
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Japanese (ja)
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JP2003179170A (ja
Inventor
キアニアン ソーラブ
シン ワン チー
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Silicon Storage Technology Inc
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Silicon Storage Technology Inc
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Priority claimed from US09/982,413 external-priority patent/US6917069B2/en
Priority claimed from US10/105,741 external-priority patent/US6952033B2/en
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Publication of JP2003179170A publication Critical patent/JP2003179170A/ja
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Publication of JP4662680B2 publication Critical patent/JP4662680B2/ja
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
JP2002291067A 2001-10-17 2002-10-03 埋め込みビット線および上昇されたソース線を持つ浮遊ゲート・メモリセルの半導体メモリ配列を形成するセルフアライメント方法及びその方法により製造されたメモリ配列 Expired - Lifetime JP4662680B2 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US09/982,413 US6917069B2 (en) 2001-10-17 2001-10-17 Semiconductor memory array of floating gate memory cells with buried bit-line and vertical word line transistor
US09/982413 2001-10-17
US10/105,741 US6952033B2 (en) 2002-03-20 2002-03-20 Semiconductor memory array of floating gate memory cells with buried bit-line and raised source line
US10/105741 2002-03-20

Publications (2)

Publication Number Publication Date
JP2003179170A JP2003179170A (ja) 2003-06-27
JP4662680B2 true JP4662680B2 (ja) 2011-03-30

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JP2002291067A Expired - Lifetime JP4662680B2 (ja) 2001-10-17 2002-10-03 埋め込みビット線および上昇されたソース線を持つ浮遊ゲート・メモリセルの半導体メモリ配列を形成するセルフアライメント方法及びその方法により製造されたメモリ配列

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Country Link
JP (1) JP4662680B2 (zh)
KR (1) KR100471015B1 (zh)
CN (1) CN1215565C (zh)
TW (1) TWI223407B (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100591764B1 (ko) 2004-05-18 2006-06-22 삼성전자주식회사 셀 어레이를 가로질러 배선된 신호라인을 갖는 반도체메모리 장치
CN102956643A (zh) * 2011-08-24 2013-03-06 硅存储技术公司 制造非易失浮栅存储单元的方法和由此制造的存储单元
CN103094087B (zh) * 2011-11-01 2015-08-19 上海华虹宏力半导体制造有限公司 刻蚀沟槽多晶硅栅的方法

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Publication number Publication date
JP2003179170A (ja) 2003-06-27
CN1416175A (zh) 2003-05-07
KR100471015B1 (ko) 2005-02-21
TWI223407B (en) 2004-11-01
KR20030032858A (ko) 2003-04-26
CN1215565C (zh) 2005-08-17

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