JP4640469B2 - Coating and developing apparatus, method and storage medium - Google Patents

Description

  The present invention relates to a coating and developing apparatus, a method and a coating and developing method for performing a resist solution coating process, a developing process after exposure, etc. on a substrate such as a semiconductor wafer or an LCD substrate (glass substrate for liquid crystal display). The present invention relates to a storage medium storing a program for implementing the above.

  In a manufacturing process of a semiconductor device or an LCD substrate, a resist pattern is formed on the substrate by a technique called photolithography. In this technique, for example, a resist solution is applied to a substrate such as a semiconductor wafer (hereinafter referred to as a wafer) to form a liquid film on the surface of the wafer, and the resist film is exposed using a photomask, and then developed. This is performed by a series of steps to obtain a desired pattern.

  Such processing is generally performed using a resist pattern forming apparatus in which an exposure apparatus is connected to a coating / developing apparatus for applying or developing a resist solution. In this apparatus, for example, as shown in FIG. 7, a carrier 10 containing a large number of wafers is carried into a carrier stage 11 of a carrier mounting portion 1A, and the wafer in the carrier 10 is received by a processing portion 1B by a delivery arm 12. Passed. Then, in the processing section 1B, after the formation of the antireflection film in the antireflection film forming module (not shown) and the formation of the resist film in the coating module 13, they are conveyed to the exposure apparatus 1D through the interface section 1C. Is done. On the other hand, the wafer after the exposure processing is returned to the processing section 1B again and subjected to development processing by the development module 14, and then returned to the original carrier 10. Before and after the formation of the antireflection film and the resist film and before and after the development process, the wafer is heated and cooled. The heating module for performing the heating process, the cooling module for performing the cooling process, and the like are the shelf modules 15. (15a to 15c) are arranged in multiple stages, and the wafer is transferred between the modules by the main arm 16 (16A, 16B) provided in the processing section 1B. Here, when the wafer is subjected to the above processing, as described in Patent Document 1, all wafers to be processed are preliminarily determined according to a transfer schedule that determines at which timing each module is transferred to which module. Be transported.

  By the way, in the above-described apparatus, the wafer A of the first lot A and the wafer B of the second lot B, which are a set of a plurality of wafers of the same type discharged from one carrier, are transferred from the carrier mounting unit 1A to the processing unit 1B. In the case where the same heating module is used between lot A and lot B, and the heating temperature of the heating module is changed between lot A and lot B. is there.

  In this case, conventionally, in consideration of the temperature settling time (time required for temperature change) in the heating module, the timing for paying out the carrier placement unit 1A in the subsequent lot B is controlled by a timer. This timer control will be described using the conveyance schedule shown in FIG. 8 as an example. The vertical axis of the transfer schedule indicates the cycle, and the horizontal axis indicates the module to be transferred. Note that FOUP is a carrier, and M1 to M4 are modules. In this example, the temperature settling process is performed in the module M4.

The payout timing control time T1 is obtained by the following equation (2).
T1 = P + Q-R (2)
P: Time until the wafer of the first lot A is unloaded from the module M4 Q: Temperature control time R: Time until the wafer of the second lot B is loaded into the module M4 where P is (in the module M1) (Remaining process time) + (travel time to module M2 + process time in module M2) + (travel time to module M2 + process time in module M2) + (travel time to module M3 + process in module M3) Time) + (movement time to module M4 + process time in module M4), for example, 15 seconds.

  R is (movement time to module M1 + process time in module M1) + (movement time to module M2 + process time in module M2) + (movement time to module M2 + process time in module M2) ) + (Movement time to module M3 + process time in module M3), for example, 20 seconds.

  As a result, the control time T1 becomes P + QR = (15 + 30)-(20) = 25 seconds, and the delivery of the first wafer of the subsequent lot B is delayed by this 25 seconds. However, according to the transfer schedule, the main arm 16 adjusts the cycle time to the latest process time (the time obtained by adding the wafer transfer time to the module M4 and the time required for processing), and this cycle time makes one transfer cycle. Although the number of wafers transferred by the main arm differs depending on the cycle, the cycle may be executed in a shorter or longer time than this cycle time. After the wafer finishes the process in the module M4, the main arm 16 does not immediately carry out the module M4 from the module M4, and there is a case where a waiting state for the reception by the main arm 16 occurs in the module M4. is there. Here, since this waiting time is not included in the above calculation formula, even if the timer control as described above is performed, the wafer B of the subsequent lot B arrives at the module M4 earlier or arrives later. A case occurs.

  When the time for the wafer B of the subsequent lot B to arrive at the module M4 becomes earlier in this way, since the temperature settling process has not been completed in the module M4, the wafer B cannot be delivered to the module. The arm 16 must wait while holding the wafer B, and there is a possibility that the transfer cycle cannot be performed and the arm 16 stops. On the other hand, when the time to arrive at the module M4 is delayed, the module M4 waits for the wafer W to be loaded even though the temperature settling process has already been completed in the module M4 and the process can be performed. This occurs, and the transfer interval between the wafer A of the first lot A and the wafer A of the first lot A becomes longer than necessary, and there is a risk of delaying the supply of the wafer B of the second lot B to the exposure apparatus, leading to a decrease in productivity. Accordingly, if the wafer B of the subsequent lot B arrives at the module M4 earlier or arrives later, the throughput is lowered.

  By the way, in Patent Document 2, the first temperature control module, the first application module, the first heating module, the second temperature control module, the second application module, the second heating module, and the cooling module are arranged in this order. In the apparatus equipped with a retracting module that can retract a plurality of substrates, after the last substrate of the starting lot has finished the heat treatment in the second heating module, the second heating module In changing the heating temperature to a temperature corresponding to the substrate of the subsequent lot, the first substrate following the first substrate is transferred from the transfer cycle next to the transfer cycle in which the first substrate of the subsequent lot is transferred to the second temperature control module. After changing the heating temperature of the second heating module so that the retreat module is sequentially filled with the substrate heat-treated by the heating module of 1 Information, configuration for conveying the successive downstream module substrate in said buffer module has been proposed. However, in this configuration, since the substrate is kept waiting in the retraction module, there is a case where it takes a long time to complete all processing on the wafer, and the problem of the present invention cannot be solved.

JP 2004-193597 A Japanese Patent Laid-Open No. 2008-34746

The present invention has been made under such circumstances, and a purpose thereof is a technique capable of improving throughput when settling processing is performed in a settling target module between a starting lot and a succeeding lot. Is to provide.

For this reason, the coating and developing apparatus according to the present invention has a carrier mounting portion on which a carrier containing a plurality of substrates is placed, and a delivery means for delivering the substrate to and from the carrier, and the carrier placement portion. Forming a coating film on the substrate delivered from and having a processing section for developing the substrate after exposure,
In the processing unit, the substrate is transferred to the temperature control module for controlling the temperature of the substrate, the application module for applying the coating liquid to the substrate, the heating module for heating the substrate, and the development module for performing the development process on the substrate. Transport the
If the place where the substrate is placed is called a module, based on a preset transfer schedule, the substrate transfer means forms a state in which the substrate with the smaller order is located in the module downstream of the substrate with the larger order. In the coating and developing apparatus in which the substrate is transported by executing one transport cycle and completing the transport cycle and then performing the next transport cycle.
After the processing of the first lot substrate, which is composed of at least one of the coating module and the heating module and is dispensed from one carrier, in the module, before the next lot substrate is transported to the module. , A settling target module for which settling processing is performed in the module, and
In the transfer schedule, after transferring the last substrate of the first lot to the processing unit, one transfer cycle is executed for the time required for the settling process until the first substrate of the subsequent lot is transferred to the processing unit. Means for creating a transport schedule so that the number of delay cycles obtained by dividing by the cycle time, which is the maximum time required when performing the operation, is made free of cycles,
In the created transport schedule, the execution cycle that is a cycle in which settling processing is performed in the settling target module and that has remaining time for settling processing in the settling target module ends, and the next cycle Before starting the operation, an appropriate time for executing the next cycle is obtained for each settling target module, and the longest appropriate time is compared with the execution time for executing the execution cycle. Is long, the substrate transport means is controlled to wait for the start of the next cycle of the execution cycle for a time corresponding to the difference between the appropriate time and the execution time. And

  At this time, the appropriate time is {(settling processing remaining time in the settling target module) + (execution time of the execution cycle) − (substrate transfer in a cycle in which the substrate of the subsequent lot is loaded into the settling target module). Time required for the means to deliver the substrate)} / (number of cycles from the execution cycle to the cycle in which the wafer of the next lot is loaded into the set target module). The start of the next cycle means that the substrate transfer means receives the substrate transferred from the carrier placement unit to the processing unit. For example, the settling target module is a heating module, and the settling process is a heating temperature changing process.

In addition, the coating and developing method of the present invention includes a carrier mounting unit on which a carrier containing a plurality of substrates is mounted, and a transfer unit that transfers the substrate to and from the carrier, and the carrier mounting unit. Forming a coating film on the transferred substrate and developing the exposed substrate;
In the processing unit, the substrate is transferred to the temperature control module for controlling the temperature of the substrate, the application module for applying the coating liquid to the substrate, the heating module for heating the substrate, and the development module for performing the development process on the substrate. Transport the
If the place where the substrate is placed is called a module, based on a preset transfer schedule, the substrate transfer means forms a state in which the substrate with the smaller order is located in the module downstream of the substrate with the larger order. In the coating and developing method in which the substrate is transported by executing one transport cycle and completing the transport cycle and then performing the next transport cycle.
After the processing of the first lot substrate, which is composed of at least one of the coating module and the heating module and is dispensed from one carrier, in the module, before the next lot substrate is transported to the module. , Including a settling target module in which settling processing is performed in the module,
In the transfer schedule, after transferring the last substrate of the first lot to the processing unit, one transfer cycle is executed for the time required for the settling process until the first substrate of the subsequent lot is transferred to the processing unit. Creating a transport schedule so that the number of delay cycles obtained by dividing by the cycle time, which is the maximum time required when performing,
In the created transport schedule, the execution cycle that is a cycle in which settling processing is performed in the settling target module and that has remaining time for settling processing in the settling target module ends, and the next cycle Before starting the operation, an appropriate time for executing the next cycle is obtained for each settling target module, and the longest appropriate time is compared with the execution time for executing the execution cycle. A step of controlling the substrate transfer means so as to wait for the start of the next cycle of the execution cycle by a time corresponding to the difference between the appropriate time and the execution time. And
At this time, the appropriate time is {(settling processing remaining time in the settling target module) + (execution time of the execution cycle) − (substrate transfer in a cycle in which the substrate of the subsequent lot is loaded into the settling target module). Time required for the means to deliver the substrate)} / (number of cycles from the execution cycle to the cycle in which the wafer of the next lot is loaded into the set target module).

  Furthermore, in the storage medium of the present invention, the processing unit forms a coating film on the substrate received from the carrier mounting unit on which the carrier containing a plurality of substrates is mounted, and develops the exposed substrate. A storage medium storing a computer program used in a coating and developing apparatus, wherein the program has a group of steps so as to execute the coating and developing method.

As described above, in the present invention, when the substrate of the starting lot and the substrate of the subsequent lot are processed by the same set target module, the processing for the substrate of the starting lot is performed after finishing the processing for the substrate of the starting lot. When the settling process is performed in the set target module before, the throughput can be improved by transporting the substrate of the subsequent lot to the set target module immediately after the settling process of the module is completed.

  First, a resist pattern forming apparatus 2 in which an exposure apparatus is connected to the coating and developing apparatus of the present invention will be described with reference to the drawings. FIG. 1 shows a plan view of an embodiment of the apparatus, and FIG. 2 is a schematic perspective view thereof. In the figure, B1 is a carrier mounting part for carrying in / out a carrier C in which, for example, 13 sheets of wafers W are hermetically stored, and a carrier station capable of mounting a plurality of mounting parts 21 of the carrier C side by side. 22, an opening / closing part 23 provided on the wall surface in front of the carrier station 22, and a delivery means 24 for taking out the wafer W from the carrier C and delivering it to the processing part B 2 described later.

  A processing unit B2 surrounded by a casing 25 is connected to the back side of the carrier mounting unit B1, and heating / cooling system modules are multi-staged sequentially from the front side to the processing unit B2. The shelf modules U1, U2, and U3, and the main arm A (A1, A2) that constitutes a substrate transfer means for transferring the wafer W between the modules of the shelf modules U1 to U3 and liquid processing modules U4 and U5 described later. They are arranged alternately. That is, the shelf modules U1, U2, U3 and the main arms A1, A2 are arranged in a line in the front-rear direction as viewed from the carrier mounting part B1, and an opening for wafer transfer (not shown) is formed at each connection part. The wafer W can freely move in the processing section B2 from the shelf module U1 on one end side to the shelf module U3 on the other end side.

  The shelf modules U1, U2, and U3 have a configuration in which various modules for performing pre-processing and post-processing of the processing performed in the liquid processing modules U4 and U5 are stacked in a plurality of stages, for example, 10 stages. Includes a delivery module TRS, a temperature control module CPL for adjusting the wafer W to a predetermined temperature, a heating module CLH for performing a heat treatment of the wafer W, and a heating module for performing a heat treatment of the wafer W after application of the resist solution. A CPH, a heating module PEB that heat-processes the wafer W before the developing process, a heating module POST that heat-processes the wafer W after the developing process, and the like are included.

  Further, for example, as shown in FIG. 2, the liquid processing modules U4 and U5 are an antireflection film forming module BCT for applying a chemical solution for forming an antireflection film to the wafer W, and a coating module COT for applying a resist solution to the wafer W. The developing module DEV and the like for supplying a developing solution to the wafer W and performing development processing are stacked in a plurality of stages, for example, five stages.

  An exposure unit B4 is connected to the back side of the shelf module U3 in the processing unit B2 via an interface unit B3. This interface unit B3 is composed of a first transfer chamber 31 and a second transfer chamber 32 provided in the front and rear between the processing unit B2 and the exposure unit B4, and can be moved up and down and rotated around a vertical axis, respectively. A first transfer arm 33 and a second transfer arm 34 that are freely movable and retractable are provided. Further, the first transfer chamber 31 is provided with a shelf module U6 in which, for example, delivery modules and the like are stacked one above the other.

The heating module CPH includes, for example, a heating plate for placing and heating the wafer W thereon and a cooling plate that also serves as a transfer arm, and the wafer W between the main arm A and the heating plate is provided. An apparatus having a configuration in which delivery is performed by a cooling plate, that is, heating and cooling can be performed by one module is used.
The main arm A will be described. This main arm A is used for all the modules in the processing section B2 (where the wafer W is placed), for example, each processing module of the shelf modules U1 to U3 and each module of the liquid processing modules U4 and U5. It is configured to deliver. For this purpose, it is configured to be movable back and forth, vertically movable, rotatable about the vertical axis, movable in the Y axis direction, and has two holding arms for supporting the peripheral area on the back surface side of the wafer W. These holding arms are configured to advance and retract independently of each other.

  An example of the flow of the wafer W in such a resist pattern forming system will be described with reference to FIG. 3. The wafer W in the carrier C placed on the carrier placement unit B1 is stored in the shelf unit U1 of the processing unit S2. Passed to the delivery module TRSA, from here temperature control module CPL → antireflection film forming module BCT → heating module CLH → temperature control module CPL → coating module COT → delivery module TRS → heating module CPH → interface part B3 → exposure part B4 The exposure process is performed here. On the other hand, the wafer W after the exposure processing is returned to the processing unit B2, and is transferred by the path of the heating module PEB → temperature control module CPL → development module DEV → heating module POST → temperature control module CPL → shelf unit U1 delivery module TRSA. From here, it is returned to the carrier C of the carrier mounting portion B1.

  At this time, in the processing unit B2, the main arm A (A1, A2) receives the wafer from the delivery module TRSA of the shelf unit U1, and passes the wafer along the transfer path described above via the temperature control module CPL and the like. Then, after sequentially transporting to the heating module CPH, the wafer W after the exposure processing is received from the interface unit B3, and the wafer is sequentially transported to the delivery module TRSA along the above-described transport path via the heating module PEB and the like. Thus, the conveyance cycle is performed in the processing unit B2. In this transfer cycle, as shown in FIG. 3, the transfer from the transfer module TRSA to the temperature control module CPL is the first transfer by the main arm A, and in this case, the transfer module TRSA becomes the transfer cycle start module. Since the wafer W is delivered to the delivery module TRSA from the carrier mounting part B1, delivery of the wafer W to the delivery module TRSA means delivery of the wafer W to the processing part B2. By receiving the main arm A from the TRSA, the transfer cycle is started.

  The resist pattern forming apparatus described above manages recipes for each processing module, manages recipes for the transfer flow (carrying path) of the wafer W, processes in each processing module, delivery means 24, main arms A1, A2, etc. The control part 4 which consists of a computer which performs drive control of this is provided. The control unit 4 has a program storage unit made up of, for example, a computer program, and the program storage unit is used for the operation of the entire resist pattern forming apparatus, ie, for forming a predetermined resist pattern on the wafer W. A program made of software having a group of steps (commands) is stored so that processing in each processing module, transfer of the wafer W, and the like are performed. Then, by reading these programs to the control unit 4, the operation of the entire resist pattern forming apparatus is controlled by the control unit 4. The program is stored in the program storage unit while being stored in a storage medium such as a flexible disk, a hard disk, a compact disk, a magnetic optical disk, or a memory card.

  FIG. 4 shows the configuration of the control unit 4, which actually includes a CPU (central processing module), a program, a memory, and the like. The present invention is characterized by the transfer of the wafer W before the development processing. Therefore, here, a part of the constituent elements related to it will be explained as a block. In FIG. 4, reference numeral 40 denotes a bus, to which a recipe storage unit 41, a recipe selection unit 42, a settling processing unit 43, a conveyance schedule creation unit 44, a standby control unit 45, and a conveyance control unit 46 are connected.

The recipe storage unit 41 is a part corresponding to a storage unit, and stores, for example, a transfer recipe in which a transfer route of the wafer W is recorded, and a plurality of recipes in which processing conditions to be performed on the wafer W are recorded. . The recipe selection unit 42 is a part for selecting an appropriate one from the recipes stored in the recipe storage unit 41. For example, the number of wafers processed, the type of resist, the temperature at the time of heat processing, and the like can be input. .
After the wafer A of one lot (hereinafter referred to as “lot A”), which is a set of a plurality of substrates of the same type dispensed from one carrier, completes a predetermined process in the module to be settled. , And a means for outputting a command to the effect that settling processing is performed on the module. The settling process refers to a process for adjusting the module state, such as a temperature changing process or an adjusting process such as a dummy dispensing process in the coating module COT. In this example, the module to be set is the heating module CPH, and the settling process in this module is a process of changing the heating temperature to a temperature corresponding to the wafer B of another subsequent lot (hereinafter referred to as “lot B”). is there. Therefore, a command to change the temperature of the heating plate is output to the heating module CPH after the heating process in the heating module CPH of the wafer A of the lot A is completed.

  Based on the transfer recipe, the transfer schedule creation unit 44 assigns the order of the wafers to all modules in the lot at which timing and to which module, for example, assigns the order to the wafer, and associates the wafer order with each module. It is means for creating a transportation schedule created by arranging transportation cycle data specifying transportation cycles in time series. At this time, in the transfer schedule creation unit 44, after the last wafer A of the starting lot A is delivered to the processing unit B1, the first wafer B of the succeeding lot B is transferred to the processing unit B1. A transport schedule is created so that the number of delay cycles obtained by dividing the time required for the settling process by the cycle time, which is the maximum time required for executing one transport cycle, is left.

The standby control unit 45 ends the predetermined execution cycle in the transfer schedule, obtains an appropriate time for executing the next cycle for each settling target module before starting the next cycle, If the appropriate time is long by comparing the long appropriate time with the execution time of the execution cycle, it waits for the start of the next cycle of the execution cycle for a time corresponding to the difference between the appropriate time and the execution time. Means for controlling the main arm A.
The transfer control unit 46 refers to the transfer schedule and controls the transfer means 24 and the main arms A1 and A2 so as to transfer the wafer written in the transfer cycle data to the module corresponding to the wafer. Means for executing the transfer cycle.

  Subsequently, the operation of the present embodiment will be described with reference to FIGS. First, the operator selects a recipe before starting the processing on the wafer W as a substrate. Here, as described above, an antireflection film is formed as a coating film, and a resist film is formed thereon. A case will be described as an example. Since the present invention is characterized by the transfer path of the wafer W to the settling target module, the transfer to the heating module CPH will be described below by taking as an example a case where the temperature setting process is performed on the heating module CPH after forming the resist film. Description will be made with attention to the route.

First, as shown in FIG. 5, the operator applies an antireflection film and a resist film to the five wafers A1 to A5 of the lot A and the five wafers B1 to B5 of the subsequent lot B. A recipe for forming a film is selected (step S1). Next, the conveyance schedule creation unit 44 creates a conveyance schedule for lot A and lot B based on the selected recipe (step S2).
At this time, a transfer schedule is created between the lot A and the lot B so as to delay the delivery of the wafer from the carrier platform B1 to the delivery module TRSA by the number of delay cycles obtained by the following equation (2).
Number of delay cycles = settling time / cycle time (2)
The settling time is the time required for the settling process, and in this example, the time required for the temperature settling process of the heating module CPH is, for example, 90 seconds. The cycle time refers to the maximum time required to execute one transport cycle of the transport schedule, and in this example is 22.8 seconds. Therefore, the number of delay cycles = 90 seconds ÷ 22.8 seconds = 3.95, which is raised to 4.

Here, since the slowest process time (the time obtained by adding the wafer transfer time to the module and the time required for processing) among the modules in the processing unit B1 becomes the rate-determining time in the transfer cycle, this rate-limiting time is the cycle. It will be time.
An example of the conveyance schedule is shown in FIG. In this figure, the vertical axis represents the cycle, and the horizontal axis represents each module in the order along the transfer path of the wafer W. In a different type of module, the left module in FIG. As the module goes to the right, it becomes a downstream module. Further, BCT1 and BCT2 in the conveyance schedule mean that two antireflection film forming modules are used, and CPH1 to CPH5 mean that five heating modules are used.

  The main arm A has two or more holding arms, and the wafers in the lower order are transferred from the wafers in the downstream module to the modules in the lower order, so that the wafers in the lower order are more downstream than the wafers in the higher order. The state located in the module on the side is formed, thereby executing one cycle (conveying cycle), and after completing the cycle, the process proceeds to the next cycle, and each cycle is sequentially executed. The wafers are sequentially transferred along the path so that predetermined processing is performed.

  In this transfer schedule, the first wafer A01 of lot A is loaded into the antireflection film forming module BCT1 in cycle 3, and the wafer A01 is also processed in the antireflection film forming module BCT1 in cycle 4. In cycle 5, the wafer A01 is unloaded from the antireflection film forming module BCT1 by one holding arm of the main arm A, and the wafer A03 held by the other holding arm of the main arm A is formed of the antireflection film. Then, the wafer A01 held on the one holding arm is carried into the heating module CLH1 which is one module downstream of the antireflection film forming module BCT2.

  Returning to the description of the number of delay cycles, the number of delay cycles is 4 as described above, and therefore a transfer schedule is created so as to delay the delivery of the wafer from the carrier B1 to the delivery module TRSA by the number of delay cycles. . That is, the transfer schedule of the first wafer B01 of the lot B is such that after the last wafer A05 of the lot A is transferred to the transfer module TRSA, the cycle number 4 is set as an empty cycle and then transferred to the transfer module TRSA. Created. That is, after the last wafer A05 of lot A is delivered to the delivery module TRSA in cycle 5, the cycle number 4 is emptied as an empty cycle, and then the first wafer B01 of lot B is delivered to the delivery module TRSA in cycle 10. It will be.

  Next, the control unit 4 outputs an instruction to each unit while referring to the created transfer schedule, executes the process for the wafer A of the lot A (step S3), and continues to the cycle 22 according to the transfer schedule. At this time, the temperature settling process of the heating module CPH1 is started in the cycle 22 (step S4). The hatched portion in the transport schedule in FIG. 6 means that the temperature settling process is being executed.

  Subsequently, at the end of the execution cycle that satisfies both of the following conditions (1) and (2), the standby control unit 45 determines whether to perform standby control of the main arm A before the next cycle starts. To do. Here, before the next cycle starts is when the main arm A returns to the position facing the transfer module TRSA, which is the transfer module start module, and the next cycle is about to start. The standby control of the main arm A refers to controlling the main arm A to wait for a predetermined time for the reception of the wafer from the delivery module TRSA.

Condition (1) There is a past history that the settling process was performed in a certain module to be set. Condition (2) There is a remaining time for the settling process. The fact that the settling process has been performed in the settling target module means that the settling process has been performed in the setting module, and in this example, in the heating module CPH1, the settling process is performed in cycle 22. Since a certain temperature settling process has been started, when the cycle 22 is completed, there is a past history that the settling process has been performed in the heating module CPH1. Therefore, in the conveyance schedule shown in the figure, the end of the cycle satisfying the condition (1) is the end of cycle 22 to cycle 29.

  Regarding the condition (2), in this example, in the heating module CPH1, the temperature setting, which is the settling process, is completed in the cycle 25, and therefore, the cycle 22 to the cycle 24 are cycles in which the remaining time for the settling process exists. Therefore, in the conveyance schedule shown in the figure, the end of the cycle satisfying the condition (2) is the end of cycle 22 to cycle 28.

  As described above, in the transfer schedule, the end of the execution cycle satisfying both the above conditions (1) and (2) is the end of the execution cycle 22 to the cycle 28. In 28, before starting the next cycles 23 to 29, the appropriate time T2 of the main arm A is calculated, and it is determined whether or not the standby control of the main arm A is performed based on the calculation result. Here, the appropriate time T2 is an ideal time for the main arm A to execute the next cycle of the execution cycle, and is calculated based on the following equation (3).

Appropriate time T2 = (I + II−III) ÷ IV (3)
I: Settling processing remaining time in the target module
II: Execution time of execution cycle
III: Transfer time of the main arm A in the cycle in which the wafer B of the subsequent lot B is carried into the set target module
IV: The number of cycles from the execution cycle until the wafer B of the subsequent lot B is loaded into the set target module. Specifically, the appropriate time of the main arm A when the cycle 22 is finished and the cycle 23 is about to start. The calculation of T2 will be described. In this case, the execution cycle is cycle 23, the settling target module is the heating module CPH1, and I to IV are as follows. Note that the execution time (II) of the execution cycle is the time required when the execution cycle is actually executed, and this execution time changes because the control for carrying at regular intervals is not performed. .
I: 73 seconds
II: Execution time of execution cycle 20 is 26 seconds
III: The cycle in which the wafer B01 is carried into the heating module CPH1 is the cycle 26, and the wafers W transferred in the cycle 26 are B05, B02, B01, and the transfer time is 9.5 seconds.
IV: The number of cycles from the execution cycle 22 to the cycle 26 in which the wafer B01 is carried into the heating module CPH1 is 4 at (26-22).
Thus, the appropriate time T2 is calculated as T2 = (73 + 26−9.5) ÷ 4 = 22.375 seconds → 22.4 seconds from the equation (3) (step S5).
Whether or not the standby control of the main arm A is performed is compared with the appropriate time T2 and the execution time (26 seconds) of the execution cycle 22, and when the appropriate time T2 is longer, the standby control of the main arm A is performed. If it is short, it is determined that the standby control is not executed. In this example, since the appropriate time T2 <execution time, it is determined that the standby control is not executed, and the next cycle 23 is executed without performing the standby control of the main arm A (step S6).

  Next, similarly, the standby control of the main arm when the cycle 23 ends and the cycle 24 is about to start will be described. In this case, the execution cycle is cycle 23, and the settling target modules are the heating module CPH1 and the heating module CPH2, and calculate the appropriate time T2 in each case (step S7), whichever is longer It is determined whether or not standby control of the main arm is to be performed by comparing the time T2 and the execution time of the execution cycle 23 (step S8).

First, regarding the heating module CPH1, I to IV are as follows.
I: 53 seconds
II: Execution time of execution cycle 23 is 20 seconds
III: Since the wafer B01 is carried into the heating module CPH1 in the cycle 26, the transfer time is 9.5 seconds as described above.
IV: The number of cycles from the execution cycle 23 to the cycle 26 in which the wafer B01 is carried into the heating module CPH1 is (26-23), 3
Thus, the appropriate time T2 is calculated as T2 = (53 + 20−9.5) ÷ 3 = 21.167 seconds → 21.2 seconds from the equation (3).
Similarly, for the heating module CPH2, I to IV are as follows.
I: 77 seconds
II: Execution time of execution cycle 23 is 20 seconds
III: The wafer B02 is carried into the heating module CPH2 in the cycle 27, and the wafers W transferred in the cycle 27 are B02 and B03, and the transfer time is 6 seconds.
IV: The number of cycles from the execution cycle 23 to the cycle 27 in which the wafer B02 is carried into the heating module CPH2 is (27-23), which is 4
Accordingly, the appropriate time T2 is calculated as T2 = (77 + 20−6) /4=seconds→22.75 seconds → 22.8 seconds from the equation (3).
Thus, since the appropriate time T2 in the heating module CPH1 is 21.2 seconds and the appropriate time T2 in the heating module CPH2 is 22.8 seconds, the longer appropriate time T2 (22.8 seconds) and execution of the execution cycle 23 are performed. Compare with time (20 seconds). In this case, since the appropriate time T2> the execution time, the standby time T3 of the main arm is obtained from the appropriate time T2-execution time. In this case, the standby time T3 is obtained as 22.8 seconds-20 seconds = 2.8 seconds. For example, the standby time T3 is rounded up and the standby control of the main arm A is performed for 3 seconds. That is, in this example, when the execution cycle 23 is completed and the next cycle 24 is to be started, the time corresponding to the standby time at the position where the main arm A faces the delivery module TRSA which is the start point of the cycle. (3 seconds) After the standby adjustment by the timer, the wafer B01 is received from the transfer module TRSA, and thus the cycle 24 is started (step S8).

Next, standby control of the main arm A when the cycle 24 ends and the cycle 25 is about to start will be described. In this case, the settling target modules are the heating module CPH1, the heating module CPH2, and the heating module CPH3, and the execution cycle is the cycle 24.
First, regarding the heating module CPH1, I to IV are as follows.
I: 33 seconds
II: Execution time of execution cycle 24 is 20 seconds
III: The wafer B01 is loaded into the heating module CPH1 in the cycle 26, and the transfer time in the cycle 26 is 9.5 seconds as described above.
IV: The number of cycles from the execution cycle 24 to the cycle 26 in which the wafer B01 is carried into the heating module CPH1 is 2 (26-24).
As a result, the appropriate time T2 is obtained from the equation (3) as T2 = (33 + 20−9.5) ÷ 2 = 21.15 seconds → 21.8 seconds.
Next, for the heating module CPH2, I to IV are as follows.
I: 57 seconds
II: Execution time of execution cycle 24 is 20 seconds
III: The wafer B02 is loaded into the heating module CPH2 in cycle 27, and in this cycle 27, the transfer time is 6 seconds as described above.
IV: The number of cycles from the execution cycle 24 to the cycle 27 in which the wafer B02 is carried into the heating module CPH2 is (27-24), 3
As a result, the appropriate time T2 is obtained from the equation (3) as T2 = (57 + 20−6) ÷ 3 = 23.67 seconds → 23.7 seconds.
Finally, regarding the heating module CPH3, I to IV are as follows.
I: 76 seconds
II: Execution time of execution cycle 24 is 20 seconds
III: The wafer B03 is loaded into the heating module CPH3 in cycle 28, and the wafers W transferred in this cycle 28 are B04 and B03, and the transfer time is 6 seconds.
IV: The number of cycles from the execution cycle 24 to the cycle 28 in which the wafer B03 is carried into the heating module CPH3 is 4 in (28-24).
As a result, the appropriate time T2 is calculated as T2 = (76 + 20−6) ÷ 4 = 22.5 seconds from the equation (3).

  Thus, the appropriate time T2 in the heating module CPH1 is 21.8 seconds, the appropriate time T2 in the heating module CPH2 is 23.7 seconds, and the appropriate time T2 in the heating module CPH3 is 22.5 seconds (step S9). The long appropriate time T2 (23.7 seconds) is compared with the execution time of the execution cycle 24 (20 seconds). In this case, since the appropriate time T2> the execution time, the standby time T3 (3.7 seconds → 4 seconds) of the main arm A is obtained from the appropriate time T2−the execution time, and the main arm A waits for 4 seconds. Then, the next cycle 25 is started (step S10).

As described above, the cycle 22 to the cycle 28 are set as execution cycles, these execution cycles are terminated, and before starting the next cycle, an appropriate time for executing the next cycle is determined for each settling target module. When the appropriate time is long by comparing the longest appropriate time with the execution time of the execution cycle, the time corresponding to the difference between the appropriate time and the execution time, the start of the next cycle of the execution cycle The remaining cycles are executed according to the above-described transfer schedule while controlling the main arm A so as to wait.
In such a resist pattern forming apparatus, the processing of the wafer A of the first lot A and the wafer B of the second lot B is successively performed in the processing unit S2. Even when the settling process in the module to be set is performed between the process for the wafer B of the lot B and the process for setting the wafer B to the module B, the occurrence timing of the transfer timing of the wafer B to the module being advanced or delayed is suppressed. Can do.

  That is, when the transfer schedule is created, the wafer W is discharged from the carrier mounting unit B1 to the processing unit B2 after a cycle corresponding to the time required for the settling process, so that the transfer of the wafer B to the module is performed. It is possible to suppress the occurrence of a situation where the timing is advanced and the wafer B is transferred to the module before the settling process is completed.

  Thus, since the wafer B is prevented from being transferred to the module before the settling process is completed, the wafer B cannot be delivered to the module, and the main arm A holds the wafer B. Therefore, it is possible to suppress the occurrence of a situation where the vehicle cannot wait for the transfer cycle and stop. Accordingly, the transfer schedule can be sequentially executed in a stable state without stopping the main arm A, so that the transfer of the wafer can be performed smoothly and the throughput can be improved.

  Further, in a cycle satisfying a predetermined condition, an appropriate time T2 for executing the next cycle is obtained, and when this time is longer than the execution time of the execution cycle, an appropriate time T2—the amount corresponding to the execution time, Control by the timer of the main arm A so as to wait for reception of the wafer W from the start module can suppress the transfer timing of the wafer B to the module, and immediately after the settling process is completed. Wafer B01 can be loaded into the settling target module. For this reason, it is possible to suppress an unnecessarily large transfer interval between the starting lot A and the wafer A, and to prevent a delay in supplying the wafer to the exposure apparatus. As described above, since the wafer can be smoothly transferred from the processing unit B1 to the exposure apparatus B4, the throughput can be improved also in this respect.

  Here, as shown in the above-described equation (3), the appropriate time is determined by taking into account past circumstances such as the remaining settling time in the set target module and the execution time of the execution cycle. This is the ideal time to execute the cycle. Then, at the end of the execution cycle, the appropriate time is obtained, and the appropriate time is compared with the execution time, and the standby control of the main arm is performed only when the appropriate time is long. It is possible to review the time for performing this cycle, and control can be performed so as to wait for the start of the next cycle for a necessary minimum time when necessary. On the other hand, in the conventional control method, the control is performed based on the cycle time which is the maximum time of the transport cycle. Therefore, the standby time is compared with the case where the appropriate time is obtained for each execution cycle as in the present invention. It becomes too long, and it takes a long time for the wafer B to be loaded into the set target module after the module settling process is completed.

  In the above, a coating module other than a heating module can be used as the settling target module of the present invention. The coating module holds the wafer W rotatably by a spin chuck, drops a coating liquid from a coating nozzle on the wafer W on the spin chuck, and rotates the wafer W to rotate the wafer W. In this case, the settling process is a dummy dispensing process in which the coating liquid is preliminarily discharged from the nozzles before the coating liquid is supplied to the substrate. The settling process includes all preparatory processes for wafer processing such as a resist solution temperature adjustment process and a peripheral exposure apparatus illuminance settling process.

  Furthermore, the present invention separates a block for forming a resist film, including a resist solution coating unit and an antireflection film forming unit, and a block for performing a development process, so that the wafer is transported from the carrier block to the exposure apparatus. The present invention can also be applied to the transfer control of the wafer W in the coating and developing apparatus in which the path and the transfer path from the exposure apparatus to the carrier block are independently formed. The present invention can also be applied to a coating and developing apparatus for processing a substrate such as a glass substrate (LCD substrate) for a liquid crystal display as well as a semiconductor wafer.

1 is a plan view showing an embodiment of a resist pattern forming apparatus according to the present invention. It is a perspective view which shows the said resist pattern formation apparatus. It is a top view which shows the conveyance path | route of the wafer W in the process part in the said resist pattern formation apparatus. It is a block diagram which shows a part of control part in the said resist pattern formation apparatus. It is process drawing for demonstrating the effect | action of the said resist pattern formation apparatus. It is a conveyance schedule which shows an example of the conveyance schedule used with the said resist pattern formation apparatus. It is a top view which shows the conventional application | coating and developing apparatus. It is a block diagram which shows an example of the conventional conveyance schedule.

Explanation of symbols

W Semiconductor wafer C Carrier B1 Carrier placement unit B2 Processing unit B3 Interface unit B4 Exposure unit A1, A2 Main arm 24 Transfer means 4 Control unit 43 Settling processing unit 44 Transfer schedule creation unit 45 Standby control unit 46 Transfer control unit

Claims (7)

A carrier containing a plurality of substrates is placed, and a carrier placement unit having delivery means for delivering the substrate to and from the carrier, and a coating film is formed on the substrate delivered from the carrier placement unit And a processing unit for performing development on the substrate after exposure,
In the processing unit, the substrate is transferred to the temperature control module for controlling the temperature of the substrate, the application module for applying the coating liquid to the substrate, the heating module for heating the substrate, and the development module for performing the development process on the substrate. Transport the
If the place where the substrate is placed is called a module, based on a preset transfer schedule, the substrate transfer means forms a state in which the substrate with the smaller order is located in the module downstream of the substrate with the larger order. In the coating and developing apparatus in which the substrate is transported by executing one transport cycle and completing the transport cycle and then performing the next transport cycle.
After the processing of the first lot substrate, which is composed of at least one of the coating module and the heating module and is dispensed from one carrier, in the module, before the next lot substrate is transported to the module. , A settling target module for which settling processing is performed in the module, and
In the transfer schedule, after transferring the last substrate of the first lot to the processing unit, one transfer cycle is executed for the time required for the settling process until the first substrate of the subsequent lot is transferred to the processing unit. Means for creating a transport schedule so that the number of delay cycles obtained by dividing by the cycle time, which is the maximum time required when performing the operation, is made free of cycles,
In the created transport schedule, the execution cycle that is a cycle in which settling processing is performed in the settling target module and that has remaining time for settling processing in the settling target module ends, and the next cycle Before starting the operation, an appropriate time for executing the next cycle is obtained for each settling target module, and the longest appropriate time is compared with the execution time for executing the execution cycle. Is long, the substrate transport means is controlled to wait for the start of the next cycle of the execution cycle for a time corresponding to the difference between the appropriate time and the execution time. A coating and developing apparatus. The appropriate time is {(the remaining settling time in the settling target module) + (the execution time of the execution cycle) − (the cycle in which the substrate of the subsequent lot is loaded into the settling target module) 2. The time required for delivering the substrate)} ÷ (the number of cycles from the execution cycle to the cycle in which the wafer of the subsequent lot is loaded into the set target module). Application and development equipment.   3. The coating and developing apparatus according to claim 1, wherein the start of the next cycle is that the substrate transport unit receives the substrate transferred from the carrier mounting unit to the processing unit.   The coating / developing apparatus according to claim 1, wherein the set target module is a heating module, and the settling process is a heating temperature changing process. A carrier containing a plurality of substrates is placed, and a carrier placement unit having delivery means for delivering the substrate to and from the carrier, and a coating film is formed on the substrate delivered from the carrier placement unit And a processing unit for performing development on the substrate after exposure,
In the processing unit, the substrate is transferred to the temperature control module for controlling the temperature of the substrate, the application module for applying the coating liquid to the substrate, the heating module for heating the substrate, and the development module for performing the development process on the substrate. Transport the
If the place where the substrate is placed is called a module, based on a preset transfer schedule, the substrate transfer means forms a state in which the substrate with the smaller order is located in the module downstream of the substrate with the larger order. In the coating and developing method in which the substrate is transported by executing one transport cycle and completing the transport cycle and then performing the next transport cycle.
After the processing of the first lot substrate, which is composed of at least one of the coating module and the heating module and is dispensed from one carrier, in the module, before the next lot substrate is transported to the module. , Including a settling target module in which settling processing is performed in the module,
In the transfer schedule, after transferring the last substrate of the first lot to the processing unit, one transfer cycle is executed for the time required for the settling process until the first substrate of the subsequent lot is transferred to the processing unit. Creating a transport schedule so that the number of delay cycles obtained by dividing by the cycle time, which is the maximum time required when performing,
In the created transport schedule, the execution cycle that is a cycle in which settling processing is performed in the settling target module and that has remaining time for settling processing in the settling target module ends, and the next cycle Before starting the operation, an appropriate time for executing the next cycle is obtained for each settling target module, and the longest appropriate time is compared with the execution time for executing the execution cycle. A step of controlling the substrate transfer means so as to wait for the start of the next cycle of the execution cycle by a time corresponding to the difference between the appropriate time and the execution time. Coating and developing method. The appropriate time is {(the remaining settling time in the settling target module) + (the execution time of the execution cycle) − (the cycle in which the substrate of the subsequent lot is loaded into the settling target module) 6. The time required for delivering the substrate)} / (the number of cycles from the execution cycle to the cycle in which the wafer of the subsequent lot is loaded into the set target module). Application and development methods. A computer used in a coating and developing apparatus for forming a coating film on a substrate received from a carrier placement unit on which a carrier containing a plurality of substrates is placed in a processing unit and developing the exposed substrate. A storage medium storing a program, wherein the program has a group of steps so as to execute the coating and developing method according to claim 5 or 6.

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